JPS6260230A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6260230A JPS6260230A JP19913585A JP19913585A JPS6260230A JP S6260230 A JPS6260230 A JP S6260230A JP 19913585 A JP19913585 A JP 19913585A JP 19913585 A JP19913585 A JP 19913585A JP S6260230 A JPS6260230 A JP S6260230A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- nitride film
- sidewall
- nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 1一 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] [Industrial application field] 11 The present invention relates to a method for manufacturing a semiconductor device.
本発明は半導体装置θ製造にお^て、ゲート電極を先に
形成し、セルファラインで素子分離用酸化膜を形成する
ことにより、ゲート電比とフィールド領域Qアライメン
ト余裕を0にし、微細化に好都合な素子の形成を提供し
たものである。In the semiconductor device θ manufacturing process, the present invention first forms the gate electrode and then forms an oxide film for element isolation in the self-alignment line, thereby reducing the gate voltage ratio and the field region Q alignment margin to 0, which facilitates miniaturization. This provides convenient device formation.
従来の半導体装置の製造方法は公知のように先に素子分
離用酸化膜を形成し、その後にフィールド領域にゲート
電極を形成していた。(第2図)〔発明が解決しようと
する問題点及び目的〕しかし、前述の従来技術では、フ
ィールド領域に対してゲート電極を合わせ余裕を考慮し
て配置しなければならないので、トランジスタ部分の微
細化が困難となっていた。そこで本発明はこのような問
題点を解決するもOで、そQ目的とするところはゲー)
1[1fとフィールド領域の合わせ余裕1−0にし、ト
ランジスタ部分の容易な微細化を提供するところにおる
。As is well known, in the conventional manufacturing method of a semiconductor device, an oxide film for element isolation is first formed, and then a gate electrode is formed in a field region. (Fig. 2) [Problems and objectives to be solved by the invention] However, in the above-mentioned conventional technology, the gate electrode must be aligned with the field region and arranged with allowances in mind, so the fineness of the transistor part is reduced. It was becoming difficult to adapt. Therefore, the present invention is intended to solve these problems, but its purpose is to solve the problems described above.
The alignment margin between 1[1f and the field region is set to 1-0 to provide easy miniaturization of the transistor portion.
本発明の半導体装置の製造方法は、−導電型の半導体基
板上に第1の酸化膜を形成する工程と、該第1の酸化膜
上に不純物をドープした多結晶シリコンを形成する工程
と、該多結晶シリコン上に哨2の酸化膜を形成する工程
と、該第2の酸化膜」二に@1の窒化膜を形成する工程
と、#第1の窒化膜、帆20酸化模、多結晶シリコンの
一部を選択除去する工程と、該多結晶シリコンの側壁に
嬶3の酸化膜全形成する工程と、第2θ窒化膜を形成す
る工程と、該第2の窒化膜の一部を選択除去する工程と
、該除去部に嬉4の酸化膜を形■する工程とを具備した
ことを特数とする。A method for manufacturing a semiconductor device of the present invention includes: forming a first oxide film on a -conductivity type semiconductor substrate; forming polycrystalline silicon doped with impurities on the first oxide film; A step of forming a second oxide film on the polycrystalline silicon, a step of forming a nitride film @1 on the second oxide film, and a step of forming a second oxide film on the second oxide film, A step of selectively removing a part of the crystalline silicon, a step of forming the entire oxide film (3) on the sidewall of the polycrystalline silicon, a step of forming a 2θ nitride film, and a step of removing a part of the second nitride film. A special feature is that the method includes a selective removal step and a step of forming a fourth oxide film on the removed portion.
以下w&1図により評細に実施例全説明する。 The entire embodiment will be explained in detail below with reference to drawings w&1.
工程1・書画1図(、z)
P型半導体基板101上に第1の酸化膜ゲート酸化膜1
02.200〜400Aを熱酸化法により形成し、その
上に多結晶シリコン103を2000〜4000A光学
的気相成長法で形成し80〇〜1000℃でリンを熱拡
散する1次に化学的気相成長法テ2o o O〜400
o−’;oHia2ノe化膜1゜4を形成する。さら
に化学的気相成長法で2000〜4ooo@ o窒化膜
105全形成する。Step 1/Drawing 1 (,z) First oxide film gate oxide film 1 on P-type semiconductor substrate 101
02. 200~400A is formed by thermal oxidation method, polycrystalline silicon 103 is formed on it by 2000~4000A optical vapor deposition method, and phosphorus is thermally diffused at 800~1000℃ using primary chemical vapor deposition. Phase growth method Te2 o o O~400
o-': oHia2 No-e film 1°4 is formed. Furthermore, the entire nitride film 105 of 2000 to 4000°C is formed by chemical vapor deposition.
工程2・・嬉1図(b)
レジストパターンをマスクに窒化膜105iエツチング
し、該窒化膜をマスクに第2の酸化膜1゜4をエツチン
グし、該第2θ酸化膜をマスクに多結晶シリコン103
tエツチ7”T7:r工程3・・酊1図(c)
工程2により多結晶シリコンoill壁は括出するため
にこの部分に嬉3f2)酸化膜106t−熱酸化法で形
成する。Step 2...Figure 1 (b) Etching the nitride film 105i using the resist pattern as a mask, etching the second oxide film 1°4 using the nitride film as a mask, and etching polycrystalline silicon using the 2θ oxide film as a mask. 103
tetch 7''T7: rStep 3... Figure 1(c) In Step 2, in order to protrude the polycrystalline silicon oil wall, an oxide film 106t is formed on this portion by a thermal oxidation method.
工程4・書画1図(ぬ
化学的気相成長法で第2の窒化膜107を全面に形成す
る。Step 4: A second nitride film 107 is formed on the entire surface by chemical vapor deposition.
工程5・11第1図<e>
該窒化膜107をリアクティブイオンで全面エツチング
すること罠より窒化膜サイドウオール108を形成する
。Step 5.11 FIG. 1 <e> A nitride film sidewall 108 is formed by etching the entire surface of the nitride film 107 using reactive ions.
4一
工程6・・wX1図ω
該第1C)窒化膜105及び窒化膜サイドウオール10
8をマスクに熱酸化を行い、素子分離用酸化膜109を
形成する。4-Step 6...wX1 Figure ω Said 1C) Nitride film 105 and nitride film sidewall 10
Thermal oxidation is performed using 8 as a mask to form an oxide film 109 for element isolation.
工程7@一酊1図(g)
該第10窒化膜105及び窒化膜サイドウオール108
を除去した後、N型不純物をイオン注入した後、熱アニ
ールを行い、ソースやドレイン拡散層110を形成する
。Step 7 @ Ichigo 1 (g) The 10th nitride film 105 and nitride film sidewall 108
After removing N-type impurities, thermal annealing is performed to form source and drain diffusion layers 110.
以上述べたように発明によればゲート電比に対しセルフ
ァラインで素子分離用酸化膜を形成できるため、フィー
ルド領域とゲート電極の会わせ余裕がiらず、トランジ
スタ部分の微細化が容易に行えるという効果を有する。As described above, according to the invention, the oxide film for element isolation can be formed in a self-alignment line with respect to the gate voltage ratio, so there is no margin for meeting the field region and the gate electrode, and the transistor part can be easily miniaturized. It has this effect.
第1図(α)〜(y)は本発明の半導体装置の工程t−
表わす主要断面図。
第2図に)〜(6) tj:従来の半導体装置の工程f
、表わす断面図。
101−P型基板
102−第1の酸化膜(ゲート酸化膜)103−多結晶
シリコン膜(ゲー) [& )104−帆2の酸化膜
105−第1D窺化膜
106−釘3θ酸化膜
107−第2Q窒化膜
108−窒化膜サイドウオール
109−素子分離用酸化膜
110−ソース・ドレイン拡散層
201−P型基板
202−素子分離用酸化膜
203−多結晶シリコン展
204−ソース嗜ドレイン拡散層
以 上
手斗朴永歪C−二1帽姻
第1 図FIG. 1 (α) to (y) show the process t- of the semiconductor device of the present invention.
Main cross-sectional view. (see Figure 2) to (6) tj: Conventional semiconductor device process f
, a cross-sectional view. 101 - P-type substrate 102 - First oxide film (gate oxide film) 103 - Polycrystalline silicon film (G) [& ) 104 - Oxide film of sail 2 105 - First D diagonal film 106 - Nail 3θ oxide film 107 - Second Q nitride film 108 - Nitride film sidewall 109 - Element isolation oxide film 110 - Source/drain diffusion layer 201 - P type substrate 202 - Element isolation oxide film 203 - Polycrystalline silicon layer 204 - Source/drain diffusion layer Figure 1
Claims (1)
と、該第1の酸化膜上に不純物をドープした多結晶シリ
コンを形成する工程と、該多結晶シリコン上に第2の酸
化膜を形成する工程と、該第2の酸化膜上に第1の窒化
膜を形成する工程と、該第1の窒化膜、第2の酸化膜、
多結晶シリコンの一部を選択除去する工程と、該多結晶
シリコンの側壁に第3の酸化膜を形成する工程と、第2
の窒化膜を形成する工程と、該第2の窒化膜の一部を選
択除去する工程と、該除去部に第4の酸化膜を形成する
工程とを具備したことを特徴とする半導体装置の製造方
法。A step of forming a first oxide film on a semiconductor substrate of one conductivity type, a step of forming polycrystalline silicon doped with an impurity on the first oxide film, and a step of forming a second oxide film on the polycrystalline silicon. a step of forming a film, a step of forming a first nitride film on the second oxide film, the first nitride film, the second oxide film,
a step of selectively removing a portion of the polycrystalline silicon; a step of forming a third oxide film on the sidewalls of the polycrystalline silicon;
A semiconductor device comprising: a step of forming a nitride film; a step of selectively removing a part of the second nitride film; and a step of forming a fourth oxide film in the removed portion. Production method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19913585A JPS6260230A (en) | 1985-09-09 | 1985-09-09 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19913585A JPS6260230A (en) | 1985-09-09 | 1985-09-09 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6260230A true JPS6260230A (en) | 1987-03-16 |
Family
ID=16402724
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19913585A Pending JPS6260230A (en) | 1985-09-09 | 1985-09-09 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6260230A (en) |
-
1985
- 1985-09-09 JP JP19913585A patent/JPS6260230A/en active Pending
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