JPS6227734B2 - - Google Patents

Info

Publication number
JPS6227734B2
JPS6227734B2 JP56044556A JP4455681A JPS6227734B2 JP S6227734 B2 JPS6227734 B2 JP S6227734B2 JP 56044556 A JP56044556 A JP 56044556A JP 4455681 A JP4455681 A JP 4455681A JP S6227734 B2 JPS6227734 B2 JP S6227734B2
Authority
JP
Japan
Prior art keywords
bonding
silicon nitride
nitride film
buffer layer
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56044556A
Other languages
English (en)
Other versions
JPS57159035A (en
Inventor
Akira Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP56044556A priority Critical patent/JPS57159035A/ja
Publication of JPS57159035A publication Critical patent/JPS57159035A/ja
Publication of JPS6227734B2 publication Critical patent/JPS6227734B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の構造、特にボンデイング
電極下がボンデイング工程に破壊されることのな
い半導体装置の構造に関するものである。
最近の高周波用バイポーラトランジスタの素子
パターンは、性能指数を上げる為にきわめて微細
化されている。これに伴ないエミツタ、ベースコ
ンタクト窓を覆う金属電極の幅が狭くなり、耐水
性が著しく悪くなり、直流増幅率及び雑音指数を
悪くしている。この耐水性の悪化を補償するた
め、陽極酸化法を用いてペレツト全面を窒化シリ
コン膜で覆う構造も採用されている。
しかし組立工程においては、省力化が進み、ボ
ンデイングは高速化されており、このペレツト構
造ではボンデイング中にボンデイング電極下のシ
リコンが衝撃力により剥離するというような不具
合が生じた。
本発明の目的は高速ボンデイングに適した高周
波用トランジスタの構造を提供するものである。
本発明によれば、電極パツドと半導体基板との
間に比較的軟かい絶縁物からなる緩衝層を設けた
半導体装置を得る。
以下に、図面を用いて、この発明をより詳細に
説明する。第１図ａ〜ｃは従来の半導体装置とそ
の欠点を説明するもので、第１図ａは半導体素子
が不純物拡散により形成された半導体基板１の表
面酸化膜２上に陽極酸化法により全面に300Å程
度の厚さの窒化シリコン膜３を形成し、その後ボ
ンデイング電極４を形成した従来の半導体装置の
断面図である。第１図ｂはこのボンデイング電極
４に金線５を用いてボンデイングすることにより
ボンデイング電極４、窒化シリコン膜３、酸化シ
リコン膜２、半導体基板１にボンデイング衝撃力
６が加わり、歪み６′がこれらに入ることを表わ
した部分断面図である。このようなボンデイング
衝撃力６によつて、窒化シリコン膜３、酸化シリ
コン膜２、半導体基板１は第１図ｃに示すように
剥離し、穴７が形成される。このような剥離が起
こる原因としては、窒化シリコン膜３が非常にう
すい為にボンデイング衝撃力６を緩衝する力が非
常に弱く、ストレスが直接ボンデイング電極４の
下に集中するからであると推定される。
本発明の一実施例によれば、第２図に示すよう
に、不純物拡散によつて半導体素子が形成された
シリコン基板１１上を酸化シリコン膜１２でおお
い、拡散領域からの電極取出部には開孔を設け、
ここから金属の配線電極１５を導出するととも
に、酸化シリコン膜１２上でボンデイング電極１
４を設ける部分には厚さ1000〜1500Åの窒化シリ
コン膜１８を設けさらにその上に全面に窒化シリ
コン膜１３を設け、しかる後に例えば金やアルミ
ニウムのボンデイング電極１４が設けられる。
このボンデイング電極１４に金細線をボンデイ
ングすると、ボンデイング衝撃力は比較的軟かく
かつ厚い窒化シリコン膜１８で緩衝されて下の酸
化シリコン膜１２やシリコン基板１１に加わるこ
とがない。このように、第２図に示す構造の半導
体装置によれば、緩衝層としての窒化シリコン膜
１８によつて、剥離不良率が５％から0.1％迄に
改善することが出来る。したがつて、やむを得
ず、ボンデイング衝撃力を大きくしなければなら
ないような場合にも、緩衝層を設けることによつ
て安全で確実なボンデイング作業が行えることに
なる。
なお、緩衝層としての窒化シリコン膜１８は、
少なくともボンデイング電極１４の下にあれば、
他の部分にあつても良いが、酸化シリコン膜１２
の開口周辺にまで設けると、絶縁膜の全体の厚さ
が厚くなりすぎ、配線金属を断線なしに取り出す
ことが困難になる。又金属は比較的軟かいので緩
衝層としては適しているが、浮遊容量が大きくな
るので、使用に際しては注意を要する。
【図面の簡単な説明】
第１図ａ〜ｃは従来の半導体装置の構造および
剥離の様子を示した断面図である。第２図は緩衝
層をもうけた本発明の一実施例を示す断面図であ
る。 １，１１……シリコン基板、２，１２……酸化
シリコン膜、３，１３……窒化シリコン膜、４，
１４……ボンデイング電極、５……ボンデイング
ワイヤー、６……ボンデイング衝撃力、６′……
ボンデイング歪み、７……剥離した部分、１５…
…配線電極、１８……緩衝層（窒化シリコン
膜）。

Claims (1)

    【特許請求の範囲】
  1. １ 半導体基板上を覆いコンタクトホールを有す
    る絶縁層と、この絶縁層上に選択的に形成され無
    機絶縁材からなる緩衝層と、この緩衝層および前
    記絶縁層の表面を覆い前記コンタクトホールまで
    延在形成されたシリコン窒化膜と、前記緩衝層上
    を覆うシリコン窒化膜上に形成されたボンデイン
    グ電極と、前記コンタクトホールを介して前記半
    導体基板の一部に接触し前記シリコン窒化膜上に
    延在形成された電極配線層とを含む半導体装置。
JP56044556A 1981-03-26 1981-03-26 Manufacture of semiconductor device Granted JPS57159035A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56044556A JPS57159035A (en) 1981-03-26 1981-03-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56044556A JPS57159035A (en) 1981-03-26 1981-03-26 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS57159035A JPS57159035A (en) 1982-10-01
JPS6227734B2 true JPS6227734B2 (ja) 1987-06-16

Family

ID=12694768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56044556A Granted JPS57159035A (en) 1981-03-26 1981-03-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57159035A (ja)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5886733A (ja) * 1981-11-18 1983-05-24 Nec Corp 半導体装置
JPS6237934U (ja) * 1985-08-27 1987-03-06
JP2527457B2 (ja) * 1988-02-29 1996-08-21 シャープ株式会社 半導体装置の電極構造

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5239378A (en) * 1975-09-23 1977-03-26 Seiko Epson Corp Silicon-gated mos type semiconductor device
JPS54107260A (en) * 1978-02-10 1979-08-22 Nec Corp Semiconductor device
JPS56105670A (en) * 1980-01-28 1981-08-22 Mitsubishi Electric Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5239378A (en) * 1975-09-23 1977-03-26 Seiko Epson Corp Silicon-gated mos type semiconductor device
JPS54107260A (en) * 1978-02-10 1979-08-22 Nec Corp Semiconductor device
JPS56105670A (en) * 1980-01-28 1981-08-22 Mitsubishi Electric Corp Semiconductor device

Also Published As

Publication number Publication date
JPS57159035A (en) 1982-10-01

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