JPS6155256B1 - - Google Patents
Info
- Publication number
- JPS6155256B1 JPS6155256B1 JP46103280A JP10328071A JPS6155256B1 JP S6155256 B1 JPS6155256 B1 JP S6155256B1 JP 46103280 A JP46103280 A JP 46103280A JP 10328071 A JP10328071 A JP 10328071A JP S6155256 B1 JPS6155256 B1 JP S6155256B1
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- circuit elements
- semiconductor
- semi
- thin plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 abstract description 26
- 238000009792 diffusion process Methods 0.000 description 11
- 239000000463 material Substances 0.000 description 10
- 239000011810 insulating material Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000004922 lacquer Substances 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910000531 Co alloy Inorganic materials 0.000 description 1
- KGWWEXORQXHJJQ-UHFFFAOYSA-N [Fe].[Co].[Ni] Chemical compound [Fe].[Co].[Ni] KGWWEXORQXHJJQ-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
- H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
- H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
- H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
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- H—ELECTRICITY
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4918—Disposition being disposed on at least two different sides of the body, e.g. dual array
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Description
第1図は本発明による一体化回路を説明する図
で、第2図は同じ関係で配置せられた第1図の一
体化回路の配線図を示す図である。
で、第2図は同じ関係で配置せられた第1図の一
体化回路の配線図を示す図である。
本発明は、主要な表面と裏面とを有する単一の
半導体薄板に、本質的に平面状に配置された複数
の回路素子と、この薄板の外部に接続が必要とさ
れる回路素子に対し電気的に接続された複数の引
出線とを有する電子回路用の半導体装置に関する
ものである。 本発明のある目的及び効果は、次のとおりであ
る。即ち、回路素子が半導体薄板の一面上の不活
性絶縁物質上に置かれた複数の導線により容易に
相互接続し得るように、半導体薄板の一面上に、
上記表面上で相互に距離的に離間された関係に形
成された回路素子を有する一体化回路にして、こ
れにより、上記回路素子とそれらの相互接続とを
単一の構造になし、コンパクトで機械的電気的に
安定な装置で、かつ高度の複雑さの回路の多様性
を可能ならしめたものである。 本発明に用いられる回路素子はN型もしくはP
型いづれか一つの型に導電型を示す単一半導体物
質の本体を使用して適当な導電型の拡散領域を形
成しその拡散領域と半導体との間或は拡散領域自
体間にP−N接合を形成することにより達成され
る。本発明の原理に依れば全電子回路の成分は以
降に詳細に説明される技術の適用に依り特徴づけ
られる様に本体に組立てられる。回路の成分が半
導体物質の本体の中に組合され且つその1部を形
成している事は注意さるべき事である。 本発明に依れば電子回路の能動及受動成分或い
は回路素子は半導体の薄板の一面或いはその近く
に形成される。 その結果、得られる回路は本質的に平面状に配
置されることになる。処理工程中に半導体材料薄
板の全形を行ない、拡散により希望の各種回路素
子を適当な関係で製造することが可能である。 本発明の効果は製造製作上満足なものであり且
つマスキング・エツチング及拡散の様な限定され
た両立性ある工程が一主面から成し得るので大量
生産に適する事であり、更に能動及受動回路素子
の電気的接続の能様が融通性に富み従つて回路が
多様多様に出来ると云う点にある。 更に本発明の他の目的及効果は従来の技術より
もより少ない工程を含む新規なる小型化電子回路
を提供することである。 更に本発明は本質的に電子回路の小型化に関す
るものである。又前述の様に本発明は適当に成形
されそして拡散されたp−n接合を形成された半
導体物質の本体の利用と、中に組込まれるか上記
半導体物質の本体の部分を構成され得る色々な回
路素子或いは成分に対し設計された成分の利用を
企図している。 本発明の他の目的、特徴及び効果は次の詳細な
記述により明白であるが、ここには本発明の好ま
しい実施例を添付図面と共に説明する。 図面に就いて詳述すると、本発明の基本原理を
より明確に理解せしめるため、本発明の好ましい
実施例について詳述する。 本発明の原理を実施している一体化回路の特別
な説明は第1図に示されているがここで金の線は
半導体薄板の一主面上の絶縁不活性物質上に敷設
される。図に示す如く、拡散P−N接合を含む単
一の結晶半導体物質の薄板は、本質的にその薄板
の一面に形成された完全にして一体化されたマル
チバイブレーター電子回路を含むように、加工さ
れ成形されている。この薄板の諸区域は種々の区
域において果されている回路素子の機能を示す記
号を付せられている。第2図は、色々な回路機能
の配線図を、第1図の半導体薄板に占める関係に
於いて示している。この第1、第2図に示された
マルチバイブレーター回路は必要とされる工程技
術を説明するものとして示されている。 まづ、適当な比抵抗の半導体薄板(なるべくは
シリコン或いはゲルマニウムが望ましい)が一面
においてラツプ加工され磨かれる。この設計のた
めに3オーム・センチメートルのP型ゲルマニウ
ムが用いられた。この薄板は、それから表面上に
深さ約0.0178mmのn型の層を生成するアンチモニ
ー拡散工程を受ける。この薄板はそれから5.08×
2.03mmの適当な大きさにカツトされ、磨かれてい
ない表面は薄板に0.0635mmの厚さを与えるように
ラツプ加工される。 金張りコバル引出線50が適当な位置に薄板に
合金化する事により接続される。コバルは鉄−ニ
ツケル−コバルト合金の商品名である。それから
金がトランジスタT1,T2のベース接続53,5
4及び抵抗蓄電器C1R8,C2R3のコンタクト5
1,52の如き、n型区域とオーミツクな接触を
なす領域51〜54を設けるためにマスクを通し
て蒸着される。アルミニウムはn層と整流接触を
形成するトランジスタのエミツタ領域56を備え
るべく、適当な形状をしたマスクを通して蒸着さ
れる。全回路素子は単一の拡散層に関して説明さ
れたが、二重の拡散構成を用いる事も全く可能で
ある。かくして、二重の拡散はn−p−n及びp
−n−p構造両方を形成する様に用いられるだろ
う。 それから、この薄板は、イーストマンコダツク
会社により出されているイーストマン光抵抗の如
き感光性抵抗或いはラツカーで被覆され、光に対
しネガを通して露光される。現像の後に残つてい
るラツカー像は、適当な形状に薄板をエツチする
ための抵抗として用いられる。特にこのエンチン
グは、R1とR2と回路の他の部分との間に分離を
与えるための薄板を通してのスロツトを形成し、
又予め計算された形状に全部の抵抗の領域を形成
する。 化学的エツチングか電気的エツチングのどちら
かが用い得るが、電気的エツチングの方がよいと
思われる。 この段階の次に光抵抗は溶剤で取り除かれ、メ
サ領域60は同じ写真工程によりマスクされる。
この薄板は再びエツチング液に浸され、n層は露
出された領域に於いて完全に取り除かれる。 これは化学的エツチングが良い様に思われる。
それから、その光抵抗は取り除かれる。 金の線70はそれから接続を完全にするため適
当な領域に熱的に接合され、最終的な清浄化エツ
チングが施される。金の線70を用いる代りに接
続は何か他の方法で行なわれてもよい。本発明の
実施例によれば酸化シリコンの如き絶縁不活性物
質が電気接続が行なわれる点を除いて完全に薄板
を被覆するか或いは電気的に接続されるべき点に
接合する選ばれた部分のみを被覆するかするため
にマスクを通して半導体回路薄板に蒸着される。
金の様な導電物質はそれから必要なる電気回路接
続を行なうために絶縁物質に被着される。 試験の後にこの回路は若し必要なら汚染から保
護するために密封されてもよい。完結の装置は過
去に提起された他の装置よりも大きさが数桁少な
い。必要なる組立段階が現在トランジスタを製造
するに用いられている組立に全く似ているので、
又必要なる段階が比較的少ないために、これらの
装置はコンパクトにして本来安価にして確実なる
ものである。 抵抗及び蓄電器の設計は分布された抵抗−蓄電
器回路素子を形成する様に結合される。これはn
型の導電型の拡散層を有するp型の導電型の薄板
は面上に広い面積のコンタクト51,52および
裏面に引出線50を具備する。 トランジスタは1956年ベルシステム・テクニカ
ル・ジヤーナル第35巻23頁のリー(Lee)に依り
述べられている如く薄板上に形成され、コレクタ
ー領域、拡散p−n接合、ベース層、ベース層と
整流接合を形成するエミツタ接触体、ベース及び
コレクターの夫々の接触体を有する。 従つて、本発明の実施例によれば複数の回路素
子、T1,T2,C1R8及びC2R3は相互に距離的に離
間され、それぞれが上述の絶縁層の下で薄板の一
主面に終端している接合により画定されている薄
い領域を含んでいることが注目されるべきであ
る。 又、シリコン酸化物絶縁体は安定で大巾の温度
範囲にわたり装置の特性を破壊しないから、その
使用がベース及びエミツタの接続がなされる温度
範囲に融通性を与えることが明白であろう。 上述した回路設計は全部単一の物質、すなわち
半導体から形成され得る故に、それら全部を、拡
散p−n接合を含む単一結晶半導体薄板に適当な
回路及び適正な成分値をもつ様に一体化して形作
る事が可能である。 また、複数の回路素子は前述した様に半導体薄
板の一主面上に平板状に配置され、マスキング、
エツチング及び拡散の様な両立性ある工程が一主
面から成し得るので半導体装置の大量生産に適し
ている。更に複数の回路素子の接続が絶縁物質上
で行なうことができるので回路に融通性、多様性
があると共に大量生産に適している。 この方法で為され得る回路の組立ての複雑さに
は限界がない。しかし限られた空間に為され得る
成分の型及び値には限界がありこの発明は従来の
技術に対し著しい改良を与えたものである。この
技術に於ける利益が本発明により達せられたので
本発明に対し前以つて達成された最高の成分密度
の1立方フイート当り50万に比較して1立方フイ
ート当り3千万以上の成分密度まで達成すること
は可能である。 本発明は特別な実施例を以つて示したがここに
示唆した発明着想が実際離れる事なく変更及び変
型が可能であることは明白である。従つてこの様
な変更及び変型は発明の範囲の中に入ると思料す
る。
半導体薄板に、本質的に平面状に配置された複数
の回路素子と、この薄板の外部に接続が必要とさ
れる回路素子に対し電気的に接続された複数の引
出線とを有する電子回路用の半導体装置に関する
ものである。 本発明のある目的及び効果は、次のとおりであ
る。即ち、回路素子が半導体薄板の一面上の不活
性絶縁物質上に置かれた複数の導線により容易に
相互接続し得るように、半導体薄板の一面上に、
上記表面上で相互に距離的に離間された関係に形
成された回路素子を有する一体化回路にして、こ
れにより、上記回路素子とそれらの相互接続とを
単一の構造になし、コンパクトで機械的電気的に
安定な装置で、かつ高度の複雑さの回路の多様性
を可能ならしめたものである。 本発明に用いられる回路素子はN型もしくはP
型いづれか一つの型に導電型を示す単一半導体物
質の本体を使用して適当な導電型の拡散領域を形
成しその拡散領域と半導体との間或は拡散領域自
体間にP−N接合を形成することにより達成され
る。本発明の原理に依れば全電子回路の成分は以
降に詳細に説明される技術の適用に依り特徴づけ
られる様に本体に組立てられる。回路の成分が半
導体物質の本体の中に組合され且つその1部を形
成している事は注意さるべき事である。 本発明に依れば電子回路の能動及受動成分或い
は回路素子は半導体の薄板の一面或いはその近く
に形成される。 その結果、得られる回路は本質的に平面状に配
置されることになる。処理工程中に半導体材料薄
板の全形を行ない、拡散により希望の各種回路素
子を適当な関係で製造することが可能である。 本発明の効果は製造製作上満足なものであり且
つマスキング・エツチング及拡散の様な限定され
た両立性ある工程が一主面から成し得るので大量
生産に適する事であり、更に能動及受動回路素子
の電気的接続の能様が融通性に富み従つて回路が
多様多様に出来ると云う点にある。 更に本発明の他の目的及効果は従来の技術より
もより少ない工程を含む新規なる小型化電子回路
を提供することである。 更に本発明は本質的に電子回路の小型化に関す
るものである。又前述の様に本発明は適当に成形
されそして拡散されたp−n接合を形成された半
導体物質の本体の利用と、中に組込まれるか上記
半導体物質の本体の部分を構成され得る色々な回
路素子或いは成分に対し設計された成分の利用を
企図している。 本発明の他の目的、特徴及び効果は次の詳細な
記述により明白であるが、ここには本発明の好ま
しい実施例を添付図面と共に説明する。 図面に就いて詳述すると、本発明の基本原理を
より明確に理解せしめるため、本発明の好ましい
実施例について詳述する。 本発明の原理を実施している一体化回路の特別
な説明は第1図に示されているがここで金の線は
半導体薄板の一主面上の絶縁不活性物質上に敷設
される。図に示す如く、拡散P−N接合を含む単
一の結晶半導体物質の薄板は、本質的にその薄板
の一面に形成された完全にして一体化されたマル
チバイブレーター電子回路を含むように、加工さ
れ成形されている。この薄板の諸区域は種々の区
域において果されている回路素子の機能を示す記
号を付せられている。第2図は、色々な回路機能
の配線図を、第1図の半導体薄板に占める関係に
於いて示している。この第1、第2図に示された
マルチバイブレーター回路は必要とされる工程技
術を説明するものとして示されている。 まづ、適当な比抵抗の半導体薄板(なるべくは
シリコン或いはゲルマニウムが望ましい)が一面
においてラツプ加工され磨かれる。この設計のた
めに3オーム・センチメートルのP型ゲルマニウ
ムが用いられた。この薄板は、それから表面上に
深さ約0.0178mmのn型の層を生成するアンチモニ
ー拡散工程を受ける。この薄板はそれから5.08×
2.03mmの適当な大きさにカツトされ、磨かれてい
ない表面は薄板に0.0635mmの厚さを与えるように
ラツプ加工される。 金張りコバル引出線50が適当な位置に薄板に
合金化する事により接続される。コバルは鉄−ニ
ツケル−コバルト合金の商品名である。それから
金がトランジスタT1,T2のベース接続53,5
4及び抵抗蓄電器C1R8,C2R3のコンタクト5
1,52の如き、n型区域とオーミツクな接触を
なす領域51〜54を設けるためにマスクを通し
て蒸着される。アルミニウムはn層と整流接触を
形成するトランジスタのエミツタ領域56を備え
るべく、適当な形状をしたマスクを通して蒸着さ
れる。全回路素子は単一の拡散層に関して説明さ
れたが、二重の拡散構成を用いる事も全く可能で
ある。かくして、二重の拡散はn−p−n及びp
−n−p構造両方を形成する様に用いられるだろ
う。 それから、この薄板は、イーストマンコダツク
会社により出されているイーストマン光抵抗の如
き感光性抵抗或いはラツカーで被覆され、光に対
しネガを通して露光される。現像の後に残つてい
るラツカー像は、適当な形状に薄板をエツチする
ための抵抗として用いられる。特にこのエンチン
グは、R1とR2と回路の他の部分との間に分離を
与えるための薄板を通してのスロツトを形成し、
又予め計算された形状に全部の抵抗の領域を形成
する。 化学的エツチングか電気的エツチングのどちら
かが用い得るが、電気的エツチングの方がよいと
思われる。 この段階の次に光抵抗は溶剤で取り除かれ、メ
サ領域60は同じ写真工程によりマスクされる。
この薄板は再びエツチング液に浸され、n層は露
出された領域に於いて完全に取り除かれる。 これは化学的エツチングが良い様に思われる。
それから、その光抵抗は取り除かれる。 金の線70はそれから接続を完全にするため適
当な領域に熱的に接合され、最終的な清浄化エツ
チングが施される。金の線70を用いる代りに接
続は何か他の方法で行なわれてもよい。本発明の
実施例によれば酸化シリコンの如き絶縁不活性物
質が電気接続が行なわれる点を除いて完全に薄板
を被覆するか或いは電気的に接続されるべき点に
接合する選ばれた部分のみを被覆するかするため
にマスクを通して半導体回路薄板に蒸着される。
金の様な導電物質はそれから必要なる電気回路接
続を行なうために絶縁物質に被着される。 試験の後にこの回路は若し必要なら汚染から保
護するために密封されてもよい。完結の装置は過
去に提起された他の装置よりも大きさが数桁少な
い。必要なる組立段階が現在トランジスタを製造
するに用いられている組立に全く似ているので、
又必要なる段階が比較的少ないために、これらの
装置はコンパクトにして本来安価にして確実なる
ものである。 抵抗及び蓄電器の設計は分布された抵抗−蓄電
器回路素子を形成する様に結合される。これはn
型の導電型の拡散層を有するp型の導電型の薄板
は面上に広い面積のコンタクト51,52および
裏面に引出線50を具備する。 トランジスタは1956年ベルシステム・テクニカ
ル・ジヤーナル第35巻23頁のリー(Lee)に依り
述べられている如く薄板上に形成され、コレクタ
ー領域、拡散p−n接合、ベース層、ベース層と
整流接合を形成するエミツタ接触体、ベース及び
コレクターの夫々の接触体を有する。 従つて、本発明の実施例によれば複数の回路素
子、T1,T2,C1R8及びC2R3は相互に距離的に離
間され、それぞれが上述の絶縁層の下で薄板の一
主面に終端している接合により画定されている薄
い領域を含んでいることが注目されるべきであ
る。 又、シリコン酸化物絶縁体は安定で大巾の温度
範囲にわたり装置の特性を破壊しないから、その
使用がベース及びエミツタの接続がなされる温度
範囲に融通性を与えることが明白であろう。 上述した回路設計は全部単一の物質、すなわち
半導体から形成され得る故に、それら全部を、拡
散p−n接合を含む単一結晶半導体薄板に適当な
回路及び適正な成分値をもつ様に一体化して形作
る事が可能である。 また、複数の回路素子は前述した様に半導体薄
板の一主面上に平板状に配置され、マスキング、
エツチング及び拡散の様な両立性ある工程が一主
面から成し得るので半導体装置の大量生産に適し
ている。更に複数の回路素子の接続が絶縁物質上
で行なうことができるので回路に融通性、多様性
があると共に大量生産に適している。 この方法で為され得る回路の組立ての複雑さに
は限界がない。しかし限られた空間に為され得る
成分の型及び値には限界がありこの発明は従来の
技術に対し著しい改良を与えたものである。この
技術に於ける利益が本発明により達せられたので
本発明に対し前以つて達成された最高の成分密度
の1立方フイート当り50万に比較して1立方フイ
ート当り3千万以上の成分密度まで達成すること
は可能である。 本発明は特別な実施例を以つて示したがここに
示唆した発明着想が実際離れる事なく変更及び変
型が可能であることは明白である。従つてこの様
な変更及び変型は発明の範囲の中に入ると思料す
る。
1 複数の回路素子を含み主要な表面及び裏面を
有する単一の半導体薄板と; 上記回路素子のうち上記薄板の外部に接続が必
要とされる回路素子に対し電気的に接続された複
数の引出線と; を有する電子回路用の半導体装置において、 (a) 上記の複数の回路素子は、上記薄板の種々の
区域に互に距離的に離間して形成されており、 (b) 上記の複数の回路素子は、上記薄板の上記主
要な表面に終る接合により画定されている薄い
領域をそれぞれ少くともひとつ含み; (c) 不活性絶縁物質とその上に被着された複数の
回路接続用導電物質とが、上記薄い領域の形成
されている上記主要な表面の上に形成されてお
り; (d) 上記互に距離的に離間した複数の回路素子中
の選ばれた薄い領域が、上記不活性絶縁物質上
の複数の上記回路接続用導電物質によつて電気
的に接続され、上記電子回路を達成する為に上
記複数の回路素子の間に必要なる電気回路接続
がなされており; (e) 上記電子回路が、上記複数の回路素子及び上
記不活性絶縁物質上の上記回路接続用導電物質
によつて本質的に平面状に配置されている; ことを特徴とする半導体装置。
有する単一の半導体薄板と; 上記回路素子のうち上記薄板の外部に接続が必
要とされる回路素子に対し電気的に接続された複
数の引出線と; を有する電子回路用の半導体装置において、 (a) 上記の複数の回路素子は、上記薄板の種々の
区域に互に距離的に離間して形成されており、 (b) 上記の複数の回路素子は、上記薄板の上記主
要な表面に終る接合により画定されている薄い
領域をそれぞれ少くともひとつ含み; (c) 不活性絶縁物質とその上に被着された複数の
回路接続用導電物質とが、上記薄い領域の形成
されている上記主要な表面の上に形成されてお
り; (d) 上記互に距離的に離間した複数の回路素子中
の選ばれた薄い領域が、上記不活性絶縁物質上
の複数の上記回路接続用導電物質によつて電気
的に接続され、上記電子回路を達成する為に上
記複数の回路素子の間に必要なる電気回路接続
がなされており; (e) 上記電子回路が、上記複数の回路素子及び上
記不活性絶縁物質上の上記回路接続用導電物質
によつて本質的に平面状に配置されている; ことを特徴とする半導体装置。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US791602A US3138743A (en) | 1959-02-06 | 1959-02-06 | Miniaturized electronic circuits |
US792840A US3138747A (en) | 1959-02-06 | 1959-02-12 | Integrated semiconductor circuit device |
US352380A US3261081A (en) | 1959-02-06 | 1964-03-16 | Method of making miniaturized electronic circuits |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6155256B1 true JPS6155256B1 (ja) | 1986-11-27 |
Family
ID=27408060
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP46103280A Pending JPS6155256B1 (ja) | 1959-02-06 | 1971-12-21 |
Country Status (10)
Country | Link |
---|---|
US (3) | US3138743A (ja) |
JP (1) | JPS6155256B1 (ja) |
AT (1) | AT247482B (ja) |
CH (8) | CH410194A (ja) |
DE (8) | DE1196299C2 (ja) |
DK (7) | DK104007C (ja) |
GB (14) | GB945749A (ja) |
MY (14) | MY6900290A (ja) |
NL (7) | NL6608451A (ja) |
SE (1) | SE314440B (ja) |
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-
0
- GB GB945740D patent/GB945740A/en active Active
- GB GB945742D patent/GB945742A/en active Active
- GB GB945747D patent/GB945747A/en active Active
-
1959
- 1959-02-06 US US791602A patent/US3138743A/en not_active Expired - Lifetime
- 1959-02-12 US US792840A patent/US3138747A/en not_active Expired - Lifetime
-
1960
- 1960-02-02 GB GB32744/63A patent/GB945749A/en not_active Expired
- 1960-02-02 GB GB3836/63A patent/GB945738A/en not_active Expired
- 1960-02-02 GB GB27542/63A patent/GB945746A/en not_active Expired
- 1960-02-02 GB GB28005/60D patent/GB945748A/en not_active Expired
- 1960-02-02 GB GB27541/63A patent/GB945745A/en not_active Expired
- 1960-02-02 GB GB27326/63A patent/GB945743A/en not_active Expired
- 1960-02-02 GB GB27195/63A patent/GB945739A/en not_active Expired
- 1960-02-02 GB GB5691/62A patent/GB945737A/en not_active Expired
- 1960-02-02 GB GB27540/63A patent/GB945744A/en not_active Expired
- 1960-02-02 GB GB3633/60A patent/GB945734A/en not_active Expired
- 1960-02-02 GB GB27197/63A patent/GB945741A/en not_active Expired
- 1960-02-05 DE DE19601196299D patent/DE1196299C2/de not_active Expired
- 1960-02-05 DK DK258365AA patent/DK104007C/da active
- 1960-02-05 DK DK258465AA patent/DK104008C/da active
- 1960-02-05 DE DET27618A patent/DE1196301B/de active Pending
- 1960-02-05 DE DET27617A patent/DE1196300B/de active Pending
- 1960-02-05 DK DK258165AA patent/DK104006C/da active
- 1960-02-05 DK DK258265AA patent/DK104470C/da active
- 1960-02-05 DE DE1960T0027614 patent/DE1196297C2/de not_active Expired
- 1960-02-05 DK DK258565AA patent/DK104185C/da active
- 1960-02-05 DE DET17835A patent/DE1196295B/de active Pending
- 1960-02-05 DK DK258665AA patent/DK104005C/da active
- 1960-02-05 DE DET27615A patent/DE1196298B/de active Pending
- 1960-02-05 DE DET27613A patent/DE1196296B/de active Pending
- 1960-02-05 DK DK45460AA patent/DK103790C/da active
- 1960-02-06 CH CH131460A patent/CH410194A/fr unknown
- 1960-02-06 CH CH738764A patent/CH380824A/fr unknown
- 1960-02-06 AT AT926861A patent/AT247482B/de active
- 1960-02-06 CH CH291263A patent/CH387799A/fr unknown
- 1960-02-06 CH CH738664A patent/CH415867A/fr unknown
- 1960-02-06 CH CH738564A patent/CH416845A/fr unknown
- 1960-02-06 CH CH738964A patent/CH415869A/fr unknown
- 1960-02-06 CH CH70665A patent/CH410201A/fr unknown
- 1960-02-06 CH CH738864A patent/CH415868A/fr unknown
-
1964
- 1964-03-16 US US352380A patent/US3261081A/en not_active Expired - Lifetime
- 1964-06-23 SE SE763964A patent/SE314440B/xx unknown
- 1964-12-02 DE DE19641439754 patent/DE1439754B2/de active Pending
-
1966
- 1966-06-17 NL NL6608451A patent/NL6608451A/xx unknown
- 1966-06-17 NL NL6608449A patent/NL6608449A/xx unknown
- 1966-06-17 NL NL6608446A patent/NL6608446A/xx unknown
- 1966-06-17 NL NL6608445A patent/NL6608445A/xx unknown
- 1966-06-17 NL NL6608447A patent/NL6608447A/xx unknown
- 1966-06-17 NL NL6608452A patent/NL134915C/xx active
- 1966-06-17 NL NL6608448A patent/NL6608448A/xx unknown
-
1969
- 1969-12-31 MY MY1969290A patent/MY6900290A/xx unknown
- 1969-12-31 MY MY1969285A patent/MY6900285A/xx unknown
- 1969-12-31 MY MY1969284A patent/MY6900284A/xx unknown
- 1969-12-31 MY MY1969292A patent/MY6900292A/xx unknown
- 1969-12-31 MY MY1969286A patent/MY6900286A/xx unknown
- 1969-12-31 MY MY1969291A patent/MY6900291A/xx unknown
- 1969-12-31 MY MY1969287A patent/MY6900287A/xx unknown
- 1969-12-31 MY MY1969315A patent/MY6900315A/xx unknown
- 1969-12-31 MY MY1969300A patent/MY6900300A/xx unknown
- 1969-12-31 MY MY1969283A patent/MY6900283A/xx unknown
- 1969-12-31 MY MY1969293A patent/MY6900293A/xx unknown
- 1969-12-31 MY MY1969296A patent/MY6900296A/xx unknown
- 1969-12-31 MY MY1969301A patent/MY6900301A/xx unknown
- 1969-12-31 MY MY1969302A patent/MY6900302A/xx unknown
-
1971
- 1971-12-21 JP JP46103280A patent/JPS6155256B1/ja active Pending
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