JPS61124159A - 半導体パツケ−ジとその製造方法 - Google Patents

半導体パツケ−ジとその製造方法

Info

Publication number
JPS61124159A
JPS61124159A JP59245236A JP24523684A JPS61124159A JP S61124159 A JPS61124159 A JP S61124159A JP 59245236 A JP59245236 A JP 59245236A JP 24523684 A JP24523684 A JP 24523684A JP S61124159 A JPS61124159 A JP S61124159A
Authority
JP
Japan
Prior art keywords
metal
aluminum
wirings
metal frame
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59245236A
Other languages
English (en)
Inventor
Hisashi Nakamura
中村　恒
Tsutomu Ishiguro
石黒　勉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP59245236A priority Critical patent/JPS61124159A/ja
Publication of JPS61124159A publication Critical patent/JPS61124159A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
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    • H01L2224/45124—Aluminium (Al) as principal constituent
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  • Physics & Mathematics (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 産業上の利用分野 本発明は広範な電子機器に用いられる半導体パッケージ
とその製造方法に関するものである。
従来例の構成とその問題点 近年、半導体技術の技術的進歩はめざましいものがあり
、その利用分野は電子機器分野のみならず他の産業分野
へと広範に波及し、その需要は飛躍的な増加をたどって
いる。この半導体のパッケージ形態は半導体素子（チッ
プ）の集積度や接続端子数、さらにはその用途に応じて
従来から様々な形状や構造を有するものが用いられてい
るが、現在もっとも一般的に広く用いられているものは
樹脂モールドタイプのデュアルインラインパッケージで
ある。
このパッケージは鉄や銅などの金属箔を金型を用いて所
望の形状に打抜き、部分的に金などの貴金属をメッキし
て作ったメタルフレームに、半導３べ一７′ 体ＩＣやＬＳｉなどの半導体チップをダイスボンドして
固定し、この半導体チップの外部接続端子トメタルフレ
ームの金めつき部分とを金線やアルミニウム線などの金
属細Ｚ線を使用して、ボンディングを行ない、最終的に
半導体チップを粉末状のエポキシ樹脂を用いてトランス
ファーモールド法によって封止したものである。
ところが、このような構成から成る半導体パッケージで
は、メタルフレームに半導体チップと安定な接続を与え
るために必要な部分に金などの高価な金属を部分的にメ
ッキする必要があり、またそのメッキプロセスが煩雑で
あるためにコストが高くつくことはもとより、半導体チ
ップと金属細線で接続する場合、特にアルミニウム線を
使用してワイヤーボンディングを行う場合に金とアルミ
ニウム間のボンデング強度が十分に得られにくいために
、信頼性テストにおいてアルミニウム線が金めつき層か
らはぐり離、断線する不良が発生しやすいこと、さらに
は、高温熱処理を行なうと、金とアルミニウムの接合部
にパープルブレイクと称する金属間化合物が生成し、と
れがアルミニウムと金との接合不良をもたらすなど、ボ
ンディングの信頼性をそこなうなどの不都合があった。
発明の目的 本発明の目的は、コストが安価でしかも半導体チップと
のワイヤーボンディングにおいて、メタルフレームと金
属細線とのボンディング強度にすぐれかつ接続の信頼性
が極めてすぐれた半導体パッケージと、その製造方法を
提供することである。
発明の構成 本発明による半導体パッケージは、金属箔を加工して作
ったメタルフレームの一部分に金属アルばニウム層を設
け、このメタルフレーム上に半導体チップを固定して、
その外部接続端子と金属アルミニウム層とがワイヤーで
接続したものであり、メタルフレームに金属アルミニウ
ム層をポンディングパッドをして設けたことにより、ワ
イヤーとのボンディング強度が向上し、その信頼性が著
しく改善されるものである。
実施例の説明 以下本発明の実施例を図面を参照しながら詳細５ページ に説明する。
図は本発明の一実施例における半導体パッケージの断面
図である。図において１は金属箔、２は金属アルミニウ
ム層、３は半導体チップ、４は金属細線、６はモールド
樹脂である。
以上のように構成された本実施例による半導体パッケー
ジについて以下、その製造方法を詳細に説明する。
先づ、図に示すように本実施例では鉄−ニッケル合金か
ら成る厚さ約０．２χのフープ上の金属箔１を金型を用
いて連続的に打抜加工を行ない、所望の模様を有するメ
タルフレームを作成した。次に、このメタルフレームの
一部分に金属アルミニウム層２を部分的に形成するが、
この金属アルミニウム層２を形成するにあたっては、真
空蒸着技術を利用し、メタルフレームの必要部分にのみ
選択的に金属アルミニウム層２を析出させるために、ス
テンレススチールで作ったメタルマスク−＆使用し、こ
のメタルマスクとメタルフレームを重ね合わせて、真空
蒸着を行ない金属アルミニウム２を６ベーン に、鉄−ニッケル金属箔１の表面にいろいろな金属をメ
ッキし金属アルミニウムとの密着性を評価したが、その
結果、鉄−ニッケル金属箔上にニッケルメッキを薄く施
こし、その表面に部分的にアルばニウムを真空蒸着法に
よって析出させることにより、アルミニウム層２と金属
箔１との密着性が極めてよくなることがわかった。そし
てこのようにして作ったメタルフレームは半導体チップ
３を所定の位置にのせ、導電性ペーストなどを用いてメ
タルフレームと強固に固定する、いわゆるダイスボンド
処理を行ない、この半導体チップ３の外部接続端子と、
メタルフレームの接続を必要とする金属アルミニウム層
２とを金線やアルミニウム線などの金属細線４を用いて
、熱圧着法や超音・減法によって接続し、しかる後に半
導体チップ３を粉末状のエポキシ樹脂などから成るモー
ルド樹脂６を用いてトランスファーモールド法により封
７ペーノ 止し、半導体パッケージを作った。尚、この半導体パッ
ケージを作成するにあたって、本実施例では特に金属細
線９としてアルミニウム線を用い、ポールボンディング
法や超音波ボンディング法によってメタルフレームと接
続させたが、メタルフレームとの接続は極めて強固であ
り、良好な信頼性を得ることができた。
発明の効果 以上の説明から明らかなように本発明による半導体パッ
ケージはメタルフレーム上に金属アルミニウム層を選択
的に形成し、このアルミニウム層と半導体チップとをワ
イヤーボンド法によって接続したものであるので、従来
例のように金などの貴金属層を設ける必要がないので、
コストが安価につくことや、特にアルミニウム線を使用
してワイヤーポンドを行なう場合には、そのボンディン
グ強度がすぐれ、接続の信頼性にすぐれた半導体パッケ
ージが得られるなどの効果がある。
【図面の簡単な説明】
図は本発明の一実施例における半導体パッケージの断面
図である。 １・・・・・・金属箔、２・・・・・・金属アルミニウ
ム層、３・・・・・・半導体チップ、４・・・・・・金
属細線、６・・・・・・モールド樹脂。

Claims (3)

    【特許請求の範囲】
  1. （１）金属箔を加工して作ったメタルフレームの一部分
    に金属アルミニウム層を選択的に設け、上記メタルフレ
    ーム上に半導体チップを固定して、その外部接続端子と
    、金属アルミニウム層とを金属細線で接続したことを特
    徴とする半導体パッケージ。
  2. （２）金属アルミニウム層がニッケル層を介して金属箔
    上に部分的に形成されたメタルフレームを使用したこと
    を特徴とする特許請求の範囲第１項記載の半導体パッケ
    ージ。
  3. （３）金属箔を加工することにより所望の形状を有する
    メタルフレームを作り、上記メタルフレームの一部分に
    真空蒸着法によって金属アルミニウムを選択的に形成す
    るとともに、上記メタルフレームに半導体チップを固定
    してその外部接続端子とアルミニウム層とをワイヤーボ
    ンド法により接続したことを特徴とする半導体パッケー
    ジの製造方法。
JP59245236A 1984-11-20 1984-11-20 半導体パツケ−ジとその製造方法 Pending JPS61124159A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59245236A JPS61124159A (ja) 1984-11-20 1984-11-20 半導体パツケ−ジとその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59245236A JPS61124159A (ja) 1984-11-20 1984-11-20 半導体パツケ−ジとその製造方法

Publications (1)

Publication Number Publication Date
JPS61124159A true JPS61124159A (ja) 1986-06-11

Family

ID=17130679

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59245236A Pending JPS61124159A (ja) 1984-11-20 1984-11-20 半導体パツケ−ジとその製造方法

Country Status (1)

Country Link
JP (1) JPS61124159A (ja)

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