JPS59204311A - Predictive encoding circuit - Google Patents

Abstract

PURPOSE:To shorten the critical path and to carry out the arithmetic processing of the critical path within one clock by shifting a register in position. CONSTITUTION:Dual difference circuit constitution consists of a difference circuit 1' which has registers 23 and 32, a subtracter 2, and an adder 4 internally, a difference circuit 2' which has registers 8, 9, 10, 21, 22, and 31, a subtracter 1, and an adder 6 externally, and a quantizer 3. The critical path of this predictive encoding circuit starts at the register 32 and extends to the register 8 through the quantizer 3 and adders 4 and 6. Therefore, the critical path is shortened by the extent corresponding to the stage the substracter 2 and a limiter. Consequently, the arithmetic processing of the critical path is carried out within one clock.

Description

【発明の詳細な説明】 （１）発明の属する技術分野 本発明はカラーテレビ信号のディジタル信号処理に関し
、特に予測符号化回路に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical field to which the invention pertains The present invention relates to digital signal processing of color television signals, and particularly to a predictive coding circuit.

（２）従来技術の説明 従来、この種の予測符号化回路は第１図に示すように１
クロツクの間に２回の減算、量子化、２回の加算、リミ
ットの演算を行なう必要があった。したがって従来の回
路構成ではクリティカルパスが長くなシ、スピードの点
から１り四ツクの間にこれらの処理を行なうことは困難
であった。(2) Description of the prior art Conventionally, this type of predictive coding circuit has one
It was necessary to perform two subtractions, quantization, two additions, and a limit operation during the clock. Therefore, in the conventional circuit configuration, the critical path is long, and from the viewpoint of speed, it is difficult to perform these processes in one to four steps.

（３）発明の目的 本発明はレジスタの位置を移動させることによシ、クリ
ティカルパスを短くした回路構成を提供するものである
。(3) Purpose of the Invention The present invention provides a circuit configuration in which the critical path is shortened by moving register positions.

（４）発明の特徴 本発明の特徴は、レジスタ５段とリミッタと加算器およ
び減算器からなる差分回路ｌと、レジスタ１段と加算器
および減算器からなる差分回路２と、量子化器で構成さ
れる予測符号化回路において、差分回路１の差分出力と
差分回路２の差分入力の間と、差分回路２と量子化器の
間にそれぞれレジスタ１段をもつ予測符号化回路にある
。(4) Features of the Invention The features of the present invention include a differential circuit 1 consisting of five register stages, a limiter, an adder, and a subtracter, a differential circuit 2 consisting of one register stage, an adder, and a subtracter, and a quantizer. In the predictive encoding circuit constructed, the predictive encoding circuit has one register stage each between the differential output of the differential circuit 1 and the differential input of the differential circuit 2, and between the differential circuit 2 and the quantizer.

（５）実施例 次に本発明の実施例について図面を参照して説明する。(5) Examples Next, embodiments of the present invention will be described with reference to the drawings.

第１図は従来の予測符号化回路の一例であル、内側にレ
ジスタ５と減算器２と加算器４を含む差分回路１と外側
にレジスタ８．９．１０．１１．１２とリミッタ７と減
算器１と加算器６を含む差分回路２と量子化器３とから
構成され、２重の差分回路構成となっている。ここでこ
の予測符号化回路のクリティカルパスはレジスタ１２か
ら始まシ、減算器１．２、量子化器３、加算器４．６、
リミッタ７を経てレジスタ８に至るパスである。このよ
うな構成によれば、１クロツクの間にクリティカルパル
スの演算処理を行なうことは困難であった。FIG. 1 shows an example of a conventional predictive encoding circuit, in which a differential circuit 1 including a register 5, a subtracter 2, and an adder 4 is placed inside, and registers 8, 9, 10, 11, 12, and a limiter 7 are placed outside. It is composed of a difference circuit 2 including a subtracter 1 and an adder 6, and a quantizer 3, and has a double difference circuit configuration. Here, the critical path of this predictive encoding circuit starts from register 12, subtracter 1.2, quantizer 3, adder 4.6,
This is a path that passes through the limiter 7 and reaches the register 8. With such a configuration, it is difficult to perform arithmetic processing on critical pulses within one clock.

そこで本発明では演算パスの短縮を図った。Therefore, the present invention aims to shorten the calculation path.

従来の予測符号化回路を示す第１図においてレジスタ５
を第２図のレジスタ２３．２４（７）位置に移動させ、
また第１図のレジスタ１１．１２を第２図のレジスタ２
１．２２と２５，２６の位置に移動させる。さらに第２
図においてレジスタ２４．２６を第３図のレジスタ３２
の位置に移動させ、また第２図のレジスタ２５を第３図
のレジスタ３１の位置に移動させ、リミッタ７とレジス
タ８の位置を交換する。In FIG. 1 showing a conventional predictive encoding circuit, register 5
Move it to the register 23.24(7) position in Figure 2,
Also, registers 11 and 12 in Figure 1 are replaced by registers 2 in Figure 2.
1. Move to positions 22, 25, and 26. Furthermore, the second
In the figure, registers 24 and 26 are replaced by registers 32 and 32 in Figure 3.
The register 25 in FIG. 2 is moved to the position of the register 31 in FIG. 3, and the positions of the limiter 7 and register 8 are exchanged.

第３図を参照すると、内側にレジスタ２３．３２と減算
器２と加算器４を含む差分回路１と外側にレジスタ８，
９．１０．２１．２２．３１と減算器１と加算器６とリ
ミッタ７を含む差分回路２と量子化器３とから構成され
、第１図と同様、２重の差分回路構成となっている。Referring to FIG. 3, a differential circuit 1 including registers 23 and 32, a subtracter 2, and an adder 4 is located inside, and a register 8 is located outside.
9.10.21.22.31, a difference circuit 2 including a subtracter 1, an adder 6, and a limiter 7, and a quantizer 3, and has a double difference circuit configuration as in FIG. There is.

ここでこの予測符号化回路のクリティカルパスはレジス
タ３２から始まシ、量子化器３、加算器４．６を経てレ
ジスタ８に至るパスである。Here, the critical path of this predictive encoding circuit is a path starting from register 32, passing through quantizer 3, adder 4.6, and ending at register 8.

第１図と第３図を比較すると機能は全く同じであるがク
リティカルパスの長さが異なる。第３図の＃１うが減算
器２段とリミッタ分だけ短い。Comparing FIG. 1 and FIG. 3, the functions are exactly the same, but the lengths of the critical paths are different. #1 in Fig. 3 is shorter by the two-stage subtractor and limiter.

第１図の構成ではスピードの点で１クロツクの間にクリ
ティカルパスの演算処理を行なうことは困難である。In the configuration shown in FIG. 1, it is difficult to perform arithmetic processing on the critical path within one clock in terms of speed.

しかし、第３図の構成では１クロツクの間でクリティカ
ルパスの演算処理を行なう仁とが可能になる。However, with the configuration shown in FIG. 3, it is possible to perform critical path arithmetic processing within one clock.

（６）発明の詳細な説明 本発明は以上説明したようにレジスタの位置を移動させ
ることによシクリティカルパスが短くなシ、１クロツク
の間で処理が実現できるという効果がある。(6) Detailed Description of the Invention As explained above, the present invention has the effect that by moving the register positions, the critical path is short and processing can be realized within one clock.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の予測符号化回路を示したブロック図、第
２図は第１図においてレジスタ５．１１．１２を移動さ
せたブロック図、第３図は第２図においてレジスタ２４
．２５．２６を移動させ、リミッタ７とレジスタ８の位
置を交換したブロック図である。 なお、図面において、１．２・・・・・・減算器、３・
・・・・・量子化器、４、伊・・・・・・加算器、７・
・・・・・リミッタ、５．８，９．１０．１１．１２，
２１．２２．２３．２４．２５．２６．３１．３２・・
曲レジスタ、である。FIG. 1 is a block diagram showing a conventional predictive encoding circuit, FIG. 2 is a block diagram in which registers 5, 11, and 12 are moved from FIG.
．． 25 and 26 are moved and the positions of the limiter 7 and the register 8 are exchanged. FIG. In addition, in the drawings, 1.2...subtractor, 3.
...Quantizer, 4, Italy...Adder, 7.
...Limiter, 5.8, 9.10.11.12,
21.22.23.24.25.26.31.32...
This is the song register.

Claims (1)

【特許請求の範囲】[Claims] ５段のレジスタとリミッタと加算器および減算器からな
る第１の差分回路と、１段のレジスタと加算器および減
算器からなる第２の差分回路と、量子化器とを含んで構
成される予測符号化回路において、前記第１の差分回路
の差分出力と前記第２の差分回路の差分入力との間と、
前記第２の差分回路と前記量子化器との間にそれぞれレ
ジスタが設けられたことを特徴とする予測符号化回路。Consisting of a first difference circuit consisting of five stages of registers, a limiter, an adder and a subtracter, a second difference circuit comprising one stage of registers, an adder and a subtracter, and a quantizer. In the predictive encoding circuit, between a differential output of the first differential circuit and a differential input of the second differential circuit;
A predictive encoding circuit characterized in that a register is provided between the second difference circuit and the quantizer.