JPH0243375B2 - - Google Patents
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- Publication number
- JPH0243375B2 JPH0243375B2 JP24577584A JP24577584A JPH0243375B2 JP H0243375 B2 JPH0243375 B2 JP H0243375B2 JP 24577584 A JP24577584 A JP 24577584A JP 24577584 A JP24577584 A JP 24577584A JP H0243375 B2 JPH0243375 B2 JP H0243375B2
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- quantizer
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- 230000003111 delayed effect Effects 0.000 claims description 5
- 238000001514 detection method Methods 0.000 claims description 2
- 238000013139 quantization Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 238000005070 sampling Methods 0.000 description 3
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
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Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、画像帯域圧縮装置に用いられる
DPCM回路特に差分信号出力手段として、３入
力２出力デイジタル・デイジタル変換器（以下３
入力２出力Ｄ／Ｄ変換器と称す）及びこの２出力
を加算する加算器を用いた高速DPCM回路に係
り、予測の為の演算速度を向上させる高速
DPCM回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention is used in an image band compression device.
A DPCM circuit, especially a 3-input 2-output digital-to-digital converter (hereinafter referred to as 3), is used as a differential signal output means.
This is a high-speed DPCM circuit that uses an input/two-output D/D converter) and an adder that adds these two outputs, and is a high-speed DPCM circuit that improves the calculation speed for prediction.
Regarding DPCM circuit.
上記高速DPCM回路を用い帯域圧縮を行う場
合予測の為の演算速度が速いことが望ましい。 When performing band compression using the above-mentioned high-speed DPCM circuit, it is desirable that the calculation speed for prediction be fast.
第２図は従来例の予測係数が1/2の場合の高速
DPCM回路のブロツク図である。
Figure 2 shows high speed when the prediction coefficient of the conventional example is 1/2.
FIG. 3 is a block diagram of a DPCM circuit.
図中１は３入力２出力Ｄ／Ｄ変換器、２，５は
加算器、３，７は遅延素子であるFF、４は量子
化器、６，８，９は予測係数1/2を乗算する乗算
器を示す。 In the figure, 1 is a 3-input 2-output D/D converter, 2 and 5 are adders, 3 and 7 are FF delay elements, 4 is a quantizer, and 6, 8, and 9 are multiplied by 1/2 prediction coefficient. shows a multiplier that
予測の為に２入力の減算器を用いるDPCM回
路の代わりに、３入力２出力Ｄ／Ｄ変換器と加算
器を用い高速化を実現したものとして、本出願人
が昭和59年８月30日特願昭59―181061で特許出願
した高速DPCM符号器がある。 On August 30, 1980, the applicant proposed a system that realized high speed by using a 3-input 2-output D/D converter and an adder instead of the DPCM circuit that uses a 2-input subtractor for prediction. There is a high-speed DPCM encoder for which a patent was applied for in Japanese Patent Application No. 181061.
この実施例を示したものが今日従来例とした第
２図である。 This embodiment is shown in FIG. 2, which is considered as a conventional example today.
第２図の場合は、量子化器４の出力のDPCM
信号は乗算器８にて予測係数1/2が乗算され、３
入力２出力Ｄ／Ｄ変換器１に反転して入力し、又
FF７の出力である１標本化周期前の値は乗算器
９にて予測係数1/2が乗算され、３入力２出力
Ｄ／Ｄ変換器１に反転して入力し、３入力２出力
Ｄ／Ｄ変換器１では入力しているPCM信号と反
転して入力した信号との加算を各桁毎に求め、桁
上げと加算結果の２出力とし、加算器２に入力す
る。 In the case of Figure 2, the DPCM of the output of quantizer 4 is
The signal is multiplied by the prediction coefficient 1/2 in multiplier 8, and
Input 2 Input to output D/D converter 1 inverted, and
The value one sampling period before, which is the output of the FF7, is multiplied by a prediction coefficient 1/2 in the multiplier 9, and is inverted and input to the 3-input 2-output D/D converter 1. The D converter 1 calculates the addition of the input PCM signal and the inverted input signal for each digit, produces two outputs: a carry and an addition result, and inputs them to the adder 2.
加算器２では、各桁毎の加算結果の出力は、各
桁毎の全加算器に入力させ、桁上げ出力は１桁上
の全加算器に入力させ、３入力２出力Ｄ／Ｄ変換
器１と加算器２により、入力するPCM信号に、
乗算器８，９の出力を反転して入力して加算し、
FF３を介して量子化器４に入力し、量子化され
たDPCM信号を出力するようにして、予測の為
に２入力の減算器を用いるDPCM回路より高速
なDPCM回路を実現している。 In the adder 2, the output of the addition result for each digit is input to the full adder for each digit, the carry output is input to the full adder one digit above, and the output is input to the full adder for each digit, and the output is input to the full adder for one digit above, and the output is input to the full adder for each digit, and the output is input to the full adder for one digit above, and the output is input to the full adder for each digit. 1 and adder 2, the input PCM signal is
The outputs of multipliers 8 and 9 are inverted and inputted and added.
The signal is input to the quantizer 4 via the FF 3 and the quantized DPCM signal is output, thereby realizing a DPCM circuit that is faster than a DPCM circuit that uses a two-input subtracter for prediction.
しかしながら、この場合処理速度を決定するク
リテイカルパスとしては、３入力２出力Ｄ／Ｄ変
換器１，加算器２，FF３，量子化器４，乗算器
８のループとなり、乗算器８の動作速度が遅い場
合予測の為の演算速度が遅い問題点がある。
However, in this case, the critical path that determines the processing speed is a loop of 3-input 2-output D/D converter 1, adder 2, FF 3, quantizer 4, and multiplier 8, and the operating speed of multiplier 8 is If it is slow, there is a problem that the calculation speed for prediction is slow.
上記問題点は、出力側に、予測係数を乗算した
後量子化DPCM信号を発生する機能を一体化し
た量子化器を備え、又第１の加算器及び第１の乗
算器及び第１の遅延素子を有し、且つ該第１の乗
算器で該第１の加算器の出力に予測係数を乗算
し、この出力を該第１の遅延素子にて遅延させ、
該量子化器の出力とともに該第１の加算器に入力
し、該第１の遅延素子の出力で予測値を検出する
予測値検出ループと、
入力するPCM信号に予測係数の逆数を乗算し
た信号を第１の入力に入力し、第２の入力に該量
子化器の出力を、第３の入力に該第１の遅延素子
の出力を各々反転して入力し、該第１〜第３の入
力に入力する入力信号の各桁毎の全加算を行い、
各桁毎の、桁上げ出力と加算結果の２出力とする
３入力２出力デイジタル・デイジタル変換器を備
え、該３入力２出力Ｄ／Ｄ変換器の各桁毎の２出
力を各桁毎に加算する第２の加算器に入力し、該
３入力２出力Ｄ／Ｄ変換器と該第２の加算器によ
り、該第１の入力に入力する信号に対し、該第
２，第３の入力に入力する信号は反転して入力し
加算を行わせ、該第２の加算器の出力を第２の遅
延素子にて遅延させ、又該第２の遅延素子の出力
を該量子化器に入力するようにした本発明の高速
DPCM回路により解決される。
The above problem is that the output side is equipped with a quantizer that integrates the function of generating a quantized DPCM signal after multiplying by a prediction coefficient, and the first adder, the first multiplier, and the first delay the first multiplier multiplies the output of the first adder by a prediction coefficient, the output is delayed by the first delay element,
a predicted value detection loop that inputs the output of the quantizer to the first adder and detects a predicted value using the output of the first delay element; and a signal obtained by multiplying the input PCM signal by the reciprocal of the prediction coefficient. is inputted to the first input, the output of the quantizer is inputted to the second input, the output of the first delay element is inverted and inputted to the third input, and the output of the first to third delay elements is inputted to the second input. Performs full addition for each digit of the input signal input to the input,
Equipped with a 3-input 2-output digital-to-digital converter that outputs 2 outputs for each digit, a carry output and an addition result, and 2 outputs for each digit of the 3-input 2-output D/D converter. The signals input to the first input are input to the second and third inputs by the three-input two-output D/D converter and the second adder. The input signal is inverted and input to perform addition, the output of the second adder is delayed by a second delay element, and the output of the second delay element is input to the quantizer. The high speed of the present invention
Solved by DPCM circuit.
本発明では、従来の高速DPCM回路の第２の
遅延素子（第２図のFF３）の出力に、第２図の
量子化器４の代りに、予測係数を乗算した後量子
化DPCM信号を発生する機能を一体化した量子
化器を設置し、第２図の乗算器８の分だけ動作速
度を速くし、その代りに、量子化器の出力及び１
標本化周期前の値（第２図のFF７の出力）に予
測係数を乗算せず、又入力するPCM信号に予測
係数の逆数を乗算して、３入力２出力Ｄ／Ｄ変換
器に入力し、第１図の乗算器６の動作速度が３入
力２出力Ｄ／Ｄ変換器の動作速度より早い場合に
クリテイカルパスは第２図の乗算器８の遅延分だ
け予測の為の演算速度を向上している。
In the present invention, instead of the quantizer 4 in FIG. 2, the output of the second delay element (FF3 in FIG. 2) of the conventional high-speed DPCM circuit is multiplied by a prediction coefficient and then a quantized DPCM signal is generated. A quantizer that integrates the function of
The value before the sampling period (output of FF7 in Figure 2) is not multiplied by the prediction coefficient, and the input PCM signal is multiplied by the reciprocal of the prediction coefficient and input to the 3-input 2-output D/D converter. , when the operating speed of the multiplier 6 in FIG. 1 is faster than the operating speed of the 3-input 2-output D/D converter, the critical path increases the calculation speed for prediction by the delay of the multiplier 8 in FIG. 2. It's improving.
第１図は本発明の実施例の予測係数1/2の場合
の、高速DPCM回路のブロツク図、第３図は３
入力２出力Ｄ／Ｄ変換器及び加算器及びフリツプ
フロツプ（FF）の接続を示す図である。
Fig. 1 is a block diagram of a high-speed DPCM circuit in the case of a prediction coefficient of 1/2 according to an embodiment of the present invention, and Fig. 3 is a block diagram of a high-speed DPCM circuit with a prediction coefficient of 1/2.
FIG. 2 is a diagram showing connections between an input-two-output D/D converter, an adder, and a flip-flop (FF).
図中、１０は予測係数1/2の逆数２を乗算する
乗算器、１１は予測係数1/2を乗算した後量子化
DPCM信号を発する機能を一体化した量子化器
を示しており、尚全図を通じ同一符号は同一機能
のものを示す。 In the figure, 10 is a multiplier that multiplies the reciprocal 2 of the prediction coefficient 1/2, and 11 is quantized after multiplying the prediction coefficient 1/2.
This figure shows a quantizer with an integrated function of emitting a DPCM signal, and the same reference numerals throughout the figures indicate the same functions.
第１図で第２図と異なる点は、FF３の出力に
量子化器１１を設け、ここで1/2が乗算されるの
で、その代わりに、第２図の量子化器４の出力及
びFF７の出力には1/2を乗算せず、又入力の
PCM信号は乗算器１０にて予測係数1/2の逆数２
を乗算し３入力２出力Ｄ／Ｄ変換器１に入力する
ようにした点である。 The difference between FIG. 1 and FIG. 2 is that the output of FF3 is provided with a quantizer 11, where it is multiplied by 1/2. The output of is not multiplied by 1/2, and the input
The PCM signal is the reciprocal of 1/2 of the prediction coefficient 2 in the multiplier 10.
The difference is that the multiplier is multiplied by 2 and input to the 3-input 2-output D/D converter 1.
このようにすれば、乗算器６の動作速度が３入
力２出力Ｄ／Ｄ変換器１の動作速度より早い場合
にクリテイカルパスは３入力２出力Ｄ／Ｄ変換器
１，加算器２，FF３，量子化器１１よりなるル
ープとなるため第２図に示す従来例に比し第２図
の乗算器８による遅延分だけ予測の為の演算速度
を向上出来るのは勿論である。 In this way, if the operating speed of the multiplier 6 is faster than the operating speed of the 3-input 2-output D/D converter 1, the critical path will be the 3-input 2-output D/D converter 1, the adder 2, and the FF3. , quantizer 11, it goes without saying that the calculation speed for prediction can be improved by the delay caused by the multiplier 8 in FIG. 2 compared to the conventional example shown in FIG.
又入力PCM信号に予測係数（第１図では1/2）
の逆数を乗算し、量子化器１１の出力及び１標本
化前の予測値には予測係数を乗算せず、３入力２
出力Ｄ／Ｄ変換器１に反転して入力し、３入力２
出力Ｄ／Ｄ変換器１及び加算器２にて加算を行つ
ているので、各信号のビツト数は従来に比し増加
し演算精度を向上出来る。 Also, a prediction coefficient (1/2 in Figure 1) is added to the input PCM signal.
The output of the quantizer 11 and the predicted value before one sampling are not multiplied by the prediction coefficient, and the 3-input 2
Invert and input to output D/D converter 1, 3 input 2
Since the addition is performed by the output D/D converter 1 and the adder 2, the number of bits of each signal is increased compared to the conventional case, and the calculation accuracy can be improved.
又FF３と量子化器１１の位置を逆にすると乗
算器６の遅延が３入力２出力Ｄ／Ｄ変換器１と量
子化器１１の遅延を加え合わせたものより小の時
従来例に比し第２図の乗算器８の遅延分だけ予測
の為の演算速度を向上出来る。 Also, when the positions of the FF 3 and the quantizer 11 are reversed, when the delay of the multiplier 6 is smaller than the sum of the delays of the 3-input 2-output D/D converter 1 and the quantizer 11, compared to the conventional example. The calculation speed for prediction can be improved by the delay of the multiplier 8 shown in FIG.
あるいは、FF７と乗算器６の位置を逆にする
と乗算器６の遅延が量子化器１１の遅延より小の
時は、従来例に比し第２図の乗算器８の遅延分だ
け予測の為の演算速度を向上出来る。 Alternatively, if the positions of FF 7 and multiplier 6 are reversed, when the delay of multiplier 6 is smaller than the delay of quantizer 11, prediction is made by the delay of multiplier 8 in FIG. 2 compared to the conventional example. The calculation speed can be improved.
次に、第３図を用い、第１図の３入力Ｄ／Ｄ変
換器１及び加算器２とFF３の詳細につき説明す
る。 Next, details of the three-input D/D converter 1, adder 2, and FF 3 shown in FIG. 1 will be explained using FIG. 3.
２進数を表す符号として２の補数を用い、入力
PCM信号を８ビツトとし、乗算器１０にて予測
係数1/2の逆数を乗算することによりＡ８〜Ａ０
の９ビツトとなり、量子化器１１の出力はＣ７〜
Ｃ０の８ビツト、FF７の出力はＢ８〜Ｂ０の９
ビツトとして以下説明する。 Using two's complement as the code representing the binary number, input
By setting the PCM signal to 8 bits and multiplying it by the reciprocal of the prediction coefficient 1/2 in the multiplier 10, A8 to A0
The output of the quantizer 11 is C7~
8 bits of C0, FF7 output is B8 to 9 of B0
This will be explained below as a bit.
３入力Ｄ／Ｄ変換器１の各桁の全加算器１―１
〜１―９の、キヤリー入力にはＡ０〜Ａ８の信号
が入力し、２入力にはＢ０〜Ｂ８，Ｃ０〜Ｃ７の
信号が各々反転して入力し（但しMSBの全加算
器１―９にはＡ８，Ｂ８，Ｃ７の信号が入力す
る）、全加算器１―１〜１―９の加算結果の出力
は、加算器２の各桁の全加算器２―１〜２―９に
入力し、桁上げ出力は１桁上の全加算器２―２〜
２―１０に入力する。 Full adder 1-1 for each digit of 3-input D/D converter 1
~1-9, the signals A0-A8 are input to the carry input, and the signals B0-B8, C0-C7 are inverted and input to the 2nd input (however, the MSB full adder 1-9 is input (signals of A8, B8, and C7 are input), and the outputs of the addition results of full adders 1-1 to 1-9 are input to full adders 2-1 to 2-9 of each digit of adder 2. , the carry output is from the full adder 2-2 ~
Enter in 2-10.
この場合、LSBの全加算器２―１の１入力及
びキヤリー入力にはＨレベルが加えられている。
又全加算器及びFFは３入力２出力Ｄ／Ｄ変換器
１の入力が９ビツト，９ビツト，８ビツト時、演
算結果が最大11ビツトになることがある為に11ケ
設けられている。 In this case, an H level is applied to the 1 input and carry input of the LSB full adder 2-1.
In addition, 11 full adders and FFs are provided because when the input of the 3-input 2-output D/D converter 1 is 9 bits, 9 bits, or 8 bits, the operation result may be a maximum of 11 bits.
全加算器２―１０には全加算器１―９の加算結
果出力が加えられており、又全加算器２―１１に
は全加算器１―９の加算結果出力及び桁上げ出力
が加えられており、全加算器２―１〜２―１０の
桁上げ出力は全加算器２―２〜２―１１に入力し
て演算が行われ、全加算器２―１〜２―１１の各
桁の出力はFF３―１〜３―１１に入力し遅延さ
れて量子化器１１に入力する。 The addition result output of the full adder 1-9 is added to the full adder 2-10, and the addition result output and carry output of the full adder 1-9 is added to the full adder 2-11. The carry outputs of full adders 2-1 to 2-10 are input to full adders 2-2 to 2-11 for calculation, and each digit of full adders 2-1 to 2-11 is The outputs are input to the FFs 3-1 to 3-11, delayed, and input to the quantizer 11.
第３図に示す如く、３入力Ｄ／Ｄ変換器１は、
入力信号の各桁毎の全加算を行い、桁上げ出力と
加算結果の出力の２出力とし、この２出力の内加
算結果の出力は加算器２の対応桁の全加算器に入
力し、桁上げ出力は１桁上の全加算器に入力す
る。 As shown in FIG. 3, the 3-input D/D converter 1 is
Full addition is performed for each digit of the input signal, resulting in two outputs: a carry output and an output of the addition result. Out of these two outputs, the output of the addition result is input to the full adder of the corresponding digit of adder 2, and the digit The raised output is input to the full adder one digit higher.
従つて、３入力Ｄ／Ｄ変換器１では全桁を通し
ての演算は行わないので、桁上げ処理を含み全桁
の演算を行う加算器，減算器に比し動作速度が速
くなる。 Therefore, since the three-input D/D converter 1 does not perform calculations on all digits, its operation speed is faster than that of adders and subtracters that perform calculations on all digits including carry processing.
以上詳細に説明せる如く本発明によれば、予測
の為の演算速度を向上出来る効果がある。
As explained in detail above, according to the present invention, there is an effect that the calculation speed for prediction can be improved.
第１図は本発明の実施例の高速DPCM回路の
ブロツク図、第２図は従来例の高速DPCM回路
のブロツク図、第３図は３入力２出力デイジタ
ル・デイジタル変換器及び加算器及びフリツプフ
ロツプの接続を示す図である。
図において、１は、３入力２出力デイジタル・
デイジタル変換器、２，５は加算器、３，７は
FF、４，１１は量子化器、６，８，９，１０は
乗算器を示す。
FIG. 1 is a block diagram of a high-speed DPCM circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional high-speed DPCM circuit, and FIG. It is a diagram showing connections. In the figure, 1 is a 3-input, 2-output digital
Digital converter, 2 and 5 are adders, 3 and 7 are
FF, 4, and 11 are quantizers, and 6, 8, 9, and 10 are multipliers.
Claims (1)
DPCM信号を発生する機能を一体化した量子化
器を備え、又第１の加算器及び第１の乗算器及び
第１の遅延素子を有し、且つ該第１の乗算器で該
第１の加算器の出力に予測係数を乗算し、この出
力を該第１の遅延素子にて遅延させ、該量子化器
の出力とともに該第１の加算器に入力し、該第１
の遅延素子の出力で予測値を検出する予測値検出
ループと、 入力するPCM信号に予測係数の逆数を乗算し
た信号を第１の入力に入力し、第２の入力に該量
子化器の出力を、第３の入力に該第１の遅延素子
の出力を各々反転して入力し、該第１〜第３の入
力に入力する入力信号の各桁毎の全加算を行い、
各桁毎の、桁上げ出力と加算結果の２出力とする
３入力２出力デイジタル・デイジタル変換器を備
え、該３入力２出力デイジタル・デイジタル変換
器の各桁毎の２出力を各桁毎に加算する第２の加
算器に入力し、該３入力２出力デイジタル・デイ
ジタル変換器と該第２の加算器により、該第１の
入力に入力する信号に対し、該第２，第３の入力
に入力する信号は反転して入力し加算を行わせ、
該第２の加算器の出力を第２の遅延素子にて遅延
させ、又該第２の遅延素子の出力を該量子化器に
入力するようにしたことを特徴とする高速
DPCM回路。[Claims] 1. Quantization after multiplying the output side by a prediction coefficient
The quantizer has a quantizer integrated with a function of generating a DPCM signal, and also has a first adder, a first multiplier, and a first delay element, and the first multiplier The output of the adder is multiplied by a prediction coefficient, this output is delayed by the first delay element, and is input to the first adder together with the output of the quantizer.
A predicted value detection loop that detects a predicted value using the output of a delay element, a signal obtained by multiplying the input PCM signal by the reciprocal of the predicted coefficient is input to the first input, and the output of the quantizer is input to the second input. Input each inverted output of the first delay element to the third input, perform full addition for each digit of the input signal input to the first to third inputs,
A 3-input, 2-output digital-to-digital converter with two outputs, a carry output and an addition result, is provided for each digit, and two outputs for each digit of the three-input, two-output digital-to-digital converter are provided for each digit. The 3-input 2-output digital-to-digital converter and the second adder add the second and third inputs to the signal input to the first input. The input signal is inverted and added,
A high speed device characterized in that the output of the second adder is delayed by a second delay element, and the output of the second delay element is input to the quantizer.
DPCM circuit.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59245775A JPS61125233A (en) | 1984-11-20 | 1984-11-20 | High-speed dpcm circuit |
| DE8585110978T DE3586932T2 (en) | 1984-08-30 | 1985-08-30 | DIFFERENTIAL CODING CIRCUIT. |
| EP85110978A EP0173983B1 (en) | 1984-08-30 | 1985-08-30 | Differential coding circuit |
| KR1019850006333A KR890004441B1 (en) | 1984-08-30 | 1985-08-30 | Automatic cording circuit |
| CA000489802A CA1338767C (en) | 1984-08-30 | 1985-08-30 | Differential coding circuit |
| US07/049,048 US4771439A (en) | 1984-08-30 | 1987-05-12 | Differential coding circuit with reduced critical path applicable to DPCM |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59245775A JPS61125233A (en) | 1984-11-20 | 1984-11-20 | High-speed dpcm circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61125233A JPS61125233A (en) | 1986-06-12 |
| JPH0243375B2 true JPH0243375B2 (en) | 1990-09-28 |
Family
ID=17138628
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59245775A Granted JPS61125233A (en) | 1984-08-30 | 1984-11-20 | High-speed dpcm circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61125233A (en) |
-
1984
- 1984-11-20 JP JP59245775A patent/JPS61125233A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61125233A (en) | 1986-06-12 |
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