JPS6167129A - Parallel multiplication circuit - Google Patents
Parallel multiplication circuitInfo
- Publication number
- JPS6167129A JPS6167129A JP18756984A JP18756984A JPS6167129A JP S6167129 A JPS6167129 A JP S6167129A JP 18756984 A JP18756984 A JP 18756984A JP 18756984 A JP18756984 A JP 18756984A JP S6167129 A JPS6167129 A JP S6167129A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- multiplier
- unit
- unit circuit
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
- G06F7/5332—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by skipping over strings of zeroes or ones, e.g. using the Booth Algorithm
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、並列乗算回路に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to parallel multiplication circuits.
２進数の演算装置として、全加算器（フルアダー）とア
ンドゲートＹ組合せた単位回路を桁数Ｘ桁数だけ行列状
に配置して乗算を行う、並列乗算回路がある。As a binary number arithmetic device, there is a parallel multiplication circuit that performs multiplication by arranging unit circuits, each of which is a combination of a full adder and an AND gate Y, in a matrix of X digits.
第２図は従来の並列乗算回路を示す。これは。FIG. 2 shows a conventional parallel multiplier circuit. this is.
４桁の２進数の並列乗算回路であり、４行４列に配置さ
れた１６個の単位回路ＭＦＡで構成されている。４桁の
乗数、被乗数をそれぞれ。This is a 4-digit binary parallel multiplication circuit, and is composed of 16 unit circuits MFA arranged in 4 rows and 4 columns. 4-digit multiplier and multiplicand, respectively.
７４ｓ７３＊）’ｔ＋３’Ｉ ； ）Ｃ４ｖ”３ｔ”
！會ｘｌ とし・その乗算結果をＰ８ 、Ｐ７ 、Ｐ
６ 、Ｐ５ 、Ｐ４ 。74s73*)'t+3'I;)C4v"3t"
! Let xl be xl, and the multiplication results are P8, P7, P
6, P5, P4.
Ｐ３ 、Ｐ２ 、ＰＩで表わしている。They are represented by P3, P2, and PI.
第鷺図は第淘図の単位回路ＭＦＡの構成と入出力信号関
係を示す。単位回路は全加算器ＦＡとアンドゲートＧと
から構成されている。ＣＩ。Fig. 3 shows the configuration of the unit circuit MFA shown in Fig. 1 and the relationship between input and output signals. The unit circuit is composed of a full adder FA and an AND gate G. C.I.
Ｃｏは各単位回路の桁上は入出力であり、Ｘ。Co is the input/output of each unit circuit, and X.
Ｙはそれぞれ被乗数１乗数の１桁であり、８Ｉ。Y is each one digit of the multiplicand 1 multiplier, and is 8I.
ＳＯはそれぞれ和の入出力である。これらの信号の間に
は次のような論理式が成立つ。SO is the input and output of the sum, respectively. The following logical formula holds between these signals.
この方式では１桁上は乞いわゆるリップルキャリ一方式
により行う ので１桁上は信号が最終段のＰ７ 、Ｐ８
ｆ２ｒ：出力する・単位回路ＭＦＡに到達するまでに、
その前の全ての単位回路ＭＦＡを通ることになる。第２
図の場合、４桁の乗算回路であるため１桁上は信号は１
０個の単位回路ＭＦＡを通るが、一般にｎ桁の乗算回路
では３ｎ−２個の単位回路を通過しなければならない。In this method, one digit higher is carried out using the so-called ripple carry one-way method, so the signal one digit higher is the final stage P7, P8.
f2r: Output ・By the time it reaches the unit circuit MFA,
It passes through all the unit circuits MFA before that. Second
In the case of the figure, since it is a 4-digit multiplication circuit, the signal one digit higher is 1.
The signal passes through 0 unit circuits MFA, but generally in an n-digit multiplication circuit, it must pass through 3n-2 unit circuits.
本発明は上記の点１：鑑み１乗算回路のゲート数を徒ら
に増加させることなく、各単位回路に規則的な回路を付
加して演算速度の向上を図った並列乗算回路を提供する
こと・を目的とする。The present invention is directed to the above point 1: In view of the above, it is an object of the present invention to provide a parallel multiplier circuit that improves the calculation speed by adding regular circuits to each unit circuit without unnecessarily increasing the number of gates in the multiplier circuit. ·With the goal.
本発明は、行列状に配置される各単位回路に。 The present invention applies to each unit circuit arranged in a matrix.
この回路への入力である乗数がＯである場合に前段の和
の出力をこの回路を通過することなくバイノクスさせる
伝送ゲートを付加したことを特徴とする。The circuit is characterized in that, when the multiplier input to this circuit is O, a transmission gate is added which causes the output of the sum of the previous stage to be binoxed without passing through this circuit.
本発明に係る並列乗算回路では、ある行の単位回路の乗
数入力が０である場合、和の入力はこの単位回路導通る
ことなく伝送ゲートでパイ、？スされて次段の単位回路
に入力される。この場合、単位回路の桁上は信号がそ、
の行の左端の単位回路に到達するのを待つことなく１次
段の単位（ロ）路での演算が開始される。即ち乗数にＯ
がある桁では、単位回路を通過することなく伝送ゲート
だけを通過して信号が伝播される。In the parallel multiplier circuit according to the present invention, when the multiplier input of a unit circuit in a certain row is 0, the sum input is pi, ? at the transmission gate without conduction in this unit circuit. and input to the next stage unit circuit. In this case, the signal on the unit circuit is
The operation in the unit circuit of the first stage is started without waiting for the unit circuit at the left end of the row to be reached. In other words, the multiplier is O
At a certain digit, the signal is propagated through only the transmission gate without passing through the unit circuit.
従って本発明によれば１乗数Ｃ二含まれる０の個数が多
い場合には乗算時間の短縮化が可能となる。Therefore, according to the present invention, when the number of zeros included in the first multiplier C2 is large, the multiplication time can be shortened.
以下本発明を実施例により具体的に説Ｉ！―する。 The present invention will be explained in detail below using examples. -do.
第１図は、第２図の回路に本発明を適用した実施例の並
列乗算回路である。第１行を除く各行の単位回路、伸ち
前段の単位回路の和出力が入力される各単位回路に、伝
送ゲートＧＩ、Ｇ２を付加している点で第２図と異なる
。Ｇ、は反転ゲートであり、乗数ｙｉ（ｉ＝２．３．４
）に応じて伝送ゲー）Ｇ、、Ｇ、を制御するよう１ユな
っている。即ち伝送ゲートＧ１は１乗数ｙｌがＯの場合
に導通して各単位回路ＭＦＡへの前段の和出力を次段の
単位回路へ直結させるバイパスとなる。乗数ｙ１が１の
場合には、この伝送ゲートＧ、は非導通で伝送ゲートＧ
、が導通状態となり、従来の第２図と等価な回路となる
。FIG. 1 shows a parallel multiplier circuit according to an embodiment in which the present invention is applied to the circuit shown in FIG. This differs from FIG. 2 in that transmission gates GI and G2 are added to each unit circuit in each row except the first row and to each unit circuit into which the sum output of the unit circuit in the previous stage of expansion is input. G is an inversion gate, and the multiplier yi (i=2.3.4
) to control the transmission game )G, ,G, according to the That is, the transmission gate G1 becomes conductive when the first multiplier yl is O, and serves as a bypass that directly connects the sum output of the previous stage to each unit circuit MFA to the next stage unit circuit. When the multiplier y1 is 1, this transmission gate G is non-conductive and the transmission gate G is non-conductive.
, becomes conductive, resulting in a circuit equivalent to the conventional circuit shown in FIG.
このような回路が実現できる遅出を以下、論理式を用い
て説明する。いま１乗数ｙ、がＯでとなる。ここで第２
行の右端の単１位回路ＭＦＡにおいて、Ｃに〇であるか
ら、Ｃ０＝０である。そして各単位回路のＣＯは左に隣
接する単位回路のＣＩであるから、結局、第２行の４つ
の単位回路において、全てＣＩ＝Ｑとなる。ゆえに。The delay output that can be realized by such a circuit will be explained below using a logical formula. Now, the 1st multiplier y is O. Here the second
In the single-digit circuit MFA at the right end of the row, C is 0, so C0=0. Since the CO of each unit circuit is the CI of the unit circuit adjacent to the left, CI=Q in all four unit circuits in the second row. therefore.
８０＝８１■ＣＩ＝８Ｉ ・・・（３）が
成り立ち１乗数ｙ２が０であれば、第２行の４つの単位
回路においてＳＩとＳＯを直結させてよいことになる。80=81■CI=8I If (3) holds true and the 1 multiplier y2 is 0, it is possible to directly connect SI and SO in the four unit circuits in the second row.
この１乗数ｙ、が０のときに８ＩとＳＯを直結させるの
が伝送ゲートＧ１である。第３行、第４行の単位回路に
ついても同様である。When this 1 multiplier y is 0, the transmission gate G1 connects 8I and SO directly. The same applies to the unit circuits in the third and fourth rows.
このように本実施例によれば、２個の伝送ゲ−Ｆ ＧＩ
＋ ＧＩからなる回路ン各単位回路に組合わせるこ
とにより１乗数ｙ１が０である場合は第１行の単位回路
を飛び越して前段の単位回路に入力される。単位回路を
信号が通過するには通常数段のゲートを通ることになる
が１本実施例では１乗数ｙｉがＯの行では１段の伝送ゲ
ートＧ、を通過するだけでよい。従って単位回路の通過
個数が減少し、演算時間の高速化が実現される。As described above, according to this embodiment, two transmission games F GI
+ GI circuits are combined with each unit circuit, and when the 1 multiplier y1 is 0, the signal is inputted to the unit circuit in the previous stage by skipping the unit circuit in the first row. In order for a signal to pass through a unit circuit, it normally passes through several stages of gates, but in this embodiment, in a row where the first multiplier yi is O, the signal only needs to pass through one stage of transmission gate G. Therefore, the number of unit circuits passing through is reduced, and the calculation time is increased.
本発明は上記した実施例に限られるものではなく、その
趣旨を逸脱しない範囲で種々変形実施することが可能で
ある。The present invention is not limited to the embodiments described above, and various modifications can be made without departing from the spirit thereof.
第１図は本発明の一実施例Ｃ二係る並列乗算回路を示す
図、第２図は従来の並列乗算回路を示す図、第３図は並
列乗算回路における単位回路を示す図である。
ＭＦＡ・・・単位回路−ＧＩ ＊ Ｇｚ・・・伝送ゲー
ト。
Ｇ３・・・反転ゲート。FIG. 1 is a diagram showing a parallel multiplication circuit according to Embodiment C2 of the present invention, FIG. 2 is a diagram showing a conventional parallel multiplication circuit, and FIG. 3 is a diagram showing a unit circuit in the parallel multiplication circuit. MFA...Unit circuit-GI*Gz...Transmission gate. G3...Reversal gate.
Claims (1)
列状に配置して構成され２進数の乗算を行う並列乗算回
路において、前段の和出力が入力される各単位回路に、
その行に入力される乗数が０のときに前記・前段の和出
力を次段の単位回路の和入力端へバイパスさせる伝送ゲ
ートを付加したことを特徴とする並列乗算回路。In a parallel multiplication circuit that multiplies binary numbers and is configured by arranging multiple unit circuits in a matrix that combine full adders and AND gates, each unit circuit to which the sum output of the previous stage is input,
A parallel multiplier circuit characterized in that a transmission gate is added that bypasses the sum output of the previous stage to the sum input terminal of the next stage unit circuit when the multiplier input to that row is 0.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18756984A JPS6167129A (en) | 1984-09-07 | 1984-09-07 | Parallel multiplication circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18756984A JPS6167129A (en) | 1984-09-07 | 1984-09-07 | Parallel multiplication circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6167129A true JPS6167129A (en) | 1986-04-07 |
Family
ID=16208389
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18756984A Pending JPS6167129A (en) | 1984-09-07 | 1984-09-07 | Parallel multiplication circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6167129A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008533617A (en) * | 2005-03-17 | 2008-08-21 | クゥアルコム・インコーポレイテッド | Method for multiplying two operands and array multiplier |
-
1984
- 1984-09-07 JP JP18756984A patent/JPS6167129A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008533617A (en) * | 2005-03-17 | 2008-08-21 | クゥアルコム・インコーポレイテッド | Method for multiplying two operands and array multiplier |
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