JPS58192359A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS58192359A JPS58192359A JP57075334A JP7533482A JPS58192359A JP S58192359 A JPS58192359 A JP S58192359A JP 57075334 A JP57075334 A JP 57075334A JP 7533482 A JP7533482 A JP 7533482A JP S58192359 A JPS58192359 A JP S58192359A
- Authority
- JP
- Japan
- Prior art keywords
- type
- well
- layer
- region
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000004020 conductor Substances 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0925—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising an N-well only in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置、％ＫＣＭＯ８に関するものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, %KCMO8.
０ＭＯ８は−ＢＫ、例えばＮｇエピタキシ考ル層自体に
設けたＰチャネルＭ Ｉ Ｓ Ｆ Ｅ Ｔ（Ｍｅｔａｌ
Ｉｎｓｕｌａｔｏｒ Ｓｅｍ１ｃｏｎｄｕｃｔｏｒ
Ｆｉｅｌｄ ＥｆｆｅｃｔＴｒａｎｓｉｓｔｏｒ
）と、同エピタキシ今ル層に形成されたＰ〜ルウエル設
けたヘチャネルＭＩＳＦＥＴとからなっている。このよ
うなＣＭＯ８Ｙ高速化するには、各ＭＩＳＦＥＴのソー
ス又はドレイン領域の接合容量を減らすことが会費であ
るが、このために基板バイアス電圧（ｖＢＢ）′ｌｋ：
印加することがある。ところが他方では、高集積化に伴
なう微細化の豊水によりＭＩＳＦＥＴのシ■−トチャネ
ル化を図ろうとする場合には、■□の印加はしきい値電
圧（Ｖｔｈ）の変動ン大きくしてしまう。0MO8 is -BK, for example, a P channel MISFET (Metal) provided in the Ng epitaxial layer itself.
Insulator Sem1conductor
Field Effect Transistor
) and a he-channel MISFET provided with a P~ruwell formed in the same epitaxial layer. To increase the speed of such a CMO8Y, it is necessary to reduce the junction capacitance of the source or drain region of each MISFET, but for this purpose, the substrate bias voltage (vBB)'lk:
may be applied. However, on the other hand, when trying to make a MISFET a sheet channel due to the abundance of miniaturization accompanying high integration, the application of ■□ will increase the fluctuation of the threshold voltage (Vth). Put it away.
このため、接合容量の低減とシ冒−トチャネル化との双
方を両立させることは不可能である。Therefore, it is impossible to achieve both reduction of junction capacitance and formation of a blank channel.
本発明はこうした状況において、上記の両立を可能とな
し、高速化・を効果的に実現することン目的とし、この
ためＫＰＭＰェル及びＮｍウェルを共Ｋ１１ｌ囲から分
離して形成している。Under such circumstances, the present invention aims to achieve both of the above requirements and to effectively achieve high speed. For this purpose, both the KPMP well and the Nm well are formed separately from the K11l surroundings.
以下、本発明＋ｌ−ＣＭＯ８ＭＩダイナミックランダム
アクセスメモリに関する実施例について詳細に説明する
。Hereinafter, embodiments relating to the +l-CMO8MI dynamic random access memory of the present invention will be described in detail.
図面に示した如く、本例によれば、Ｐ＋型シリコン基板
ｌの一生面忙、通常の半導体技術によってＮ＋諧棚込み
層２，３ｖ弁しＰ型エピタキシ々ル層４が成長せしめら
れ、このエピタキシ今ル層４ＫＮｆｆｉウェル５が拡散
法で形成されている。Ｎ諧つェル５はＮ＋ ｔＩｉ寝込
み層２に接して形成され、かつその側部には場込み層２
と一体の高湯度Ｎ＋型半導体領域６が形成されており、
これによってＮ型ウェル５はその側部及び底部に存在す
るＮ＋型領領域６２のために、＠部及び抵Ｓを包囲する
Ｐ型餉竣４，１から光分く分離されている。このＮ型ウ
ェル５には、周辺回路のＣＭＯ８Ｙ構成するＰ？ヤネル
ＭＩＳＦＥＴのソースヌはドレイン領域とじ℃のＰ＋型
半導体餉領域、８が形成され、これら両領埴間のゲート
酸化膜９上にはゲート電極ｌＯが設けられている。一方
、０ＭＯ８のへチャネルＭＩＳＦＥＴは、エピタキシキ
ル層４に形成されたＮ＋淑半導体慎域１１．１２（ソー
ス又はドレイン領域）と、ゲート酸化膜９上のゲート電
極ｌＯとによって構成されている。As shown in the drawing, according to this example, during the entire life of a P+ type silicon substrate 1, a P type epitaxial layer 4 is grown using normal semiconductor technology, and a P type epitaxial layer 4 is grown thereon. An epitaxial well layer 4KNffi well 5 is formed by a diffusion method. The N well 5 is formed in contact with the N+ tIi bed layer 2, and the field layer 2 is formed on the side thereof.
A high-temperature N+ type semiconductor region 6 is formed integrally with the
As a result, the N-type well 5 is optically separated from the P-type well 4,1 surrounding the @ part and the resistor S due to the N+ type region 62 present on its side and bottom. This N-type well 5 contains P? which constitutes CMO8Y of the peripheral circuit. In the source of the Yanel MISFET, a drain region and a P+ type semiconductor layer 8 are formed, and a gate electrode 10 is provided on a gate oxide film 9 between these two regions. On the other hand, the 0MO8 he channel MISFET is constituted by N+ semiconductor regions 11 and 12 (source or drain regions) formed in the epitaxy layer 4 and a gate electrode lO on the gate oxide film 9.
また、メモリセル（図面には簡略化のために１つのＮｆ
ヤネルＭＩＳＦＥＴのみｔ示している。）はエピタキシ
セル層４に設けられるが、その素子領域の側部及び底部
は高一度Ｎ＋型拡散領域１３及びＮ＋＋埋込み層３によ
って包囲されている。In addition, a memory cell (one Nf is shown in the drawing for simplicity)
Only the Yarnel MISFET is shown. ) is provided in the epitaxial cell layer 4, and the sides and bottom of the device region are surrounded by a high-temperature N+ type diffusion region 13 and an N++ buried layer 3.
従って、その素子慣塚は周囲が浚導電型領域で囲まれた
ＰｆＭウェル４として用いられる。このウェル内にはソ
ース又はドレイン領域としてのＮｍｍ線域１１１２が形
成され、ゲート電極１０と共にメモリセルのＦＥＴ）ｌ
構成している。なお、図中、１４はフィールドＳ ｉＱ
、膜、１５はリンガラス膜、１６．１７はアルミニウム
配線である。なお、上記の各Ｎ＋型領１１Ｉ６．１３は
共通の拡散工程で形成可能であるが、一方のＮ 島’Ｉ
Ｉ域６は必すしも形成すること）ｋ’ｌｌない。Therefore, the element cavity is used as a PfM well 4 surrounded by a conductive type region. In this well, an Nmm line region 1112 is formed as a source or drain region, and together with the gate electrode 10, the FET of the memory cell is formed.
It consists of In addition, in the figure, 14 is the field S iQ
, 15 is a phosphor glass film, and 16.17 is an aluminum wiring. Note that each of the above N+ type regions 11I6.13 can be formed by a common diffusion process, but one of the N+ type regions 11I6.13
I area 6 is not necessarily formed).
上記の如く、各Ｐａｌ！ウェル及びＮ型ウェルが夫々独
立したウェルとして形成されているので、各ウェルに作
成する個々のトランジスタに対し、必要に応じて他のウ
ェルのものとは別個に基板バイアス電圧（Ｖ、、 ）’
ｔ−ウ゛エルに印加することかできる。即ち、互いに独
立した各ウェルには選択的に■ＢＢｔ印加できるから、
その印加されたウェル内では接合容量が減少し、高速化
ン効果的Ｋｌ！３ｎできることになる。他方、ＶＢＢＹ
印加した（ないウェルでは、基板バイアスケしないよう
にできるか （ら、シ、−）チャネル化ン遍
成でき、上記した接合容量の減少と両立させた構造とな
る。具体的には、メモリセルでは上記Ｐａｌウェル４の
基板ノ（イアスによる接合＠量の減少でその高速化Ｙ図
れ、。As mentioned above, each Pal! Since the well and the N-type well are each formed as independent wells, the substrate bias voltage (V, , )' is applied to each transistor formed in each well separately from that of other wells as necessary.
It can also be applied to the t-well. That is, since ■BBt can be selectively applied to each well independently of each other,
In the applied well, the junction capacitance decreases and the effective Kl! You will be able to do 3n. On the other hand, VBBY
In wells where voltage is not applied, it is possible to avoid substrate bias. By reducing the amount of bonding due to the substrate of the Pal well 4, the speed can be increased.
かつ周辺回路ではＮ型ウェル５ｔｔむ基板）（イアスｔ
なくしてしきい値電圧（Ｖｔｈ）の変１ｔｈｙｔ少なく
し、シ１−トチ々ネル化又は高速化ン図れることになる
。加えて、Ｎ型ウェル５はＩｎ２囲の卜 層領域６，２
によってより低抵抗化することができるので、ノイズ、
電位変ｌｉ！ｌＹ：抑えることかできる。In addition, in the peripheral circuit, a substrate with an N-type well 5tt) (Iast
By eliminating this, the variation in threshold voltage (Vth) can be reduced by 1 th, and it is possible to increase the channel speed or increase the speed. In addition, the N-type well 5 is surrounded by In2 layer regions 6, 2.
Since the resistance can be lowered by
Potential change li! lY: Can be suppressed.
なお、上記の例において、エピタキシ々ル層４ｔＮ製と
し、これにＰｍウェルを拡散法で形成してよい。この場
合には、Ｎ”！！Ｓ！ｍ込み層はＰ“湯濶込み層に変更
する必要がある。In the above example, the epitaxial layer may be made of 4tN, and the Pm well may be formed thereon by a diffusion method. In this case, the N''!!S!m layer needs to be changed to the P'' layer.
図面は本発明の実施例によるＣＭＯ８型ダイ型ダイグミ
ツクランダムアクセスメモリの断面図である。
２．３・・・場込み層、４，５・・・ウェル、６，１３
・・・高濃度領域。The drawing is a cross-sectional view of a CMO 8 die type digital random access memory according to an embodiment of the present invention. 2.3...field layer, 4,5...well, 6,13
...High concentration area.
Claims (1)
して形成され、これらの各ウェルの側部及び底部が半導
体基板に対して、もしくは、ウェル領域に対し１逆導電
型の中導体慎域によって包囲されていることＶ＊徴とす
る半導体装置。1. A predetermined semiconductor layer KP-type well and N-type well are formed separately, and the sides and bottom of each of these wells are connected to the semiconductor substrate or to the well region with a middle conductor of opposite conductivity type. A semiconductor device characterized by V* being surrounded by a region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57075334A JPS58192359A (en) | 1982-05-07 | 1982-05-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57075334A JPS58192359A (en) | 1982-05-07 | 1982-05-07 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58192359A true JPS58192359A (en) | 1983-11-09 |
| JPH0410227B2 JPH0410227B2 (en) | 1992-02-24 |
Family
ID=13573248
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57075334A Granted JPS58192359A (en) | 1982-05-07 | 1982-05-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58192359A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6050953A (en) * | 1983-08-31 | 1985-03-22 | Toshiba Corp | Radiation resistant semiconductor element |
| JPS629665A (en) * | 1985-07-05 | 1987-01-17 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| EP0319047A2 (en) * | 1987-12-04 | 1989-06-07 | Nissan Motor Co., Ltd. | Power integrated circuit |
| US4928157A (en) * | 1988-04-08 | 1990-05-22 | Kabushiki Kaisha Toshiba | Protection diode structure |
| EP0384396A2 (en) * | 1989-02-20 | 1990-08-29 | Kabushiki Kaisha Toshiba | Bi-CMOS semiconductor device having memory cells formed in isolated wells |
| EP0493659A2 (en) * | 1991-01-02 | 1992-07-08 | International Business Machines Corporation | PMOS wordline boost circuit for dram |
| EP0498251A2 (en) * | 1991-02-05 | 1992-08-12 | International Business Machines Corporation | Word line driver circuit for dynamic random access memories |
| WO2006127751A3 (en) * | 2005-05-23 | 2009-04-16 | Amalfi Semiconductor Inc | Electrically isolated cmos device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5098791A (en) * | 1973-12-27 | 1975-08-06 | ||
| JPS5211883A (en) * | 1975-07-18 | 1977-01-29 | Toshiba Corp | Semiconductor integrated circuit device |
| JPS5211881A (en) * | 1975-07-18 | 1977-01-29 | Toshiba Corp | Semiconductor integrated circuit device |
| JPS5575265A (en) * | 1978-12-01 | 1980-06-06 | Fujitsu Ltd | Complementary type field-effect metal-insulator- semiconductor device |
| JPS5582461A (en) * | 1978-12-18 | 1980-06-21 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
| JPS55111171A (en) * | 1979-02-20 | 1980-08-27 | Mitsubishi Electric Corp | Field-effect semiconductor device |
-
1982
- 1982-05-07 JP JP57075334A patent/JPS58192359A/en active Granted
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5098791A (en) * | 1973-12-27 | 1975-08-06 | ||
| JPS5211883A (en) * | 1975-07-18 | 1977-01-29 | Toshiba Corp | Semiconductor integrated circuit device |
| JPS5211881A (en) * | 1975-07-18 | 1977-01-29 | Toshiba Corp | Semiconductor integrated circuit device |
| JPS5575265A (en) * | 1978-12-01 | 1980-06-06 | Fujitsu Ltd | Complementary type field-effect metal-insulator- semiconductor device |
| JPS5582461A (en) * | 1978-12-18 | 1980-06-21 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
| JPS55111171A (en) * | 1979-02-20 | 1980-08-27 | Mitsubishi Electric Corp | Field-effect semiconductor device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6050953A (en) * | 1983-08-31 | 1985-03-22 | Toshiba Corp | Radiation resistant semiconductor element |
| JPS629665A (en) * | 1985-07-05 | 1987-01-17 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| EP0319047A2 (en) * | 1987-12-04 | 1989-06-07 | Nissan Motor Co., Ltd. | Power integrated circuit |
| US4928157A (en) * | 1988-04-08 | 1990-05-22 | Kabushiki Kaisha Toshiba | Protection diode structure |
| EP0384396A2 (en) * | 1989-02-20 | 1990-08-29 | Kabushiki Kaisha Toshiba | Bi-CMOS semiconductor device having memory cells formed in isolated wells |
| EP0493659A2 (en) * | 1991-01-02 | 1992-07-08 | International Business Machines Corporation | PMOS wordline boost circuit for dram |
| EP0498251A2 (en) * | 1991-02-05 | 1992-08-12 | International Business Machines Corporation | Word line driver circuit for dynamic random access memories |
| WO2006127751A3 (en) * | 2005-05-23 | 2009-04-16 | Amalfi Semiconductor Inc | Electrically isolated cmos device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0410227B2 (en) | 1992-02-24 |
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