JPS57121274A - Forming method for p-n junction - Google Patents

Forming method for p-n junction

Info

Publication number
JPS57121274A
JPS57121274A JP638381A JP638381A JPS57121274A JP S57121274 A JPS57121274 A JP S57121274A JP 638381 A JP638381 A JP 638381A JP 638381 A JP638381 A JP 638381A JP S57121274 A JPS57121274 A JP S57121274A
Authority
JP
Japan
Prior art keywords
substrate
film
boron
junction
si3n4
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP638381A
Other languages
Japanese (ja)
Inventor
Ryoichi Fukuyama
Shiyuuji Kobayashi
Kenji Yoshinaga
Kousuke Tanaka
Kazuo Kaneko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP638381A priority Critical patent/JPS57121274A/en
Publication of JPS57121274A publication Critical patent/JPS57121274A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To obtain a P-N junction having short junction length by selectively forming an Si3N4 film on a substrate implanted with boron in a shallow depth, heat treating it, forming an SiO2 film which absorbs boron on the exposed part of the substrate, and diffusing the boron under the Si3N4 film in the sub strate. CONSTITUTION:Boron ions are implanted in 0.3mum from the surface in an N type Si substrate 5. A silicon nitride film 6 is selectively covered on the main surface of the substrate 5. The substrate 5 is heat treated, and an SiO2film 7 is formed on the Si exposed part not covered with the film 6. At this time, the boron existing in the vicinity of the surface of the substrate is all absorbed to the film 7, and the substrate becomes N type. On the other hand, the boron under the Si3N4 is activated to be diffused in the substrate, thereby forming a P type region 8. since the lower edge of the region 8 is shallower than the lower edge of the film 7, the end of the P-N junction 9 is faced with the side face of the film 7, but there is no increased diffusion length. In this manner, a diffused region which is smaller than the planar method can be formed
JP638381A 1981-01-21 1981-01-21 Forming method for p-n junction Pending JPS57121274A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP638381A JPS57121274A (en) 1981-01-21 1981-01-21 Forming method for p-n junction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP638381A JPS57121274A (en) 1981-01-21 1981-01-21 Forming method for p-n junction

Publications (1)

Publication Number Publication Date
JPS57121274A true JPS57121274A (en) 1982-07-28

Family

ID=11636856

Family Applications (1)

Application Number Title Priority Date Filing Date
JP638381A Pending JPS57121274A (en) 1981-01-21 1981-01-21 Forming method for p-n junction

Country Status (1)

Country Link
JP (1) JPS57121274A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05243020A (en) * 1992-03-02 1993-09-21 Rohm Co Ltd Chip network type resistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05243020A (en) * 1992-03-02 1993-09-21 Rohm Co Ltd Chip network type resistor

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