JPS57120332A - Selectively diffusing method for semiconductor substrate - Google Patents

Selectively diffusing method for semiconductor substrate

Info

Publication number
JPS57120332A
JPS57120332A JP706081A JP706081A JPS57120332A JP S57120332 A JPS57120332 A JP S57120332A JP 706081 A JP706081 A JP 706081A JP 706081 A JP706081 A JP 706081A JP S57120332 A JPS57120332 A JP S57120332A
Authority
JP
Japan
Prior art keywords
region
diffused
diffusion
substrate
grooves
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP706081A
Other languages
Japanese (ja)
Inventor
Takao Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP706081A priority Critical patent/JPS57120332A/en
Publication of JPS57120332A publication Critical patent/JPS57120332A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • H01L21/2233—Diffusion into or out of AIIIBV compounds

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To secure the diffusion to the desired region in a semiconductor substrate and to enhance the yield by isolating the surface of the substrate with grooves formed into the first and the second regions, covering the surface of the second region and the slots with diffusing mask to diffuse only in the exposed first region. CONSTITUTION:Grooves 14 are formed by etching on the surface of an N type GaP substrate 11, and the substrate 11 is isolated into the first region 12 to be diffused with diffusing substance later and the region 13 not necessary for the diffusion around the region 12. At this time the depth of the grooves 14 is formed deeper than the later diffusion depth. A diffusion mask 15 made of Si3N2 is covered from the side wall of the groove 14 to the non-diffused region 13. Thereafter, Zn is diffused by a sealing method in the first region 12 exposed later to obtain the desired P type region. In this manner, only the desired region can be diffused.
JP706081A 1981-01-19 1981-01-19 Selectively diffusing method for semiconductor substrate Pending JPS57120332A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP706081A JPS57120332A (en) 1981-01-19 1981-01-19 Selectively diffusing method for semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP706081A JPS57120332A (en) 1981-01-19 1981-01-19 Selectively diffusing method for semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS57120332A true JPS57120332A (en) 1982-07-27

Family

ID=11655515

Family Applications (1)

Application Number Title Priority Date Filing Date
JP706081A Pending JPS57120332A (en) 1981-01-19 1981-01-19 Selectively diffusing method for semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS57120332A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4826182A (en) * 1971-08-09 1973-04-05

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4826182A (en) * 1971-08-09 1973-04-05

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