JPS56122126A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS56122126A
JPS56122126A JP2551080A JP2551080A JPS56122126A JP S56122126 A JPS56122126 A JP S56122126A JP 2551080 A JP2551080 A JP 2551080A JP 2551080 A JP2551080 A JP 2551080A JP S56122126 A JPS56122126 A JP S56122126A
Authority
JP
Japan
Prior art keywords
layer
oxide
diffused
diffusing
depth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2551080A
Other languages
Japanese (ja)
Inventor
Kazunori Kawamoto
Shigeo Kanazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
NipponDenso Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NipponDenso Co Ltd filed Critical NipponDenso Co Ltd
Priority to JP2551080A priority Critical patent/JPS56122126A/en
Publication of JPS56122126A publication Critical patent/JPS56122126A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To form a diffused layer having different layer resistance and diffusing depth by one diffusion treatment by selectively forming an oxide preventive layer on an impurity glass layer formed on a semiconductor substrate surface and diffusing in an oxide atmosphere. CONSTITUTION:Glass layers (such as, phosphorus glass) 13, 14 containing impurity are formed in a thickness of approx. 1,000-14,000Angstrom on a P type Si substrate 11. After an oxide preventive layer 12 of Si3N4 or the like is subsequently selectively formed only on a desired region, it is diffused at 800-1,100 deg.C in oxide atmosphere such as oxygen, steam or the like to form diffused layers 15, 16 having different diffusion depth. Since an oxide film 17 is formed on the region where no oxide preventive layer 12 exists at the time of diffusing in this manner, the diffused layer 16 under this region is so formed as to be shallower in depth and lower in concentration than the layer 15. Accordingly, diffused layers having different layer resistance and diffusing depth can be formed by one treatment with preferable reproducibility.
JP2551080A 1980-02-29 1980-02-29 Manufacture of semiconductor device Pending JPS56122126A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2551080A JPS56122126A (en) 1980-02-29 1980-02-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2551080A JPS56122126A (en) 1980-02-29 1980-02-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56122126A true JPS56122126A (en) 1981-09-25

Family

ID=12168050

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2551080A Pending JPS56122126A (en) 1980-02-29 1980-02-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56122126A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6421918A (en) * 1987-07-16 1989-01-25 Fujitsu Ltd Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6421918A (en) * 1987-07-16 1989-01-25 Fujitsu Ltd Manufacture of semiconductor device

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