JPS5679444A - Semiconductor device and production thereof - Google Patents
Semiconductor device and production thereofInfo
- Publication number
- JPS5679444A JPS5679444A JP15553879A JP15553879A JPS5679444A JP S5679444 A JPS5679444 A JP S5679444A JP 15553879 A JP15553879 A JP 15553879A JP 15553879 A JP15553879 A JP 15553879A JP S5679444 A JPS5679444 A JP S5679444A
- Authority
- JP
- Japan
- Prior art keywords
- section
- high voltage
- layer
- element section
- resisting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
PURPOSE:To improve the reliability without impairing high integration degree by keeping an anti-inversion layer apart from an impurities diffused layer for high voltage resisting elements when a field oxide film is formed on a semiconductor substrate through the layer. CONSTITUTION:A thin SiO2 film 16 and an Si3N4 film 17 are laminated on a p type Si substrate 11 and undergoes a patterning to remove all but only leaving sections on a high voltage resisting element section A and a normal voltage section B. Only the laminated films on the high voltage resisting element section A are surrounded with an ion resisting injected mask made up of a resist or the like and B ion is injected to form p<+> type antiinversion layers 13 on a field region in the exposed section of the substrate 11. Then, after removal of the mask 17, a field oxide film 12 is provided by high temperature oxidation and the pattern is removed from the laminated films so that n<+> type regions 14a and 14b are respectively diffused into the high voltage resisting element section A and the normal voltage section B sandwitched by the layers 13. In this manner, in the element section A, the region 14a is kept apart from the antiinversion layer 13.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15553879A JPS5679444A (en) | 1979-12-03 | 1979-12-03 | Semiconductor device and production thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15553879A JPS5679444A (en) | 1979-12-03 | 1979-12-03 | Semiconductor device and production thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5679444A true JPS5679444A (en) | 1981-06-30 |
Family
ID=15608245
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15553879A Pending JPS5679444A (en) | 1979-12-03 | 1979-12-03 | Semiconductor device and production thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5679444A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5164876A (en) * | 1974-12-03 | 1976-06-04 | Nippon Electric Co | ZETSUENGEETOGATADENKAIKOKAHANDOTAISOCHINOSEIZOHOHO |
JPS54155538A (en) * | 1978-05-30 | 1979-12-07 | Murakami Kaimeido Kk | Automatic dazzling preventive mirror provided with automatic changeeover sensitivity correcting mechanism |
-
1979
- 1979-12-03 JP JP15553879A patent/JPS5679444A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5164876A (en) * | 1974-12-03 | 1976-06-04 | Nippon Electric Co | ZETSUENGEETOGATADENKAIKOKAHANDOTAISOCHINOSEIZOHOHO |
JPS54155538A (en) * | 1978-05-30 | 1979-12-07 | Murakami Kaimeido Kk | Automatic dazzling preventive mirror provided with automatic changeeover sensitivity correcting mechanism |
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