JPS56116618A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS56116618A
JPS56116618A JP1919780A JP1919780A JPS56116618A JP S56116618 A JPS56116618 A JP S56116618A JP 1919780 A JP1919780 A JP 1919780A JP 1919780 A JP1919780 A JP 1919780A JP S56116618 A JPS56116618 A JP S56116618A
Authority
JP
Japan
Prior art keywords
poly
film
sio2
substrate
oxidized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1919780A
Other languages
Japanese (ja)
Inventor
Nobuhisa Kubota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1919780A priority Critical patent/JPS56116618A/en
Publication of JPS56116618A publication Critical patent/JPS56116618A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To provide a thermally oxidized film without disturbing impurity distribution by eliminating an SiO2 film used for the formation of semiconductor circuit elements wherein an Si substrate is covered with a poly Si at 1,000 deg.C or below to oxidize the poly Si. CONSTITUTION:An SiO2 film is removed after providing a required diffusion layer on an Si substrate by using the SiO2 film. A poly Si film 7 is formed at 1,000 deg.C or below to apply Si3N4 mask 8 and the film 7 is changed to SiO2 7' by selectively oxidizing the poly Si at 1,000 deg.C or below. Al electrodes 9 are installed in the SiO2 7' by removing the mask 8. Then, treatment is done at 600 deg.C or below to apply the electrodes and the poly Si. In this composition, the Si substrate will not be oxidized and only the poly Si in which impurities are not diffused will be oxidized. Therefore, the change in impurity distribution will be prevented. And reliability will be improved as simple and accurate control during manufacturing processes for each characteristic of circuit elements is attained.
JP1919780A 1980-02-20 1980-02-20 Manufacture of semiconductor device Pending JPS56116618A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1919780A JPS56116618A (en) 1980-02-20 1980-02-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1919780A JPS56116618A (en) 1980-02-20 1980-02-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56116618A true JPS56116618A (en) 1981-09-12

Family

ID=11992619

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1919780A Pending JPS56116618A (en) 1980-02-20 1980-02-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56116618A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59149045A (en) * 1983-02-16 1984-08-25 Nec Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59149045A (en) * 1983-02-16 1984-08-25 Nec Corp Semiconductor device
JPH0425711B2 (en) * 1983-02-16 1992-05-01 Nippon Electric Co

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