JPS56169421A - Phase synchronizing circuit - Google Patents

Phase synchronizing circuit

Info

Publication number
JPS56169421A
JPS56169421A JP7315780A JP7315780A JPS56169421A JP S56169421 A JPS56169421 A JP S56169421A JP 7315780 A JP7315780 A JP 7315780A JP 7315780 A JP7315780 A JP 7315780A JP S56169421 A JPS56169421 A JP S56169421A
Authority
JP
Japan
Prior art keywords
circuit
converter
output
phase
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7315780A
Other languages
Japanese (ja)
Other versions
JPS6352496B2 (en
Inventor
Masaaki Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7315780A priority Critical patent/JPS56169421A/en
Publication of JPS56169421A publication Critical patent/JPS56169421A/en
Publication of JPS6352496B2 publication Critical patent/JPS6352496B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0624—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Color Television Systems (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To reduce the phase jitter due to quantized error of an A/D converter, by applying a given fine value within one step of this circut to an output of an error operating circuit which detects the shift from the reference phase. CONSTITUTION:An NTSC signal given to an input terminal 10 is digitized at an A/D converter 11 and outputted to an output terminal 12. On the other hand, the output of the converter 11 is fed to a synchronizing separation circuit 13, and the color burst signal is picked up from a burst pickup circuit 14 by the output. The phase of this color burst signal is compared with that of the reference signal at an error operating circuit 15, and a voltage controlled oscillator 18 is controlled through a D/A converter 16 and a filter 17 to form a sampling signal and it is fed to the A/D converter 11. Further the phase synchronizing loop has a bang-bang control characteristics by adding a given fine value from a digital level producing circuit by an addition circuit 50 51 to the output of the circuit 15, and the phase jitter of sampling signal can be reduced.
JP7315780A 1980-05-31 1980-05-31 Phase synchronizing circuit Granted JPS56169421A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7315780A JPS56169421A (en) 1980-05-31 1980-05-31 Phase synchronizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7315780A JPS56169421A (en) 1980-05-31 1980-05-31 Phase synchronizing circuit

Publications (2)

Publication Number Publication Date
JPS56169421A true JPS56169421A (en) 1981-12-26
JPS6352496B2 JPS6352496B2 (en) 1988-10-19

Family

ID=13510054

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7315780A Granted JPS56169421A (en) 1980-05-31 1980-05-31 Phase synchronizing circuit

Country Status (1)

Country Link
JP (1) JPS56169421A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62242422A (en) * 1986-04-15 1987-10-23 Sony Corp A/d conversion circuit for video signal
EP0461538A1 (en) * 1990-06-15 1991-12-18 ANT Nachrichtentechnik GmbH Hybrid control loop system

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02116898U (en) * 1989-03-03 1990-09-19

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62242422A (en) * 1986-04-15 1987-10-23 Sony Corp A/d conversion circuit for video signal
EP0461538A1 (en) * 1990-06-15 1991-12-18 ANT Nachrichtentechnik GmbH Hybrid control loop system

Also Published As

Publication number Publication date
JPS6352496B2 (en) 1988-10-19

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