JPS57109422A - Frequency stabilizing device for pulse modulator - Google Patents

Frequency stabilizing device for pulse modulator

Info

Publication number
JPS57109422A
JPS57109422A JP18580680A JP18580680A JPS57109422A JP S57109422 A JPS57109422 A JP S57109422A JP 18580680 A JP18580680 A JP 18580680A JP 18580680 A JP18580680 A JP 18580680A JP S57109422 A JPS57109422 A JP S57109422A
Authority
JP
Japan
Prior art keywords
signal
pulse
frequency
output
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18580680A
Other languages
Japanese (ja)
Other versions
JPH025050B2 (en
Inventor
Taro Shibagaki
Takeshi Koseki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP18580680A priority Critical patent/JPS57109422A/en
Publication of JPS57109422A publication Critical patent/JPS57109422A/en
Publication of JPH025050B2 publication Critical patent/JPH025050B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump

Landscapes

  • Facsimile Image Signal Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To stabilize a frequency with a high precision for a long time by a simple control. CONSTITUTION:A picture signal is inputted to an adder 3 through a clamp circuit 2, and an error signal is added to the picture signal, and this signal is subjected to pulse frequency modulation by a pulse modulator 1 and is outputted. Meanwhile, the picture signal is led to a synchronizing signal extracting circuit 4, and the synchronizing signal, namely, the time of the reference level signal is detected. The output of the pulse modulator 1 is led to a duty correcting circuit 5 and is converted to a pulse signal of duty ratio 1:1 and is normalized to a pulse signal indicating a frequency f1 of the said modulation signal and is compared with a pulse of a reference frequency fb in frequency by a digital phase comparator 8. In accordance with the comparison result, a discrimination output signal (a) or (b) is generated. The discrimination output signal is applied to a charge pump 10 through a switch circuit 9 whose switching is controlled by the synchronizing signal. A signal obtained by taking out the output of the charge pump 10 through a low pass filter 12 becomes the error signal.
JP18580680A 1980-12-26 1980-12-26 Frequency stabilizing device for pulse modulator Granted JPS57109422A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18580680A JPS57109422A (en) 1980-12-26 1980-12-26 Frequency stabilizing device for pulse modulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18580680A JPS57109422A (en) 1980-12-26 1980-12-26 Frequency stabilizing device for pulse modulator

Publications (2)

Publication Number Publication Date
JPS57109422A true JPS57109422A (en) 1982-07-07
JPH025050B2 JPH025050B2 (en) 1990-01-31

Family

ID=16177210

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18580680A Granted JPS57109422A (en) 1980-12-26 1980-12-26 Frequency stabilizing device for pulse modulator

Country Status (1)

Country Link
JP (1) JPS57109422A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0684696A2 (en) * 1994-05-06 1995-11-29 Philips Patentverwaltung GmbH Frequency modulator with a trimming circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53134641U (en) * 1977-03-30 1978-10-25

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53134641U (en) * 1977-03-30 1978-10-25

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0684696A2 (en) * 1994-05-06 1995-11-29 Philips Patentverwaltung GmbH Frequency modulator with a trimming circuit
EP0684696A3 (en) * 1994-05-06 1996-05-15 Philips Patentverwaltung Frequency modulator with a trimming circuit.

Also Published As

Publication number Publication date
JPH025050B2 (en) 1990-01-31

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