JPS5620355A - Clock signal forming circuit - Google Patents

Clock signal forming circuit

Info

Publication number
JPS5620355A
JPS5620355A JP9623479A JP9623479A JPS5620355A JP S5620355 A JPS5620355 A JP S5620355A JP 9623479 A JP9623479 A JP 9623479A JP 9623479 A JP9623479 A JP 9623479A JP S5620355 A JPS5620355 A JP S5620355A
Authority
JP
Japan
Prior art keywords
output
signal
reproduced
frequency
converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9623479A
Other languages
Japanese (ja)
Other versions
JPS6251015B2 (en
Inventor
Masami Shirakawa
Kazuo Yamagiwa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP9623479A priority Critical patent/JPS5620355A/en
Publication of JPS5620355A publication Critical patent/JPS5620355A/en
Publication of JPS6251015B2 publication Critical patent/JPS6251015B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Television Signal Processing For Recording (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To form a clock signal that synchronizes with a reproduced PCM signal by detecting an error component by comparing a clock signal formed by an AFC circuit to a data synchronizing signal separated from the reproduced signal and further by excluding the error component by frequency conversion. CONSTITUTION:AFC circuit 3 generates frequency Nfh'(1Xdelta) of reproduced synchronizing signal HD from frequency fh'. Here, delta is an error in comparison with the reproduced signal. This output and an output from crystal oscillator 13 are supplied to frequency converter 14, the output of which is applied to phase comparator 21. A reproduced PCM signal from terminal 17 is converted by tuning circuit 16 into a signal of a continuous frequency, which is applied to converter 18, whose output is applied to comparator 21 by way of BPF20 to make a phase comparison to the output of converter 14, detecting an error component. Additionally, BPF20 is applied with the output of VCO19 controlled by the output of comparator 21 and the output of VCO19 and that of BPF15 are supplied to converter 23 for frequency conversion, thereby outputting them with the error component canceled.
JP9623479A 1979-07-28 1979-07-28 Clock signal forming circuit Granted JPS5620355A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9623479A JPS5620355A (en) 1979-07-28 1979-07-28 Clock signal forming circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9623479A JPS5620355A (en) 1979-07-28 1979-07-28 Clock signal forming circuit

Publications (2)

Publication Number Publication Date
JPS5620355A true JPS5620355A (en) 1981-02-25
JPS6251015B2 JPS6251015B2 (en) 1987-10-28

Family

ID=14159530

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9623479A Granted JPS5620355A (en) 1979-07-28 1979-07-28 Clock signal forming circuit

Country Status (1)

Country Link
JP (1) JPS5620355A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58211311A (en) * 1982-05-31 1983-12-08 Akai Electric Co Ltd Data extracting clock generator of pcm reproducer
JPS6148170A (en) * 1984-08-15 1986-03-08 Canon Inc Data reproducing device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02107516U (en) * 1989-02-14 1990-08-27

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58211311A (en) * 1982-05-31 1983-12-08 Akai Electric Co Ltd Data extracting clock generator of pcm reproducer
JPS6148170A (en) * 1984-08-15 1986-03-08 Canon Inc Data reproducing device
JPH0583982B2 (en) * 1984-08-15 1993-11-30 Canon Kk

Also Published As

Publication number Publication date
JPS6251015B2 (en) 1987-10-28

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