JPS56169423A - Phase synchronizing circuit - Google Patents
Phase synchronizing circuitInfo
- Publication number
- JPS56169423A JPS56169423A JP7316180A JP7316180A JPS56169423A JP S56169423 A JPS56169423 A JP S56169423A JP 7316180 A JP7316180 A JP 7316180A JP 7316180 A JP7316180 A JP 7316180A JP S56169423 A JPS56169423 A JP S56169423A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- signal
- fed
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0624—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by synchronisation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0836—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of phase error, e.g. jitter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Color Television Systems (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
PURPOSE:To eliminate the phase jitter of clocks, by adding a fluctuating signal to an output of a voltage controlled oscillator and producing a sample clocks through slicing. CONSTITUTION:An NTSC signal 11 at an input terminal is fed to a synchronizing separation circuit 4 and fed to an A/D converter 2 and digitized for output. A part of this output is fed to a burst pickup circuit 5 and the color burst signal is picked up by the output of the circuit 4. The shift of phase between the color burst signal and the reference is detected at an operation circuit 6 to control a voltage controlled oscillator 8 via a D/A converter 7. Further, a step fluctuation signal in which the level corresponding to the 3rd cycle of the color burst signal is zero and the level before and after it is changed positive or negative with a given step, is produced at a production circuit 41 and it is added by an addition circuit 42 to the output of an oscillator 8, and sampled clocks are formed by slicing it at a given level with a slicer 43. Thus, the phase comparison characteristics are in bang bang control and the phase jitter of clock can be eliminated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7316180A JPS56169423A (en) | 1980-05-31 | 1980-05-31 | Phase synchronizing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7316180A JPS56169423A (en) | 1980-05-31 | 1980-05-31 | Phase synchronizing circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56169423A true JPS56169423A (en) | 1981-12-26 |
Family
ID=13510161
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7316180A Pending JPS56169423A (en) | 1980-05-31 | 1980-05-31 | Phase synchronizing circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56169423A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6118317A (en) * | 1997-03-12 | 2000-09-12 | Nec Corporation | Clock synchronizing system and synchronizing method |
-
1980
- 1980-05-31 JP JP7316180A patent/JPS56169423A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6118317A (en) * | 1997-03-12 | 2000-09-12 | Nec Corporation | Clock synchronizing system and synchronizing method |
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