JPS6421918A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6421918A JPS6421918A JP17846887A JP17846887A JPS6421918A JP S6421918 A JPS6421918 A JP S6421918A JP 17846887 A JP17846887 A JP 17846887A JP 17846887 A JP17846887 A JP 17846887A JP S6421918 A JPS6421918 A JP S6421918A
- Authority
- JP
- Japan
- Prior art keywords
- film
- region
- bsg
- type
- type impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Bipolar Transistors (AREA)
Abstract
PURPOSE:To shorten the manufacturing process, by depositing a BSG film on a semiconductor substrate, covering said film with a film, which imparts tensile stress selectively, performing thermal diffusion with the BSG as a diffusing source, forming a high resistance p-type impurity region at a part, where said film is not formed, and forming a low resistance p-type impurity region at a part covered with the film at the same time. CONSTITUTION:A boron silicate glass (BSG) film 5 is deposited on semiconductor substrates 2 and 3. The BSG film 5 is covered with a film 10, which imparts tensile stress selectively. Then, thermal diffusion is performed with said BSC as a diffusion source. A high resistance p-type impurity regions 12 is formed at a part, where said film 10 is not formed. A low resistance p-type impurity region 11 is formed on a part, which is covered with the film 10. For example, windows are provided in a base forming region and a resistance-element forming region in an SiO2 film 4 at the surfaces of the n-type collector region 2 and the n-type substrate region 3. The BSG film 5 is deposited on the entire surface including the windows. The Si3N4 film 10 is deposited on the film 5. The film is made to remain only at the base forming region. Then, heat treatment is performed at 1,100 deg.C for 10 seconds. Thus, the p<+> type base region 10 and the p-type resistance element region 12 are formed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17846887A JPS6421918A (en) | 1987-07-16 | 1987-07-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17846887A JPS6421918A (en) | 1987-07-16 | 1987-07-16 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6421918A true JPS6421918A (en) | 1989-01-25 |
Family
ID=16049037
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17846887A Pending JPS6421918A (en) | 1987-07-16 | 1987-07-16 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6421918A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56122126A (en) * | 1980-02-29 | 1981-09-25 | Nippon Denso Co Ltd | Manufacture of semiconductor device |
-
1987
- 1987-07-16 JP JP17846887A patent/JPS6421918A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56122126A (en) * | 1980-02-29 | 1981-09-25 | Nippon Denso Co Ltd | Manufacture of semiconductor device |
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