JPS56110226A - Forming method of impurity doped region in semiconductor substrate - Google Patents

Forming method of impurity doped region in semiconductor substrate

Info

Publication number
JPS56110226A
JPS56110226A JP1217480A JP1217480A JPS56110226A JP S56110226 A JPS56110226 A JP S56110226A JP 1217480 A JP1217480 A JP 1217480A JP 1217480 A JP1217480 A JP 1217480A JP S56110226 A JPS56110226 A JP S56110226A
Authority
JP
Japan
Prior art keywords
doped region
impurity
semiconductor substrate
impurity doped
depth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1217480A
Other languages
Japanese (ja)
Other versions
JPS5837979B2 (en
Inventor
Yoshihiko Mizushima
Akitsu Takeda
Masashi Yamaguchi
Kiyoshi Kudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP55012174A priority Critical patent/JPS5837979B2/en
Publication of JPS56110226A publication Critical patent/JPS56110226A/en
Publication of JPS5837979B2 publication Critical patent/JPS5837979B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To increase the depth of an impurity doped region and improve controllability by irradiating a light element charged particle onto a semiconductor substrate provided with an impurity layer. CONSTITUTION:An impurity layer 3 consisting of an impurity (e.g. Sb) is formed in a desired pattern on the surface of an Si semiconductor substrate. Next, a protection layer 4 composed of polysilicon, amorphous silicon or oxidized silicon is formed. Following this process, a light element charged particle 5 made up of proton, deuteron, helium etc. is irradiated to control acceleration voltage, etc. As a result, an impurity doped region 6 with well controllable depth is formed. Then it is thermally treated at 800 deg.C to form an N type region. Thus it is possible to form an impurity doped region with more depth compared with the heat diffusion method or the ion injection method.
JP55012174A 1980-02-04 1980-02-04 Method for forming impurity doped regions in semiconductor substrates Expired JPS5837979B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55012174A JPS5837979B2 (en) 1980-02-04 1980-02-04 Method for forming impurity doped regions in semiconductor substrates

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55012174A JPS5837979B2 (en) 1980-02-04 1980-02-04 Method for forming impurity doped regions in semiconductor substrates

Publications (2)

Publication Number Publication Date
JPS56110226A true JPS56110226A (en) 1981-09-01
JPS5837979B2 JPS5837979B2 (en) 1983-08-19

Family

ID=11798057

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55012174A Expired JPS5837979B2 (en) 1980-02-04 1980-02-04 Method for forming impurity doped regions in semiconductor substrates

Country Status (1)

Country Link
JP (1) JPS5837979B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0058566A2 (en) * 1981-02-17 1982-08-25 Fujitsu Limited Process for producing a semiconductor device using a diffusion step
US5108935A (en) * 1990-11-16 1992-04-28 Texas Instruments Incorporated Reduction of hot carrier effects in semiconductor devices by controlled scattering via the intentional introduction of impurities

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0058566A2 (en) * 1981-02-17 1982-08-25 Fujitsu Limited Process for producing a semiconductor device using a diffusion step
US5108935A (en) * 1990-11-16 1992-04-28 Texas Instruments Incorporated Reduction of hot carrier effects in semiconductor devices by controlled scattering via the intentional introduction of impurities

Also Published As

Publication number Publication date
JPS5837979B2 (en) 1983-08-19

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