JPS5565471A - Input protective device for mos integrated circuit - Google Patents

Input protective device for mos integrated circuit

Info

Publication number
JPS5565471A
JPS5565471A JP13952778A JP13952778A JPS5565471A JP S5565471 A JPS5565471 A JP S5565471A JP 13952778 A JP13952778 A JP 13952778A JP 13952778 A JP13952778 A JP 13952778A JP S5565471 A JPS5565471 A JP S5565471A
Authority
JP
Japan
Prior art keywords
layer
wiring
small
wiring layers
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13952778A
Other languages
Japanese (ja)
Inventor
Yasoji Suzuki
Minoru Takada
Yasushi Sato
Hiroshi Osanai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13952778A priority Critical patent/JPS5565471A/en
Publication of JPS5565471A publication Critical patent/JPS5565471A/en
Pending legal-status Critical Current

Links

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE: To obtain chips as small in size as possible by constituting a wiring connection of n-layer small enough to allow other wiring layers to pass on p-layer from forming a protective diode for which n-layer is formed on p-layer.
CONSTITUTION: An n+-layer 32 is diffused on a p-layer 31, a small connection hole 34 is perforated in an SiO2 film 33 covering the surface, and a wiring layer 35 in ohmic contact is arranged. Then, wiring layers 36, 37 having nothing to do with the protective input device are provided on both sides of the wiring layer 35 on the SiO2 film 33. Thus the hole 34 is arranged small enough as compared with the layer 32, therefore the n+-layer 32 is placed upon the wiring layers 36, 37, and the interval between the wiring layers 36, 37 can be shortened. Thus a space can be utilized effectively at the protective diode section, and hence chips of IC using the input protective diode many particularly are obtainable as small in size as possible.
COPYRIGHT: (C)1980,JPO&Japio
JP13952778A 1978-11-13 1978-11-13 Input protective device for mos integrated circuit Pending JPS5565471A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13952778A JPS5565471A (en) 1978-11-13 1978-11-13 Input protective device for mos integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13952778A JPS5565471A (en) 1978-11-13 1978-11-13 Input protective device for mos integrated circuit

Publications (1)

Publication Number Publication Date
JPS5565471A true JPS5565471A (en) 1980-05-16

Family

ID=15247352

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13952778A Pending JPS5565471A (en) 1978-11-13 1978-11-13 Input protective device for mos integrated circuit

Country Status (1)

Country Link
JP (1) JPS5565471A (en)

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