JPH088386A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH088386A
JPH088386A JP6141422A JP14142294A JPH088386A JP H088386 A JPH088386 A JP H088386A JP 6141422 A JP6141422 A JP 6141422A JP 14142294 A JP14142294 A JP 14142294A JP H088386 A JPH088386 A JP H088386A
Authority
JP
Japan
Prior art keywords
loc
semiconductor device
tape
resin
inner lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6141422A
Other languages
English (en)
Inventor
Masahiko Ichise
理彦 市瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP6141422A priority Critical patent/JPH088386A/ja
Publication of JPH088386A publication Critical patent/JPH088386A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/061—Disposition
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    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】 【目的】ＩＲリフローや温度サイクルによって発生した
界面の剥離の波及が原因で発生したクラックによるＡｕ
ワイヤーの断線を抑える。 【構成】内部リード１の先端部をＬＯＣテープ２より突
出させる。これによりＩＲリフローや温度サイクルによ
る剥離の波及を抑え、クラックの発生を防ぎ、クラック
によるＡｕワイヤーの断線を防止する。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は、半導体装置に関し、特
にリード・オン・チップ構造（ＬＯＣ構造）の半導体装
置に関する。
【０００２】
【従来の技術】図４は従来のＬＯＣ構造の半導体装置の
樹脂封入前の平面図であり、図５は樹脂封入後の断面図
である。従来のＬＯＣ構造の半導体装置は、図のように
内部リード１の下面に絶縁性テープ（ＬＯＣテープ）２
により、半導体チップ３を固着して搭載している。内部
リード１の先端はＬＯＣテープ２の内側に位置してい
る。こうすることにより内部リード１の先端部分全体を
ＬＯＣテープ２に固着している。これは内部リード１が
十分に固着されていない場合に半導体チップ３と内部リ
ード１とをＡｕワイヤー４で電気的接続を行うボンディ
ング工程の際に内部リード１が動いてしまい、Ａｕワイ
ヤー４と内部リード１の接合が不十分になってしまう不
良を防ぐためである。さらに内部リード１とＬＯＣテー
プ２の接着面積をより大きくし、内部リード１とＬＯＣ
テープ２との固着をより堅固なものにし、樹脂封止工程
の際に内部リード１とＬＯＣテープ２が剥れてしまい内
部リード１から半導体チップ３が脱落してしまう不良を
防ぐためである。
【０００３】
【発明が解決しようとする課題】従来のＬＯＣ構造の半
導体装置において、封入樹脂とＬＯＣテープの界面の密
着力は他の界面よりも弱い。従って、基板に実装する際
のＩＲリフローや温度サイクルによるストレスによっ
て、図３（ａ）のようにまず封入樹脂５とＬＯＣテープ
２の界面に第１の剥離６が発生する。
【０００４】内部リード１の先端部分の上面はＡｕワイ
ヤー４との接合のためにＡｇメッキが施されているが、
このＡｇメッキは内部リード１の先端部分の上面以外の
内部リード裏面９を除く部分にも付着するため、内部リ
ード１の先端部分の側面にはＡｇメッキが付着してい
る。このＡｇメッキと封入樹脂の界面の密着力は、封入
樹脂とＬＯＣテープの界面に次いで弱い。このため、ス
トレスが更に加わると前述した封入樹脂とＬＯＣテープ
の界面の第１の剥離６が図３（ｂ）の様に内部リード１
の側面と封入樹脂５の界面に波及し、第２の剥離７を発
生させる。そして、ストレスが加わり続けると図３
（ｃ）の様に内部リード１の先端の角部よりクラック８
が発生し、Ａｕワイヤー４を切断してしまう。
【０００５】
【課題を解決するための手段】本発明は、両面に接着面
を有するＬＯＣテープにより、内部リードフレーム下面
に半導体チップを固着して搭載するＬＯＣ構造の半導体
装置において、内部リードの先端をＬＯＣテープより突
出させたことを特徴とする。さらに、内部リードの先端
を樹脂でコーティングすると封入樹脂との密着が良くな
る。
【０００６】
【実施例】次に本発明について図面を参照して説明す
る。図１（ａ）は本発明の第１の実施例の樹脂封入前の
平面図であり、図１（ｂ）は樹脂封入後の要部断面図で
ある。本実施例においては、図の様に内部リード１の先
端がＬＯＣテープ２より突出している。このようにする
ことにより、基板に実装する際のＩＲリフローや温度サ
イクルでのストレスのために封入樹脂５とＬＯＣテープ
２との界面に第１の剥離６が発生しても、封入樹脂５と
の密着力が比較的強いリードフレーム素材が露出してい
るＡｇメッキされていない内部リード裏面９と封入樹脂
５の界面が、封入樹脂５とＬＯＣテープ２との界面で発
生した第１の剥離６が波及することを防ぐ。
【０００７】また、本実施例では従来と異なり、第１の
剥離６が内部リードの下面で発生するため、クラックの
起点となる内部リード１の上側の角部までの剥離の径路
が、内部リードの側面と樹脂の界面を通るので長くな
る。したがって、クラックの起点となる内部リード１の
上側の角部まで剥離が到達することもない。
【０００８】内部リードの先端をＬＯＣテープより突出
させる方法としては、内部リードの先端を長くする方法
とＬＯＣテープを小さくする方法がある。前者の場合は
特に問題はないが、後者の場合はボンディング工程や封
入工程への影響が懸念される。封入樹脂とＬＯＣテープ
との界面で発生した剥離の波及を防ぐためには、内部リ
ード先端がＬＯＣテープより０．２ｍｍ以上突出してい
ればよい。０．２ｍｍ程度のＬＯＣテープのサイズの変
更はボンディング工程、封入工程の歩留りに影響を与え
ることはない。実際にＬＯＣ構造の３２ピン４００ミル
ＳＯＪパッケージに使用しているリードフレームにおい
て、内部リード先端をＬＯＣテープより０．２ｍｍ突出
させるためにＬＯＣテープを縮小しても、ボンディング
工程及び封入工程での歩留りの低下は無かった。
【０００９】図２（ａ）は本発明の第２の実施例の樹脂
封入前の平面図であり、図２（ｂ）は要部断面図であ
る。本実施例では、内部リード１の先端を封入樹脂５と
の密着力が強い樹脂（例えばシリコーン樹脂）１０によ
るコーティングを施している。これにより、内部リード
の裏面９だけでなく、Ａｇメッキが付着している内部リ
ード１の側面と封入樹脂５との密着力も向上するため、
封入樹脂５とＬＯＣテープ２との界面で発生した第１の
剥離６がより波及し難くなっている。
【００１０】
【発明の効果】本発明はＬＯＣ構造用リードフレームの
内部リードの先端がＬＯＣテープより突出しているの
で、基板に実装する際のＩＲリフローや温度サイクルで
のストレスで発生した封入樹脂とＬＯＣテープとの界面
の剥離が波及することを防いでいる。従って、内部リー
ド角部からクラックの発生することが少なくなるため、
クラックによりＡｕワイヤーの切断される不良の発生は
少なくなる。
【００１１】従来のリードフレームのように内部リード
先端がＬＯＣテープの内側に位置する場合、ＳＯＪパッ
ケージにおいて、温度サイクル５００〜６００サイクル
時点で５０％程度の発生率でＡｕワイヤーの断線による
オープン不良が発生していたが、本発明のリードフレー
ムの場合には温度サイクル１０００サイクル時点でもＡ
ｕワイヤーの断線によるオープン不良は発生しない。ま
た、剥離部分が少なくなるため、パッケージが吸湿して
もリークなどの不良の発生は抑えられる。よって、本発
明の半導体装置は総合的な信頼性の向上につながる。
【図面の簡単な説明】
【図１】本発明の第１の実施例を示す図で、（ａ）は樹
脂封入前の平面図、（ｂ）は樹脂封入後の要部断面図で
ある。
【図２】本発明の第２の実施例を示す図で、（ａ）は樹
脂封入前の平面図、（ｂ）は樹脂封入後の要部断面図で
ある。
【図３】（ａ）〜（ｃ）は、従来のＬＯＣ構造の半導体
装置においてクラックが生じる状態を示す断面図であ
る。
【図４】従来のＬＯＣ構造の半導体装置の樹脂封入前の
平面図である。
【図５】従来のＬＯＣ構造の半導体装置の樹脂封入後の
断面図である。
【符号の説明】
１ 内部リード ２ ＬＯＣテープ ３ 半導体チップ ４ Ａｕワイヤー ５ 封入樹脂 ６ 第１の剥離 ７ 第２の剥離 ８ クラック ９ 内部リード裏面 １０ 樹脂

Claims (2)

    【特許請求の範囲】
  1. 【請求項１】 接着面を有する絶縁性テープを介して内
    部リードフレーム下面に半導体チップを固着して搭載す
    るリード・オン・チップ構造の半導体装置において、内
    部リードの先端を絶縁性テープより突出させることを特
    徴とする半導体装置。
  2. 【請求項２】 前記内部リードの先端部を樹脂でコーテ
    ィングしたことを特徴とする請求項１記載の半導体装
    置。
JP6141422A 1994-06-23 1994-06-23 半導体装置 Pending JPH088386A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6141422A JPH088386A (ja) 1994-06-23 1994-06-23 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6141422A JPH088386A (ja) 1994-06-23 1994-06-23 半導体装置

Publications (1)

Publication Number Publication Date
JPH088386A true JPH088386A (ja) 1996-01-12

Family

ID=15291633

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6141422A Pending JPH088386A (ja) 1994-06-23 1994-06-23 半導体装置

Country Status (1)

Country Link
JP (1) JPH088386A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7139056B2 (en) 1998-11-27 2006-11-21 Sanyo Electric Co., Ltd. Liquid crystal display device having particular orientation control window

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04100265A (ja) * 1990-08-20 1992-04-02 Hitachi Ltd 樹脂封止型半導体装置
JPH0582585A (ja) * 1991-09-19 1993-04-02 Mitsubishi Electric Corp 半導体装置
JPH06140452A (ja) * 1992-10-26 1994-05-20 Hitachi Ltd 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04100265A (ja) * 1990-08-20 1992-04-02 Hitachi Ltd 樹脂封止型半導体装置
JPH0582585A (ja) * 1991-09-19 1993-04-02 Mitsubishi Electric Corp 半導体装置
JPH06140452A (ja) * 1992-10-26 1994-05-20 Hitachi Ltd 半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7139056B2 (en) 1998-11-27 2006-11-21 Sanyo Electric Co., Ltd. Liquid crystal display device having particular orientation control window
US7251003B2 (en) 1998-11-27 2007-07-31 Sanyo Electric Co., Ltd. Liquid crystal display device having particular orientation control window

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