JPH08264765A - Power chip carrier and power semiconductor device using the same - Google Patents
Power chip carrier and power semiconductor device using the sameInfo
- Publication number
- JPH08264765A JPH08264765A JP7067333A JP6733395A JPH08264765A JP H08264765 A JPH08264765 A JP H08264765A JP 7067333 A JP7067333 A JP 7067333A JP 6733395 A JP6733395 A JP 6733395A JP H08264765 A JPH08264765 A JP H08264765A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- cathode
- anode
- side internal
- internal electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Landscapes
- Die Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＭＯＳ制御型パワー半
導体、特に、トランジスタ（ＩＧＢＴ等）、あるいはト
ランジスタとサイリスタとの複合型半導体（ＩＧＣＴ
等）及びダイオードを搭載した、単位パワーチップキャ
リア及びこれらを同一金属基板間に挟み加圧し並列動作
を可能にした大容量半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS-controlled power semiconductor, and more particularly to a transistor (IGBT or the like) or a composite semiconductor (IGCT) of a transistor and a thyristor.
Etc.) and a diode, and a large-capacity semiconductor device which enables parallel operation by sandwiching and pressing these unit power chip carriers between the same metal substrates.
【０００２】[0002]
【従来の技術】インバータ装置をはじめとする電力用変
換器の高性能化，低騒音化に対応するため、高速、低損
失のスイッチング素子の開発が強く望まれている。この
半導体素子として、ＩＧＢＴ（Insulated Gate Bipolar
Transistor ）及びＩＧＣＴ（Insulated Gate Control
led Thyristor ）がある。ＩＧＢＴは、例えば電子技術
１９９１年８月号ｐｐ．１７ー７１に示されているよう
に電圧駆動であり、高速動作が可能である。更に、電圧
制御であることから、従来の電流制御素子であるＧＴＯ
サイリスタに比べ、オン電圧を低く出来るため、素子の
低損失が可能である。また、ＩＧＣＴはＩＧＢＴに比
べ、更にオン電圧の低減，大電流化が可能である。しか
し、ＩＧＢＴあるいはＩＧＣＴ等のＭＯＳ制御型半導体
はチップの大面積化がプロセス歩留りの点から難しいた
め、大電力のスイッチングを行う際、チップの並列接続
が不可欠であり、このためにはモジュール化が不可欠で
ある。2. Description of the Related Art In order to cope with higher performance and lower noise of power converters such as inverter devices, development of high-speed, low-loss switching elements is strongly desired. As this semiconductor element, an IGBT (Insulated Gate Bipolar)
Transistor) and IGCT (Insulated Gate Control)
led Thyristor). The IGBT is disclosed in, for example, the electronic technology August 1991 pp. As shown in 17-71, it is voltage driven, and high speed operation is possible. Furthermore, since it is voltage control, the conventional GTO that is a current control element is used.
Compared with a thyristor, the ON voltage can be lowered, so that the loss of the element can be reduced. Further, the IGCT can further reduce the on-voltage and increase the current as compared with the IGBT. However, since it is difficult to increase the chip area of a MOS control type semiconductor such as IGBT or IGCT from the viewpoint of process yield, it is indispensable to connect the chips in parallel when high power switching is performed. It is essential.
【０００３】図１（ａ)，(ｂ）は従来の片面冷却型ＩＧ
ＢＴモジュールの平面及び断面構造を示した図である。
図において、１０１はＩＧＢＴチップ、１０２はコレク
タ（アノード）側支持電極板、１０３はボンデイングワ
イヤ、１０４はＡｌＮ基板、１０５は半田層、１０６は
エミッタ電極端子、１０７はＡｌ電極、１０８はゲート
電極端子、１０９はコレクタ(アノード)電極端子及び１
１０はダイオードチップを示している。ＩＧＢＴチップ
１０１内部で生じた熱は銅回路板であるコレクタ側電極
端子１０９，ＡｌＮ基板１０４及びＭｏ，銅等の金属基
板であるコレクタ側電極支持板１０２を通して外部へ放
散する。このような片面冷却型IGBTモジュールの例とし
て、例えば三菱電機技報vol ６７，Ｎo.９，１９９３，
ＰＰ．９０−９３に示されている。1A and 1B show a conventional single-sided cooling IG.
It is the figure which showed the plane and sectional structure of a BT module.
In the figure, 101 is an IGBT chip, 102 is a collector (anode) side supporting electrode plate, 103 is a bonding wire, 104 is an AlN substrate, 105 is a solder layer, 106 is an emitter electrode terminal, 107 is an Al electrode, and 108 is a gate electrode terminal. , 109 are collector (anode) electrode terminals and 1
Reference numeral 10 indicates a diode chip. The heat generated inside the IGBT chip 101 is dissipated to the outside through the collector side electrode terminal 109 which is a copper circuit plate, the AlN substrate 104 and the collector side electrode supporting plate 102 which is a metal substrate of Mo, copper or the like. As an example of such a single-sided cooling type IGBT module, for example, Mitsubishi Electric Technical Report vol 67, No. 9, 1993,
PP. 90-93.
【０００４】一方、平成６年電気学会全国大会資料（Ｎ
o.５０７）に開示されている加圧接触型パッケージ構造
のＩＧＢＴを図２に示す。この構造はＩＧＢＴチップ２
０１のコレクタあるいはアノード側を下部のコレクタ側
電極板２０３に接合層２０２により接合し、エミッタ上
に設けた加圧用電極２０５を凸部を有するエミッタ電極
板２０４で加圧圧接した点に特徴がある。また、ゲート
電極２０６はワイヤ２０７によりゲート端子２０８に接
続されている。両面から冷却が可能なため、熱抵抗が低
く、信頼性も高い。On the other hand, the 1994 National Conference of the Institute of Electrical Engineers of Japan (N
FIG. 2 shows the IGBT of the pressure contact type package structure disclosed in O.507). This structure is IGBT chip 2
The characteristic is that the collector or anode side of No. 01 is bonded to the lower collector side electrode plate 203 by the bonding layer 202, and the pressing electrode 205 provided on the emitter is pressed and pressed by the emitter electrode plate 204 having the convex portion. . The gate electrode 206 is connected to the gate terminal 208 by the wire 207. Since it can be cooled from both sides, it has low thermal resistance and high reliability.
【０００５】[0005]
【発明が解決しようとする課題】従来の片面冷却型構造
では、冷却効率が低いため基板上に高密度にＩＧＢＴを
実装するとチップ温度が上昇して、半田接合部及びワイ
ヤボンデイング部が劣化し易い。また、ゲート電極（１
０８のチップ側電極に対応）直下には脆く、薄いゲート
酸化膜が存在するため、ワイヤボンデイング時のチップ
ダメージが発生し易く、接合部の信頼性に問題が生じ
る。更に、上記構造の場合、シリーズ化に対応するため
には、その都度モジュール構造の設計を行う必要が生じ
る。In the conventional one-sided cooling type structure, since the cooling efficiency is low, the chip temperature rises when the IGBTs are mounted on the substrate at a high density, and the solder joint portion and the wire bonding portion are easily deteriorated. . In addition, the gate electrode (1
(Corresponding to the chip side electrode of 08) Since there is a fragile and thin gate oxide film immediately below, chip damage is likely to occur during wire bonding, which causes a problem in reliability of the joint portion. Further, in the case of the above structure, it is necessary to design the module structure each time in order to correspond to the series.
【０００６】また、加圧接触型パッケージ構造では、エ
ミッタ側は圧接構造となっているため、加圧した状態で
通電すると、チップ温度は上昇する。その結果、加圧電
極はＩＧＢＴチップよりも伸びるため偏荷重になり易
く、接触抵抗の変動が起こり易い。また、ごみ，ずれ等
のハンドリングにも問題を生じ易い。更に、加圧用電極
をチップ上に設けているため、ＭＯＳ制御部のチップ面
積に閉める割合が小さくなり、面積当りの電流容量が小
さくなる。Further, in the pressure contact type package structure, since the emitter side has a pressure contact structure, the chip temperature rises when current is applied in a pressurized state. As a result, the pressurizing electrode extends more than the IGBT chip, so that an eccentric load is likely to occur and the contact resistance is likely to change. In addition, handling of dust, misalignment, etc. is likely to cause problems. Further, since the pressurizing electrode is provided on the chip, the ratio of closing the chip area of the MOS control unit becomes small, and the current capacity per area becomes small.
【０００７】本発明の目的は、信頼性，ハンドリング
性，製造性及び冷却効率に優れたパワーチップキャリア
を提供することにある。An object of the present invention is to provide a power chip carrier excellent in reliability, handleability, manufacturability and cooling efficiency.
【０００８】また、本発明の他の目的は上記パワーチッ
プキャリアを基本にして大容量化，シリーズ化が容易な
パワー半導体装置を提供することにある。Another object of the present invention is to provide a power semiconductor device which can be easily increased in capacity and series based on the power chip carrier.
【０００９】[0009]
【課題を解決するための手段】本発明のチップキャリア
によれば、ＭＯＳ制御型パワー半導体素子のカソード電
極及びアノード電極とがカソード側内部電極及びアノー
ド側内部電極に金属学的に接合されている。According to the chip carrier of the present invention, the cathode electrode and the anode electrode of the MOS control type power semiconductor element are metallurgically bonded to the cathode side inner electrode and the anode side inner electrode. .
【００１０】実施態様によれば、カソード電極及びアノ
ード電極はＡｌを第１層にし、接合され最上層がＡｇ又
はＡｕで構成され、中間層はＣｒ，Ｔｉ又はＮｉから構
成される接着層を有する。また、カソード側内部電極及
びアノード側内部電極はＮｉを第１層にし、接合される
最上層がＡｇ又はＡｕで構成された接着層を有する。更
に、カソード電極とカソード側内部電極との接合、及
び、上記アノード電極とアノード側内部電極との接合は
ＡｇとＡｇ、又は、ＡｇとＡｕとの相互拡散により金属
学的接合されていることが好ましい。このＡｇとＡｇ、
又は、ＡｇとＡｕとの相互拡散による金属学的接合は２
５０℃以下で行われることが望ましい。According to an embodiment, the cathode electrode and the anode electrode have Al as the first layer and are bonded and the uppermost layer is composed of Ag or Au, and the intermediate layer has an adhesive layer composed of Cr, Ti or Ni. . The cathode-side internal electrode and the anode-side internal electrode have Ni as the first layer, and the uppermost layer to be bonded has an adhesive layer composed of Ag or Au. Further, the junction between the cathode electrode and the cathode-side internal electrode and the junction between the anode electrode and the anode-side internal electrode may be metallurgically joined by mutual diffusion of Ag and Ag or Ag and Au. preferable. This Ag and Ag,
Or, the metallurgical bonding by mutual diffusion of Ag and Au is 2
It is desirable to be performed at 50 ° C. or lower.
【００１１】本発明のパワー半導体装置によれば、上述
のパワーチツプキャリアを複数用い、これらのパワーチ
ツプキャリアのそれぞれのカソード側内部電極及びアノ
ード側内部電極に金属学的に接合した複数の絶縁基板
と、カソード側内部電極に接合した絶縁基板と、及び、
アノード側内部電極に接合した絶縁基板とに加圧接続さ
れ、複数パワーチツプキャリアを並列的に固定する第１
及び第２の外部電極とを有する。According to the power semiconductor device of the present invention, a plurality of the above-mentioned power chip carriers are used, and a plurality of insulating substrates are metallurgically bonded to the cathode side internal electrode and the anode side internal electrode of each of these power chip carriers. And an insulating substrate bonded to the cathode-side internal electrode, and
First pressure-connected to an insulating substrate bonded to an anode-side internal electrode to fix a plurality of power chip carriers in parallel
And a second external electrode.
【００１２】カソード側内部電極に接合した絶縁基板と
第１の外部電極間に海面金属層、又は、超弾性合金層を
有することが望ましいを特徴とする半導体装置。A semiconductor device characterized in that it is desirable to have a sea surface metal layer or a super elastic alloy layer between the insulating substrate bonded to the cathode side internal electrode and the first external electrode.
【００１３】[0013]
【作用】本発明構造では半導体素子基板のアノード，カ
ソード両主面上の各電極と内部電極とが金属学的に接合
されているため、界面に空気層が介在する圧接構造に比
べ、両面からの十分な冷却が可能であリ、熱抵抗が低
い。さらに、圧接構造特有の偏荷重現象も起こりにく
く、ごみ，ずれ等のハンドリング性を悪化させることも
ない。例えば、本発明を適用したＩＧＢＴモジュールの
場合、ＶＣＥ（飽和電圧）の加圧力依存性は極めて小さ
くなる。すなわち、加圧力を小さくできる。以上のこと
から本発明構造は小型化，高信頼化に有利である。更
に、樹脂封止してあるため用途によっては絶縁板を接続
しない状態、すなわち単位モジュールのままでも使用で
きる。In the structure of the present invention, since the electrodes on the main surfaces of both the anode and cathode of the semiconductor element substrate are metallurgically bonded to the internal electrodes, compared to the pressure contact structure in which an air layer is interposed at the interface, Can be sufficiently cooled and has low thermal resistance. Further, the unbalanced load phenomenon peculiar to the pressure contact structure hardly occurs, and the handling property such as dust and misalignment is not deteriorated. For example, in the case of the IGBT module to which the present invention is applied, the pressure dependence of VCE (saturation voltage) becomes extremely small. That is, the pressing force can be reduced. From the above, the structure of the present invention is advantageous for miniaturization and high reliability. Further, since it is resin-sealed, it can be used in a state in which an insulating plate is not connected, that is, a unit module as it is depending on the application.
【００１４】本発明の金属学的接合は２５０度以下の温
度での接合がよいが、特に１２０〜１５０度付近の温度
で接続すれば、内部電極はＷ，ＭｏあるいはＣｕ−Ａｌ
Ｎ，Ｃｕ−ＳｉＣ，Ｃｕ−Ｗ，Ｃｕ−Ｍｏ等の低熱膨張
係数の材料ばかりなくＣｕ，Ａｌ等の熱膨張係数の比較
的大きい材料でも可能になる。低温であるため、熱膨張
係数のミスマッチが大きくても、接合部に発生する熱応
力を小さくできるからである。The metallurgical bonding of the present invention is preferably carried out at a temperature of 250 ° C. or less, but if the connection is made at a temperature of around 120 to 150 ° C., the internal electrodes will be W, Mo or Cu--Al.
Not only materials having a low coefficient of thermal expansion such as N, Cu-SiC, Cu-W, and Cu-Mo but also materials having a relatively large coefficient of thermal expansion such as Cu and Al can be used. Since the temperature is low, the thermal stress generated in the joint can be reduced even if the mismatch of the thermal expansion coefficient is large.
【００１５】本発明のパワー半導体装置では上述のパワ
ーチップキャリアをモジュール単位とし並列接続によ
り、従来モジュールに比べ、かなり小型化して達成でき
る。In the power semiconductor device of the present invention, the above-described power chip carrier is used as a module unit and connected in parallel.
【００１６】すなわち、ＭＯＳ制御型半導体ではチップ
歩留りの点から、チップを３cm角以上にすることは難し
いため、チップ容量としてはたかだか、百アンペア程度
であり、これを数千アンペアまで大容量化するためには
多数のチップを同時に動作させる必要がある。従って、
従来の片側冷却方式のモジュールでは冷却効率を考慮す
るとかなり寸法的に大きなものになる。また容量に応じ
てチップの位置，端子の位置等の設計，作製したモジュ
ールの信頼性評価等が必要となり、シリーズ化が困難で
ある。That is, in the case of a MOS control type semiconductor, since it is difficult to make the chip 3 cm square or more from the viewpoint of chip yield, the chip capacity is at most about 100 amperes, which is increased to several thousand amperes. Therefore, it is necessary to operate many chips at the same time. Therefore,
The conventional one-sided cooling type module has a considerably large size in consideration of cooling efficiency. Further, it is necessary to design the chip position, the terminal position, etc. according to the capacity and to evaluate the reliability of the manufactured module, which makes it difficult to make a series.
【００１７】本発明のパワー半導体装置によれば、上述
した小型で、冷却効率が高い高信頼性を有するパワーチ
ップキャリアを用いており、しかも、それぞれのパワー
チップキャリアは第１及び第２の外部電極により並列接
続されている。従って、シリーズ化が容易にでき、小型
でしかも信頼性に富む大容量のパワー半導体装置が実現
できる。According to the power semiconductor device of the present invention, the above-described small-sized power chip carrier with high cooling efficiency and high reliability is used, and each power chip carrier has the first and second external parts. The electrodes are connected in parallel. Therefore, a large-capacity power semiconductor device that can be easily made into a series, is small, and is highly reliable can be realized.
【００１８】また、カソード側内部電極に接合した絶縁
基板と第１の外部電極間に海面金属層、又は、超弾性合
金層を有することにより、それぞれのパワーチップキャ
リアには均一に加圧されるため、信頼性が更に増す。Further, since the sea surface metal layer or the super elastic alloy layer is provided between the insulating substrate joined to the cathode side internal electrode and the first external electrode, each power chip carrier is uniformly pressed. Therefore, reliability is further increased.
【００１９】[0019]
【実施例】以下、本発明を実施例により具体的に説明す
る。EXAMPLES The present invention will be specifically described below with reference to examples.
【００２０】図３（ａ)，(ｂ）は本発明のパワーチップ
キャリアの断面構造の一例を示す。また、図４はパワー
チップキャリアに使用するＩＧＢＴの断面図を示す。図
３において、３０１はＳｉ基体、３０２はゲート、３０
３はカソード電極、３０４はコレクタ（アノード）側電
極、３０５はカソード側接着層、３０６はコレクタ（ア
ノード）側接着層、３０７はカソード側内部電極、３０
８はコレクタ（アノード）側内部電極、３０９はゲート
電極、３１０はボンデイングワイヤ、３１１はゲート端
子、３１２は絶縁支持基板、３１３は樹脂、３１４はカ
ソード側絶縁基板との接着層、３１５はコレクタ（アノ
ード）側絶縁板との接着層、３１６，３１７は絶縁基板
を示す。図３（ａ）の特徴はＳｉ基体３０１のカソード
電極３０３及びコレクタ（アノード）電極３０４と内部
電極３０７，３０８とが強固に金属学的に接着され、Ｉ
ＧＢＴの周囲に配置されたゲート電極３０９がワイヤに
よりゲート端子３１１に接続され、樹脂３１３で封止さ
れた構造にある。またゲート電極３０９は図４のエミッ
タ電極４０５の間に位置するゲート電極３０２に接続し
ている。なお、図４の４０６はカソード電極３０３とゲ
ート３０２とを絶縁する絶縁膜である。3 (a) and 3 (b) show an example of a sectional structure of the power chip carrier of the present invention. Further, FIG. 4 shows a sectional view of an IGBT used for a power chip carrier. In FIG. 3, 301 is a Si substrate, 302 is a gate, 30
3 is a cathode electrode, 304 is a collector (anode) side electrode, 305 is a cathode side adhesive layer, 306 is a collector (anode) side adhesive layer, 307 is a cathode side internal electrode, 30
8 is a collector (anode) side internal electrode, 309 is a gate electrode, 310 is a bonding wire, 311 is a gate terminal, 312 is an insulating support substrate, 313 is a resin, 314 is an adhesive layer with the cathode side insulating substrate, and 315 is a collector ( Adhesive layers to the (anode) side insulating plate, 316 and 317 are insulating substrates. The feature of FIG. 3A is that the cathode electrode 303 and the collector (anode) electrode 304 of the Si substrate 301 and the internal electrodes 307 and 308 are strongly metallurgically adhered to each other.
The gate electrode 309 arranged around the GBT is connected to the gate terminal 311 by a wire and is sealed with the resin 313. The gate electrode 309 is connected to the gate electrode 302 located between the emitter electrodes 405 in FIG. Note that 406 in FIG. 4 is an insulating film that insulates the cathode electrode 303 from the gate 302.
【００２１】この構造において、ＩＧＢＴの容量はそれ
ぞれＳｉ基体の性能，大きさにもよるが、５００〜３０
００Ｖ，５０〜３００Ａ程度であり、この容量の範囲で
あれば、この状態で使用出来る。また、ＩＧＢＴのカソ
ードおよびコレクタ電極が内部電極３０７及び３０８と
接着されているため、両面から熱を逃す（両面冷却）こ
とができ、熱抵抗，信頼性の点で従来技術に比べ極めて
有利である。それでワイヤボンデイング部も劣化しにく
い。In this structure, the capacity of the IGBT depends on the performance and size of the Si substrate, but it is 500 to 30.
00V, about 50 to 300 A, and within this capacity range, it can be used in this state. Further, since the cathode and collector electrodes of the IGBT are bonded to the internal electrodes 307 and 308, heat can be dissipated from both sides (double-sided cooling), which is extremely advantageous in terms of thermal resistance and reliability as compared with the prior art. . Therefore, the wire bonding part is also less likely to deteriorate.
【００２２】カソード電極３０３，コレクタ電極３０４
の電極構造としてはＡｌ／Ｃｒ／Ｎｉ／Ａｇ，Ａｌ／Ｎ
ｉ／Ｔｉ／Ｎｉ／ＡｕあるいはＡｌ／Ｃｒ／Ａｇ，Ａｌ
／Ｎｉ／Ａｕ，Ａｌ／Ｃｒ／Ａｇ等Ａｌを第一層にし、
最上層はＡｇ、あるいはＡｕで、中間に密着性向上のＣ
ｒ，Ｔｉ層、バリアであるＮｉ層からなっていれば良
い。一方、内部電極３０７及び３０８の接着層はＮｉ／
Ａｇからなる。ＡｇとＡｇあるいはＡｕの相互拡散によ
り２５０℃以下の温度での金属接合が完了する。Cathode electrode 303, collector electrode 304
The electrode structure of Al / Cr / Ni / Ag, Al / N
i / Ti / Ni / Au or Al / Cr / Ag, Al
/ Ni / Au, Al / Cr / Ag, etc. as the first layer,
The uppermost layer is Ag or Au, and C, which improves adhesion, is in the middle.
It only has to be composed of an r layer, a Ti layer and a Ni layer which is a barrier. On the other hand, the adhesive layer of the internal electrodes 307 and 308 is Ni /
It consists of Ag. Metal bonding at a temperature of 250 ° C. or lower is completed by the mutual diffusion of Ag and Ag or Au.
【００２３】これに対し、図１に示した片面冷却型で
は、１０５で示す半田接続の場合、ＩＧＢＴチップの裏
面にはＡｌ／Ｃｒ／Ｎｉ／Ａｇ処理をしているが、エミ
ッタ電極板１０６上にはＮｉめっきが施され、Ｐｂ−Ｓ
ｎあるいはＳｎ−Ｓｂ半田で接続される。この場合に
は、Ａｇが半田に拡散し、両側の界面にＮｉとＳｎの化
合物が生成して接着が完了する。ＮｉとＳｎの化合物は
２５０℃以上の温度にならなければ十分に成長しない、
ＡｌＮ基板１０２と基板１０４との半田接続も同様にＮ
ｉとＳｎとの化合物が生成して接合が完了する。Ｎｉと
Ｓｎの化合物の生成は接合温度ばかりでなくＮｉめっき
膜表面の酸化膜（ＮｉＯ，Ｎｉ2Ｏ3）、汚れ及び半田中
のガスにもかなりの影響を受け、界面及び半田中に大き
なボイド等の欠陥が生じたりして接合にばらつきが大き
い。On the other hand, in the single-sided cooling type shown in FIG. 1, in the case of the solder connection 105, the back surface of the IGBT chip is Al / Cr / Ni / Ag treated, but on the emitter electrode plate 106. Ni plating is applied to Pb-S
It is connected with n or Sn-Sb solder. In this case, Ag diffuses into the solder, Ni and Sn compounds are generated at the interfaces on both sides, and the adhesion is completed. The compound of Ni and Sn does not grow sufficiently unless the temperature reaches 250 ° C or higher.
Similarly, the solder connection between the AlN substrate 102 and the substrate 104 is N
A compound of i and Sn is produced to complete the joining. The formation of the compound of Ni and Sn is considerably affected not only by the bonding temperature but also by the oxide film (NiO, Ni 2 O 3 ) on the surface of the Ni plating film, dirt and gas in the solder, and a large void is generated at the interface and in the solder. There is a large variation in bonding due to defects such as.
【００２４】本実施例では内部電極、絶縁基板上のＡｇ
あるいはＡｕ膜の中の炭素濃度を３０ａｔ％以下にする
だけで、カソード及びアノード電極上のＡｕ，Ａｇ膜と
の低温拡散接合が可能である。炭素は拡散接合を阻害す
る。炭素濃度を３０ａｔ％以下にするためにはＡｇの微
粒子を用いる場合には、有機溶剤からの炭素を除去する
ためＡｇ粒子を塗布した内部電極あるいは絶縁基板を２
５０℃の温度に大気中で加熱すればよい。蒸着あるいは
スパッタによりＡｕあるいはＡｇ膜を形成する場合に
は、炭素を無くせるため加熱処理は不要である。In this embodiment, internal electrodes and Ag on the insulating substrate are used.
Alternatively, low-temperature diffusion bonding with the Au and Ag films on the cathode and anode electrodes is possible only by setting the carbon concentration in the Au film to 30 at% or less. Carbon hinders diffusion bonding. When fine particles of Ag are used to reduce the carbon concentration to 30 at% or less, the internal electrode or the insulating substrate coated with Ag particles for removing carbon from the organic solvent is not used.
It may be heated in the air to a temperature of 50 ° C. When the Au or Ag film is formed by vapor deposition or sputtering, carbon can be eliminated, so that heat treatment is unnecessary.
【００２５】図３（ｂ）に示した構造は、更に大容量化
を目的として、図３（ａ）に示したチップキャリアを多
数に並列接続させるために、絶縁基板３１６，３１７が
内部電極３０７，３０８とＡｇからなる接続層３１４，
３１５により同様に低温接合されている。なお、ゲート
電極３０９はＩＧＢＴ基体３０１の周囲に配置してあ
り、ワイヤボンデイング時にゲート３０２の酸化膜のダ
メージが起こりにい構造となっている。ワイヤの他に薄
板でゲート電極と外部端子とを接続してもよい。この場
合にはアノード及びカソード電極の低温接着と同様の方
法で接合するのがよい。In the structure shown in FIG. 3B, the insulating substrates 316 and 317 have internal electrodes 307 in order to connect a large number of chip carriers shown in FIG. 3A in parallel for the purpose of further increasing the capacity. , 308 and a connection layer 314 made of Ag.
Similarly, low temperature bonding is performed by 315. The gate electrode 309 is arranged around the IGBT substrate 301, and has a structure in which the oxide film of the gate 302 is less likely to be damaged during wire bonding. In addition to the wire, the thin plate may be used to connect the gate electrode and the external terminal. In this case, it is preferable to bond the anode and the cathode electrode by a method similar to the low temperature bonding.
【００２６】図３(ｃ)はＭｏ内部電極上にＮｉめっき膜
を介して粉末あるいはスパッタによりＡｇ膜を設け、同
様の方法によりＡｇ膜を設けたＭｏ内部電極と重ね、２
００℃に大気中で加熱して接着したサンプルの接合強度
比とＡｇ膜中の炭素濃度との関係を示す。Ａｇが３０ａ
ｔ％以上になると接合強度が著しく低下することが分か
る。In FIG. 3 (c), an Ag film is formed on the Mo internal electrode by powder or sputtering through a Ni plating film, and the Ag internal film is laminated by the same method as the Mo internal electrode.
The relationship between the bonding strength ratio and the carbon concentration in the Ag film of the sample bonded by heating to 00 ° C. in the atmosphere is shown. Ag is 30a
It can be seen that the bonding strength is remarkably reduced when t% or more.
【００２７】図５は図４においてゲート５０２とカソー
ド電極５０３の間にＴＩＷ，ＴｉＮ等の高融点金属ある
いは窒化物層５０６を設けたＩＧＢＴの構造を示す。図
において５０５はエミッタ電極、５０７はゲート酸化物
を示す。この図に示す構造のＩＧＢＴ基体を用いて図３
（ａ)，(ｂ）に示すパワーチップキヤリアを同様に作製
することも可能である、強度の高い高融点金属化合物層
５０６がゲート５０２の上部に存在することにより、ゲ
ート酸化物５０７が外部応力から保護され、信頼性が向
上する。FIG. 5 shows the structure of an IGBT in which a refractory metal such as TIW or TiN or a nitride layer 506 is provided between the gate 502 and the cathode electrode 503 in FIG. In the figure, 505 is an emitter electrode and 507 is a gate oxide. By using the IGBT substrate having the structure shown in FIG.
The power chip carrier shown in (a) and (b) can be manufactured in the same manner. Since the refractory metal compound layer 506 having high strength is present above the gate 502, the gate oxide 507 is exposed to external stress. Protected against, and improved reliability.
【００２８】図６は図４及び図５に示したＩＧＢＴチッ
プを用いた単位モジュール、すなわちパワーチップキャ
リアの断面図を示している。本構造の特徴は図６(ａ)に
示すようにエミッタ電極６１４とカソード側内部電極６
０７の凸部とが接着層６０５により固相接合され、ゲー
ト６０２上カソード電極６０３には内部電極が接合され
ていない点にある。熱のヒートシンクとなるエミッタ電
極６１４に内部電極６０７が直接接続されているため、
ゲート６０２上のカソード電極６０３上に接続されるよ
りは熱の冷却効率は向上する。その他は図３（ａ）で示
した構造と同様である。FIG. 6 shows a sectional view of a unit module using the IGBT chips shown in FIGS. 4 and 5, that is, a power chip carrier. This structure is characterized by the emitter electrode 614 and the cathode side internal electrode 6 as shown in FIG.
This is that the convex portion 07 is solid-phase bonded with the adhesive layer 605, and the internal electrode is not bonded to the cathode electrode 603 on the gate 602. Since the internal electrode 607 is directly connected to the emitter electrode 614 which serves as a heat sink for heat,
The cooling efficiency of heat is improved as compared with the case where the cathode 603 on the gate 602 is connected. Others are the same as the structure shown in FIG.
【００２９】図６（ｂ）は更に大容量化を目指して、図
６（ａ）を多数に並列接続するために絶縁基板６１７，
６１８と内部電極６０７，６０８とを接続層６１５，６
１６により低温金属接合した構造を示す。FIG. 6B shows an insulating substrate 617 for connecting a large number of FIG. 6A in parallel in order to further increase the capacity.
618 and the internal electrodes 607 and 608 to connect the connection layers 615 and 6
16 shows a structure in which low temperature metal bonding is performed.
【００３０】以上の実施例において、接着層はＡｇ層か
らなり、その密度は後述するように６０〜１００％の範
囲にあれば、電気伝導度、応力緩和の点から好ましい。
この密度は、使用するＡｇ粒子の大きさ、接合温度によ
って変化する。また、内部電極６０７，６０８として、
Ｍｏ，Ｗのような低熱膨張係数の材料を使用する場合に
は、２００度以上の温度に加熱して、接合層の密度も１
００％に近ずけてもよい。一方、内部電極６０７，６０
８としてＣｕ，Ａｌ及びこれらとＷ，Ｍｏ，ＡｌＮ，Ｓ
ｉＣらの低熱膨張係数の材料との複合材料を使用する場
合には、200度以下の低温で接合することが信頼性を確
保する点で望ましい。In the above examples, the adhesive layer is made of an Ag layer, and the density thereof is preferably in the range of 60 to 100% as described later from the viewpoint of electric conductivity and stress relaxation.
This density changes depending on the size of Ag particles used and the bonding temperature. Also, as the internal electrodes 607 and 608,
When a material having a low coefficient of thermal expansion such as Mo or W is used, it is heated to a temperature of 200 ° C. or higher and the density of the bonding layer is 1
It may be close to 00%. On the other hand, the internal electrodes 607, 60
8 as Cu, Al and these and W, Mo, AlN, S
When using a composite material with a material having a low coefficient of thermal expansion such as iC, it is desirable to join at a low temperature of 200 ° C. or less from the viewpoint of ensuring reliability.
【００３１】以上ＩＧＢＴ基体を用いたパワーチップキ
ャリアの構造について実施例を述べてきたが、本発明は
ＭＯＳ制御型トランジスタの他にもＭＯＳ制御型サイリ
スタにも適用可能である。Although the embodiment of the structure of the power chip carrier using the IGBT substrate has been described above, the present invention can be applied not only to the MOS control type transistor but also to the MOS control type thyristor.
【００３２】図７に本発明のパワーチップキャリアに用
いるＭＯＳ制御型サイリスタ(IGCT)の断面構造を示す。
図において、７０１はＩＧＣＴ、７０２はゲート酸化
膜、７０３はポリＳｉゲート、７０４はサイリスタ上の
絶縁膜、７０５はカソード、７０６はアノード側Ａｌ／
Ｃｒ／Ｎｉ／Ａｇ膜、及び、７０７はエミッタ電極であ
る。サイリスタ上の絶縁膜７０４は、例えばＰＳＧ（Ph
ospo−Silicate−Glass)あるいはＳｉＯ2 を用いる。FIG. 7 shows a sectional structure of a MOS control type thyristor (IGCT) used in the power chip carrier of the present invention.
In the figure, 701 is an IGCT, 702 is a gate oxide film, 703 is a poly-Si gate, 704 is an insulating film on a thyristor, 705 is a cathode, and 706 is an anode side Al /
The Cr / Ni / Ag film and 707 are emitter electrodes. The insulating film 704 on the thyristor is, for example, PSG (Ph
ospo-Silicate-Glass) or SiO 2 .
【００３３】図４に示したＩＧＢＴではエミッタ電極４
０５の長さに対するゲート上のカソード電極４０３の長
さの比が小さい方が高耐圧化、ＯＮ電圧の低減に有効で
あるのに対し、ＩＧＣＴでは図７におけるエミッタ電極
７０７の長さが小さい方が高耐圧化、ＯＮ電圧の低減に
有効である。すなわち、カソード側内部電極との接合面
積を大きくできるため、接合部の信頼性、冷却効率の点
でもパワーチップキャリアに適合した素子であると言え
る。In the IGBT shown in FIG. 4, the emitter electrode 4
A smaller ratio of the length of the cathode electrode 403 on the gate to the length of 05 is more effective in increasing the withstand voltage and reducing the ON voltage, whereas in the IGCT, the length of the emitter electrode 707 in FIG. 7 is smaller. Is effective for increasing the withstand voltage and reducing the ON voltage. That is, since the bonding area with the cathode-side internal electrode can be increased, it can be said that the device is suitable for the power chip carrier in terms of reliability of the bonding portion and cooling efficiency.
【００３４】図８は図７に示したＩＧＣＴを用いて作製
したパワーチップキャリアの断面図を示す。図８（ａ）
は数百Ａまでの容量の範囲で使用する場合である。図に
おいて、８０１はＩＧＣＴ基体、８０２はゲート絶縁
膜、８０３はゲート、８０４は絶縁膜、８０５はカソー
ド電極、８０６はエミッタ電極、８０７はコレクタ側電
極、８０８はカソード側接着層、８０９はコレクタ側接
着層、８１０はカソード側内部電極、８１１はコレクタ
側内部電極、８１２はゲート電極、８１３はボンデイン
グワイヤ、８１４は樹脂、８１５は絶縁支持基板であ
る。カソード電極８０５及びコレクタ電極８０７はＡｌ
／Ｃｒ／Ｎｉ／Ａｇ，Ａｌ／Ｃｒ／Ａｇ及びＡｌ／Ｃｒ
／Ａｇで構成される。カソード側内部電極８１０、及び
コレクタ側内部電極８１１上の接合層８０８，８０９は
Ａｇで構成さる。Ａｇ同志の拡散によりそれぞれカソー
ド電極膜８０５とカソード側内部電極８１０、及び、コ
レクタ側電極８０７とコレクタ側内部電極８１１とが低
温接合されている。ＩＧＣＴ基体８０１それ自体がＯＮ
電圧が低いことに加えて、カソード電極８０５の面積が
大きいため、冷却効率、信頼性の特に優れたパワーチッ
プキャリアができる。またゲート電極８１２はワイヤボ
ンデイング８１３によりゲート端子８１６に接続されて
いる。図８(ｂ)は更に内部電極８１０，８１１と絶縁板
８１９，８２０とを接合したものである。FIG. 8 shows a sectional view of a power chip carrier manufactured by using the IGCT shown in FIG. Figure 8 (a)
Indicates the case of using in the capacity range of several hundred A. In the figure, 801 is an IGCT substrate, 802 is a gate insulating film, 803 is a gate, 804 is an insulating film, 805 is a cathode electrode, 806 is an emitter electrode, 807 is a collector side electrode, 808 is a cathode side adhesive layer, and 809 is a collector side. An adhesive layer, 810 is a cathode side internal electrode, 811 is a collector side internal electrode, 812 is a gate electrode, 813 is a bonding wire, 814 is a resin, and 815 is an insulating support substrate. The cathode electrode 805 and the collector electrode 807 are made of Al.
/ Cr / Ni / Ag, Al / Cr / Ag and Al / Cr
/ Ag. The bonding layers 808 and 809 on the cathode side internal electrode 810 and the collector side internal electrode 811 are made of Ag. The cathode electrode film 805 and the cathode-side internal electrode 810, and the collector-side electrode 807 and the collector-side internal electrode 811 are bonded to each other at a low temperature by diffusion of Ag. IGCT base 801 itself is ON
In addition to the low voltage, the cathode electrode 805 has a large area, so that a power chip carrier having particularly excellent cooling efficiency and reliability can be obtained. The gate electrode 812 is connected to the gate terminal 816 by wire bonding 813. In FIG. 8B, the internal electrodes 810 and 811 are further joined to the insulating plates 819 and 820.
【００３５】図９に２個のチップキャリア９０１を並べ
て、カソード内部電極９０２同志を接続９０３，コレク
タ電極９０４同志を接続９０５，ゲート電極９０６同志
を接続９０７し、絶縁板９０８の上下から冷却フィン９
１０付外部電極９０９により挟み、ネジ９１１により締
めつけ、加圧し、並列動作させることにより、大容量化
して使用するための構造を示す。図において、２個のチ
ップキャリアを均一に加圧するために、カソード側絶縁
物板９０８と冷却フィン付外部電極９０９との間には、
海綿状金属あるいは超弾性合金板９１２が設けられてい
る。本実施例は２個のパワーチップキャリアの場合であ
るが、キャリアの数を増やすことにより、大電力に対応
できる半導体装置が可能になるため、用途に応じてシリ
ーズ化が容易になる。In FIG. 9, two chip carriers 901 are arranged side by side, cathode internal electrodes 902 are connected to each other 903, collector electrodes 904 are connected to each other 905, gate electrodes 906 are connected to each other 907, and cooling fins 9 are provided from above and below the insulating plate 908.
10 shows a structure for use by increasing the capacity by sandwiching it with the external electrode 909 with 10 and tightening with a screw 911, pressurizing, and operating in parallel. In the figure, in order to uniformly pressurize the two chip carriers, between the cathode side insulator plate 908 and the cooling fin-equipped external electrode 909,
A spongy metal or superelastic alloy plate 912 is provided. This embodiment is a case of two power chip carriers, but by increasing the number of carriers, a semiconductor device that can handle a large amount of power becomes possible, and thus series formation is facilitated depending on the application.
【００３６】次にパワーチップキャリアの作製方法につ
いて述べる。図３及び図８に示す内部電極上にめっき，
スパッタ，蒸着等の手法により、Ｎｉ層を設け、この上
部に例えば有機溶媒に懸濁したＡｇの超微粒子（１００
０Å未満）を均一に塗布する。次に、大気中において３
００度以上の温度に加熱し、Ｃを除去する。次の工程で
は、真空中において、同様に加熱し、Ａｇ表面の酸化膜
を除去する。次にIGBT，ＩＧＣＴの電極上のＡｇ層と内
部電極表面のＡｇ層と重ね、１５０〜２５０度の温度範
囲に加熱し接合する。絶縁板と接合する場合も同様にＡ
ｇ層を用いて行い、ワイヤボンデイング、樹脂封止して
完成する。上記したＡｇの微粒子の他に、スパッタした
Ａｇ，Ａｕ膜を用いる場合には、Ｍｏ等内部電極上のＮ
ｉ膜上に常温から１００℃の温度範囲において、スパッ
タ法によりＡｇ膜を厚さ２〜２０μｍ形成する。続い
て、ＭＯＳパワー半導体のアノード，カソード電極と重
ね１００〜２５０℃の温度に大気中、Ｎ2 中で加熱して
接合する。Next, a method of manufacturing the power chip carrier will be described. Plating on the internal electrodes shown in FIG. 3 and FIG.
A Ni layer is provided by a technique such as sputtering or vapor deposition, and an ultrafine particle of Ag (100
(Less than 0Å) is evenly applied. Next, 3 in the atmosphere
C is removed by heating to a temperature of 00 ° C. or higher. In the next step, the same heating is performed in vacuum to remove the oxide film on the Ag surface. Next, the Ag layer on the electrodes of the IGBT and IGCT and the Ag layer on the surface of the internal electrode are overlapped, and heated to a temperature range of 150 to 250 degrees to bond them. Similarly when connecting to an insulating plate
g layer, wire bonding and resin sealing to complete. When a sputtered Ag or Au film is used in addition to the Ag fine particles described above, N on the internal electrode such as Mo is used.
An Ag film having a thickness of 2 to 20 μm is formed on the i film by a sputtering method in a temperature range of room temperature to 100 ° C. Subsequently, the anode and cathode electrodes of the MOS power semiconductor are overlapped and heated at a temperature of 100 to 250 ° C. in N 2 in the air and bonded.
【００３７】[0037]
【発明の効果】本発明によれば、信頼性が高い，低熱抵
抗，大容量のパワーチップキャリア、及び半導体装置を
提供することができる。According to the present invention, it is possible to provide a highly reliable, low thermal resistance, large capacity power chip carrier and a semiconductor device.
【図１】従来の片面冷却方式の半導体モジュールの構造
を示す図である。FIG. 1 is a diagram showing a structure of a conventional single-sided cooling type semiconductor module.
【図２】従来の圧接型両面冷却方式のモジュール構造を
示す図である。FIG. 2 is a view showing a conventional pressure contact type double-sided cooling type module structure.
【図３】本発明のパワーチップキャリアを示す図であ
る。FIG. 3 is a diagram showing a power chip carrier of the present invention.
【図４】本発明のパワーチップキャリアに使用するＩＧ
ＢＴの断面を示す図である。FIG. 4 is an IG used in the power chip carrier of the present invention.
It is a figure which shows the cross section of BT.
【図５】本発明のパワーチップキャリアに使用するＩＧ
ＢＴの断面図である。FIG. 5 is an IG used in the power chip carrier of the present invention.
It is sectional drawing of BT.
【図６】本発明のパワーチップキャリアを示す図であ
る。FIG. 6 is a diagram showing a power chip carrier of the present invention.
【図７】本発明のパワーチップキャリアに使用するＩＧ
ＣＴの断面図である。FIG. 7 is an IG used in the power chip carrier of the present invention.
It is sectional drawing of CT.
【図８】本発明のパワーチップキャリアを示す断面図で
ある。FIG. 8 is a sectional view showing a power chip carrier of the present invention.
【図９】本発明の大用量半導体の断面構造を示す図であ
る。FIG. 9 is a diagram showing a cross-sectional structure of a large-volume semiconductor of the present invention.
３０１…Ｓｉ基体、３０２…ゲート、３０３…カソード
電極、３０４…コレクタ（アノード）側電極、３０５…
カソード側接着層、３０６…コレクタ（アノード）側接
着層、３０７…カソード側内部電極、３０８…コレクタ
（アノード）側内部電極、３０９…ゲート電極、３１０
…ボンデイングワイヤ、３１１…ゲート端子、３１２…
絶縁支持基板、３１３…樹脂、３１４…カソード側絶縁
基板との接着層、３１５…コレクタ（アノード）側絶縁
板との接着層、３１６，３１７…絶縁基板。301 ... Si substrate, 302 ... Gate, 303 ... Cathode electrode, 304 ... Collector (anode) side electrode, 305 ...
Cathode side adhesive layer, 306 ... Collector (anode) side adhesive layer, 307 ... Cathode side internal electrode, 308 ... Collector (anode) side internal electrode, 309 ... Gate electrode, 310
... Bonding wire, 311 ... Gate terminal, 312 ...
Insulating support substrate, 313 ... Resin, 314 ... Adhesive layer with cathode side insulating substrate, 315 ... Adhesive layer with collector (anode) side insulating plate, 316, 317 ... Insulating substrate.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 佐藤 満雄 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 (72)発明者 山田 一二 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 (72)発明者 小林 秀男 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 (72)発明者 長瀬 博 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 (72)発明者 諏訪 正輝 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mitsuo Sato 7-1-1, Omika-cho, Hitachi-shi, Ibaraki Hitachi, Ltd. Hitachi Research Laboratory (72) Inventor, Hitoshi Yamada 7-chome, Omika-cho, Hitachi-shi, Ibaraki No. 1-1 Hitachi Ltd. Hitachi Research Laboratory (72) Inventor Hideo Kobayashi 7-11 Omika-cho, Hitachi-shi, Ibaraki Hitachi Incorporated Hitachi Research Laboratory (72) Inventor Hiroshi Nagase Hitachi City, Ibaraki Prefecture 7-1, Omika-cho, Hitachi Research Laboratory, Hitachi Ltd. (72) Inventor, Masateru Suwa 7-1, 1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi Ltd.
Claims (16)
Ｓ制御型パワー半導体素子と、 上記の半導体基板の一方の主面上に形成された上記半導
体素子のカソード電極と、 上記の半導体基板の一方の主面上に絶縁層を介して形成
された上記半導体素子のゲート電極と、 上記半導体基板の他方の主面上に形成された上記半導体
素子のアノード電極と、 上記カソード電極と金属学的に接合されたカソード側内
部電極と、 上記アノード電極と金属学的に接合されたアノード側内
部電極と、を有するパワーチツプキャリア。1. An MO formed on one main surface of a semiconductor substrate.
An S-controlled power semiconductor element, a cathode electrode of the semiconductor element formed on one main surface of the semiconductor substrate, and the cathode electrode formed on one main surface of the semiconductor substrate via an insulating layer. A gate electrode of a semiconductor element, an anode electrode of the semiconductor element formed on the other main surface of the semiconductor substrate, a cathode-side internal electrode metallurgically bonded to the cathode electrode, the anode electrode and a metal A power chip carrier having an anode-side internal electrode that is logically joined.
アノード電極はＡｌを第１層にし、接合され最上層がＡ
ｇ又はＡｕで構成され、中間層はＣｒ，Ｔｉ又はＮｉか
ら構成される接着層を有することを特徴とするパワーチ
ツプキャリア。2. The cathode electrode and the anode electrode according to claim 1, wherein Al is used as a first layer, and the uppermost layer is joined to A.
A power chip carrier, characterized in that it is made of g or Au, and the intermediate layer has an adhesive layer made of Cr, Ti or Ni.
極及びアノード側内部電極はＮｉを第１層にし、接合さ
れる最上層がＡｇ又はＡｕで構成された接着層を有する
ことを特徴とするパワーチツプキャリア。3. The cathode-side internal electrode and the anode-side internal electrode according to claim 2, wherein Ni is a first layer, and an uppermost layer to be bonded has an adhesive layer composed of Ag or Au. Power chip carrier.
ソード側内部電極との接合、及び、上記アノード電極と
アノード側内部電極との接合はＡｇとＡｇ、又は、Ａｇ
とＡｕとの相互拡散により金属学的接合されていること
を特徴とするパワーチツプキャリア。4. The method according to claim 3, wherein the cathode electrode and the cathode-side internal electrode are joined to each other and the anode electrode and the anode-side internal electrode are joined to each other by Ag and Ag or Ag.
A power chip carrier, which is metallurgically bonded by mutual diffusion of Au and Au.
は、ＡｇとＡｕとの相互拡散により金属学的接合は２５
０℃以下で行われることを特徴とするパワーチツプキャ
リア。5. The metallurgical bond according to claim 4, wherein the metallurgical bonding is 25 due to the mutual diffusion of Ag and Ag or Ag and Au.
A power chip carrier, which is performed at 0 ° C. or lower.
極及びアノード側内部電極はＭｏ若しくはＷ、又は、Ａ
ｌ，ＣｕとＷ，Ｍｏ，ＡｌＮ若しくはＳｉＣの複合材料
からなることを特徴とするパワーチツプキャリア。6. The cathode-side internal electrode and the anode-side internal electrode according to claim 5, wherein Mo or W, or A
A power chip carrier made of a composite material of 1, Cu and W, Mo, AlN or SiC.
絶縁層を介して上記カソード電極が配置されていること
を特徴とするパワーチツプキャリア。7. The power chip carrier according to claim 1, wherein the cathode electrode is disposed on the gate electrode via an insulating layer.
ＴｉＷ，ＴｉＮ、又は、窒化物の層が形成されているこ
とを特徴とするパワーチツプキャリア。8. The power chip carrier according to claim 7, wherein a layer of TiW, TiN, or nitride is formed on the gate electrode.
極は上記カソード電極方向に凸部を有し、上記ゲート電
極上では非接触であることを特徴とするパワーチツプキ
ャリア。9. The power chip carrier according to claim 7, wherein the cathode-side internal electrode has a convex portion in the cathode electrode direction and is not in contact with the gate electrode.
いて、上記パワーチップキャリアが樹脂封止されている
ことを特徴するパワーチツプキャリア。10. A power chip carrier according to claim 1, wherein the power chip carrier is resin-sealed.
ＯＳ制御型パワー半導体素子と、上記の半導体基板の一
方の主面上に形成された上記半導体素子のカソード電極
と、上記の半導体基板の一方の主面上に絶縁層を介して
形成された上記半導体素子のゲート電極と、上記の半導
体基板の他方の主面上に形成された上記半導体素子のア
ノード電極と、上記カソード電極と金属学的に接合され
たカソード側内部電極と、上記アノード電極と金属学的
に接合されたアノード側内部電極とを有する複数のパワ
ーチツプキャリアと、 上記パワーチツプキャリアのそれぞれのカソード側内部
電極及びアノード側内部電極に金属学的に接合した複数
の絶縁基板と、 上記カソード側内部電極に接合した絶縁基板と、及び、
上記アノード側内部電極に接合した絶縁基板とに加圧接
続され、上記複数パワーチツプキャリアを並列的に固定
する第１及び第２の外部電極と、を有するパワー半導体
装置。11. An M formed on one main surface of a semiconductor substrate.
The OS-controlled power semiconductor element, the cathode electrode of the semiconductor element formed on one main surface of the semiconductor substrate, and the cathode formed on one main surface of the semiconductor substrate via an insulating layer. A gate electrode of the semiconductor element, an anode electrode of the semiconductor element formed on the other main surface of the semiconductor substrate, a cathode-side internal electrode metallurgically bonded to the cathode electrode, and the anode electrode A plurality of power chip carriers having a metallurgically bonded anode-side internal electrode, and a plurality of insulating substrates metallurgically bonded to the cathode-side internal electrode and the anode-side internal electrode of each of the power chip carriers, An insulating substrate joined to the cathode-side internal electrode, and
A power semiconductor device comprising: a first and a second external electrode, which are pressure-connected to an insulating substrate bonded to the anode-side internal electrode and fix the plurality of power chip carriers in parallel.
部電極に接合した絶縁基板と上記第１の外部電極間に海
面金属層、又は、超弾性合金層を有することを特徴とす
るパワー半導体装置。12. The power semiconductor device according to claim 11, further comprising a sea surface metal layer or a super elastic alloy layer between the insulating substrate bonded to the cathode side internal electrode and the first external electrode.
部電極と上記絶縁基板間、及び、上記アノード側内部電
極と上記絶縁基板間にはＡｇ又はＡｕを主成分とする接
合層を有することを特徴とするパワー半導体装置。13. A bonding layer containing Ag or Au as a main component between the cathode-side internal electrode and the insulating substrate and between the anode-side internal electrode and the insulating substrate according to claim 11. Power semiconductor device.
て、上記カソード電極及びアノード電極はＡｌを第１層
にし、接合され最上層がＡｇ又はＡｕで構成され、中間
層はＣｒ，Ｔｉ又はＮｉから構成される接着層を有する
ことを特徴とするパワー半導体装置。14. The cathode electrode and the anode electrode according to claim 11, 12 or 13, wherein Al is used as the first layer, and the uppermost layer is joined and composed of Ag or Au, and the intermediate layer is Cr, Ti or Ni. A power semiconductor device having an adhesive layer composed of:
部電極及びアノード側内部電極はＮｉを第１層にし、接
合される最上層がＡｇ又はＡｕで構成された接着層を有
することを特徴とするパワー半導体装置。15. The cathode-side internal electrode and the anode-side internal electrode according to claim 14, wherein Ni is the first layer, and the uppermost layer to be bonded has an adhesive layer composed of Ag or Au. Power semiconductor device.
とカソード側内部電極との接合、及び、上記アノード電
極とアノード側内部電極との接合はＡｇとＡｇ、又は、
ＡｇとＡｕとの相互拡散により金属学的接合されている
ことを特徴とするパワー半導体装置。16. The method according to claim 15, wherein the cathode electrode and the cathode-side internal electrode are joined to each other and the anode electrode and the anode-side internal electrode are joined to each other by Ag and Ag, or
A power semiconductor device characterized by being metallurgically bonded by mutual diffusion of Ag and Au.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06733395A JP3307145B2 (en) | 1995-03-27 | 1995-03-27 | Power chip carrier and power semiconductor device using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06733395A JP3307145B2 (en) | 1995-03-27 | 1995-03-27 | Power chip carrier and power semiconductor device using the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08264765A true JPH08264765A (en) | 1996-10-11 |
| JP3307145B2 JP3307145B2 (en) | 2002-07-24 |
Family
ID=13341998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP06733395A Expired - Fee Related JP3307145B2 (en) | 1995-03-27 | 1995-03-27 | Power chip carrier and power semiconductor device using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3307145B2 (en) |
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| US8558381B2 (en) | 2009-03-23 | 2013-10-15 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device |
| CN109659280A (en) * | 2018-12-27 | 2019-04-19 | 西安中车永电电气有限公司 | A kind of compression joint type IGBT internal enclosing structure |
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| JP3307145B2 (en) | 2002-07-24 |
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