JPH0936186A - Power semiconductor module and its mounting method - Google Patents

Power semiconductor module and its mounting method

Info

Publication number
JPH0936186A
JPH0936186A JP7187446A JP18744695A JPH0936186A JP H0936186 A JPH0936186 A JP H0936186A JP 7187446 A JP7187446 A JP 7187446A JP 18744695 A JP18744695 A JP 18744695A JP H0936186 A JPH0936186 A JP H0936186A
Authority
JP
Japan
Prior art keywords
power semiconductor
semiconductor module
conductor
insulating substrate
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7187446A
Other languages
Japanese (ja)
Inventor
Masahiro Koizumi
正博 小泉
Ryoichi Kajiwara
良一 梶原
Kazuya Takahashi
和弥 高橋
Toshiyuki Takahashi
敏幸 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7187446A priority Critical patent/JPH0936186A/en
Publication of JPH0936186A publication Critical patent/JPH0936186A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/3718—Molybdenum [Mo] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/3754—Coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PROBLEM TO BE SOLVED: To enable a power semiconductor module to be improved in yield, lessened in time required for assembly in an assembly process, and decreased in electrical resistance between an element and an electrode in a conventional intra-chip layout and to provide a mounting structure which ensures the power semiconductor module of a long-term reliability in a practical environment where joints between members comprised in the power semiconductor module are subjected to a temperature cycling load. SOLUTION: An insulating board 3 is provided onto a heat slinger, a silicon semiconductor chip 1 is provided thereon, and an electrode 4 on the insulating board 3 is connected to a pad 2 located on the semiconductor chip 1 with conductors 20 and 21 for the formation of a power semiconductor module, wherein the conductors 20 and 21, the pad 2, and the electrode 4 are bonded together with a solder 12, and a thermal expansion coefficient difference between the conductors 20 and 21 and the heat slinger, the insulating board 3, and the silicon substrate 1 is set below 10×10<-6> / deg.C respectively.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、パワー半導体モジュー
ルに関し、特に各接合部に発生する熱応力を低減したパ
ワー半導体モジュールの実装構造ならびに実装方法に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor module, and more particularly to a mounting structure and a mounting method for a power semiconductor module in which thermal stress generated in each joint is reduced.

【０００２】[0002]

【従来の技術】パワー半導体モジュールは、各種モータ
ーの制御、電力変換機及び無停電電源等広範囲に使用さ
れている。近年、ＩＧＢＴ（絶縁ゲート型バイポーラト
ランジスタ）デバイスの大容量化に伴い、従来サイリス
タが使用されていた領域にもＩＧＢＴモジュールが適用
されつつある。例えば、車両用のインバータ装置は、低
騒音、小型化及び高性能化の要求により、従来のサイリ
スタに代わりＩＧＢＴモジュールの適用が各所で検討さ
れている。2. Description of the Related Art Power semiconductor modules are widely used for controlling various motors, power converters and uninterruptible power supplies. In recent years, with the increase in capacity of IGBT (insulated gate bipolar transistor) devices, the IGBT module is being applied to a region where a thyristor has been conventionally used. For example, in an inverter device for a vehicle, application of an IGBT module has been studied in various places in place of a conventional thyristor due to demands for low noise, miniaturization, and high performance.

【０００３】図１３は従来のパワー半導体モジュールの
構造の概略図であり、（ａ）は平面図、（ｂ）は側面図
である。図において１はシリコン半導体チップ、２は半
導体チップ上に形成されたアルミニウムパッド、３は絶
縁基板、４は絶縁基板上に形成されたＮｉ／Ｃｕ層とし
て設けられた電極、５はアルミニウムパッドと電極とを
接続するために使用されたアルミニウムワイヤ、６は半
導体素子と電極とを接合するために使用された半田、７
は放熱板、８は絶縁基板と放熱板とを接合するために使
用された半田である。FIG. 13 is a schematic view of the structure of a conventional power semiconductor module, (a) is a plan view and (b) is a side view. In the figure, 1 is a silicon semiconductor chip, 2 is an aluminum pad formed on the semiconductor chip, 3 is an insulating substrate, 4 is an electrode provided as a Ni / Cu layer formed on the insulating substrate, and 5 is an aluminum pad and an electrode. Aluminum wire used to connect to the semiconductor element, 6 is solder used to bond the semiconductor element and the electrode, 7
Is a heat radiating plate, and 8 is a solder used for joining the insulating substrate and the heat radiating plate.

【０００４】次に、従来のモジュールの組立て工程につ
いて説明する。シリコン半導体チップ１を絶縁基板３上
の電極４に半田６を用いて接合する。接合は専用治具を
用い、半導体チップと電極４の間に半導体チップとほぼ
同形状の薄いスズが主成分の半田６を置き、水素等の非
酸化性雰囲気中において加熱し、半田を溶融させて両者
を接合する。次いで半導体チップ上に形成されたアルミ
ニウムパッド２と電極４とを太いアルミニウムワイヤ５
を用い、ワイヤボンディングによって接続する。ワイヤ
ボンディングは、アルミニウムワイヤにツールを介し
て、大きな荷重と超音波を印加することによってワイヤ
ならびに接合する相手材を変形させ、両者の酸化膜を除
去し互いに清浄な新生面を露出させる原理で接合するも
のである。最後に、この絶縁基板３を、半田８を用いて
放熱板７に接合する。接合は、前述の半導体チップ１と
絶縁基板３との接合と同様の方法で行われるが、半導体
チップ１と絶縁基板３との間にある半田６が溶融しない
ように、半導体チップの接合に使用された半田６よりも
融点が低い半田８が使用される。Next, a conventional module assembling process will be described. The silicon semiconductor chip 1 is bonded to the electrodes 4 on the insulating substrate 3 using solder 6. For joining, a dedicated jig is used, and a solder 6 having a thin tin as a main component, which has substantially the same shape as the semiconductor chip, is placed between the semiconductor chip and the electrode 4, and heated in a non-oxidizing atmosphere such as hydrogen to melt the solder. And join the two. Next, the aluminum pad 2 and the electrode 4 formed on the semiconductor chip are connected to the thick aluminum wire 5
Are connected by wire bonding. In wire bonding, a large load and ultrasonic waves are applied to an aluminum wire through a tool to deform the wire and the mating material to be bonded, and the oxide film of both is removed to bond clean new surfaces to each other. It is a thing. Finally, the insulating substrate 3 is joined to the heat sink 7 by using the solder 8. The bonding is performed in the same manner as the above-described bonding between the semiconductor chip 1 and the insulating substrate 3, but is used for bonding the semiconductor chips so that the solder 6 between the semiconductor chip 1 and the insulating substrate 3 is not melted. The solder 8 whose melting point is lower than that of the solder 6 is used.

【０００５】パワー半導体モジュールは、大電流を通電
するため半導体チップの発熱が著しく、この発熱に伴い
モジュール全体の温度が上昇する。そのため各接合部に
は部材間の熱膨張率の相違に基づいて熱応力が発生し、
この熱応力により接合界面が破壊するという問題があ
る。従来、絶縁基板と半導体チップとの接合部の信頼性
を高めることを主として検討されてきたが、半導体チッ
プ上のパッドと電極との接続構造に関する検討は不十分
であった。In the power semiconductor module, a large amount of current is passed through the semiconductor chip, so that the semiconductor chip remarkably generates heat, and the temperature of the entire module rises due to this heat generation. Therefore, thermal stress is generated in each joint based on the difference in the coefficient of thermal expansion between the members,
There is a problem that the bonding interface is destroyed by this thermal stress. Conventionally, studies have been mainly made to improve the reliability of the joint portion between the insulating substrate and the semiconductor chip, but studies on the connection structure between the pad on the semiconductor chip and the electrode have been insufficient.

【０００６】[0006]

【発明が解決しようとする課題】パワー半導体モジュー
ルは、大電流をオン、オフするため温度の上下変動が著
しく、各接合部には部材間の熱膨張率の相違に基づいて
発生する熱応力に対する高い信頼性が要求される。従
来、半導体チップと絶縁基板との接合部は、半導体チッ
プの熱膨張率に近い絶縁基板が適用され熱応力の軽減が
図られているが、半導体チップ上のパッド並びに電極と
導体との接合部に作用する熱応力については検討されて
いない。ＩＧＢＴモジュール等のパワー半導体モジュー
ルの半導体チップ上のパッドと電極との接続は、前述の
ように導体としてアルミニウムワイヤが用いられ、接続
の方法はワイヤボンディングで行われている。In the power semiconductor module, since a large current is turned on and off, the temperature fluctuates remarkably, and the thermal stress generated due to the difference in the thermal expansion coefficient between the members at each joint is large. High reliability is required. Conventionally, an insulating substrate having a coefficient of thermal expansion close to that of the semiconductor chip has been applied to the joint between the semiconductor chip and the insulating substrate to reduce thermal stress. The thermal stress acting on is not examined. The connection between the pad and the electrode on the semiconductor chip of the power semiconductor module such as the IGBT module is performed by using the aluminum wire as the conductor as described above, and the connection method is wire bonding.

【０００７】接続方法としてワイヤボンディングを用い
ること及び導体としてアルミニウムを用いることに関し
ては、以下の大きな問題がある。一つは、半導体チップ
上のパッドに接合されたワイヤボンディング部並びに絶
縁基板上の電極との接合部が、長期にわたる温度の上下
変動によって劣化剥離するという問題である。モジュー
ルは車両の走行状態に応じて、温度の上昇、下降のサイ
クルを受ける。この温度サイクルによって、シリコン半
導体チップ並びに絶縁基板（Ａｌ2Ｎ3）の熱膨張率とア
ルミニウムの熱膨張率が大きく異なることに起因して、
両者の接合面寸法と比例した熱歪が接合界面に発生す
る。パッド及び電極とワイヤの接合部には、接合界面外
周部に沿ってクラック先端と同様の鋭い切欠きが不可避
的に形成されており、熱歪によって発生した熱応力がこ
の切欠き先端に集中的に加わって、温度の上下動と共に
クラックが発生する。切欠き先端の応力集中部に発生す
る応力がアルミニウムの破壊強度より小さければ、クラ
ックは発生せず、長期信頼性も保証される。しかし、実
製品で使用されているような直径２００μｍ以上の太線
のワイヤボンディング部では、必ずクラックが発生す
る。クラックの発生を防ぐためには、アルミニウムワイ
ヤの線径を細くし本数を増やせばよいが、半導体チップ
面積の増加やボンディング時間の増大によるコストの上
昇を招く。There are the following major problems in using wire bonding as a connecting method and using aluminum as a conductor. First, there is a problem that the wire bonding portion bonded to the pad on the semiconductor chip and the bonding portion with the electrode on the insulating substrate are deteriorated and peeled due to the vertical fluctuation of the temperature over a long period of time. The module undergoes a cycle of temperature rise and fall according to the running state of the vehicle. Due to this thermal cycle, the coefficient of thermal expansion of the silicon semiconductor chip and the insulating substrate (Al 2 N 3 ) and the coefficient of thermal expansion of aluminum are greatly different.
Thermal strain proportional to the size of the joint surface of the two occurs at the joint interface. A sharp notch similar to a crack tip is inevitably formed along the outer periphery of the joint interface at the joint between the pad and electrode and the wire, and thermal stress generated by thermal strain is concentrated at this notch tip. In addition, cracks occur as the temperature fluctuates. If the stress generated in the stress-concentrated portion at the tip of the notch is smaller than the fracture strength of aluminum, cracks do not occur and long-term reliability is guaranteed. However, cracks always occur at the wire bonding portion of a thick wire having a diameter of 200 μm or more as used in an actual product. In order to prevent the occurrence of cracks, the wire diameter of the aluminum wire may be reduced and the number thereof may be increased. However, this increases the area of the semiconductor chip and the bonding time, resulting in an increase in cost.

【０００８】二つ目は、ワイヤボンディングの際に発生
する半導体チップの損傷である。ボンディング部の温度
サイクルに対する寿命を伸ばすためには、ワイヤを強固
に接合する必要がある。そのためには大きなパワーと荷
重でボンディングするが、この時、パッド下の絶縁層を
破壊し、絶縁耐圧が低下するという問題が発生する。三
つ目は、従来のワイヤによる接続では配線の電気抵抗を
低減することが困難なため、パワー半導体モジュールの
通電容量の増加に対応できないことである。すなわち、
電気抵抗を低減するには、ワイヤ径の増大及び低抵抗の
銅ワイヤを用いる方法があるが、太線ではボンディング
の際により大きなパワーが必要であり、銅ワイヤの場合
では硬いためいずれも前述の半導体チップの損傷が発生
する。The second is damage to the semiconductor chip that occurs during wire bonding. In order to extend the life of the bonding part with respect to the temperature cycle, it is necessary to firmly bond the wires. For that purpose, bonding is performed with a large power and load, but at this time, there arises a problem that the insulating layer under the pad is destroyed and the withstand voltage is lowered. Thirdly, it is difficult to reduce the electrical resistance of the wiring by the conventional wire connection, so that it is not possible to cope with the increase in the current carrying capacity of the power semiconductor module. That is,
In order to reduce the electric resistance, there is a method of increasing the wire diameter and using a copper wire having a low resistance. However, a thick wire requires more power for bonding, and a copper wire is harder. Chip damage occurs.

【０００９】四つ目は、ワイヤボンディングの工程があ
るために、全体の組立て工程に時間がかかり、それに伴
ってコストが上昇し、また以下に述べる工程の複雑さの
ために歩留まりが低下することである。すなわち、前述
したようにモジュールの組立て工程は、主として（１）
絶縁基板への半導体チップの接合、（２）ワイヤボンデ
ィング、（３）放熱板への絶縁基板の接合の３工程で行
われている。（１）及び（３）の接合は半田を用いて行
われるが、（１）の接合の時には、（３）の接合の場合
より融点の高い半田が用いられている。したがって、特
に（３）の接合の際には、極めて慎重な温度管理が必要
とされるが、制御が困難なため接合後の半田にボイドが
発生し、接合部が短時間で劣化、剥離するという問題が
発生する。しかし、半導体チップの接合と放熱板への絶
縁基板の接合を１回の工程で行い、その後ワイヤボンデ
ィングをする方法は採用できない。これは、放熱板には
複数個の絶縁基板を接合するため、外形が大きくなり過
ぎてワイヤボンディングの可動範囲を越えることと、ワ
イヤボンディングで不良が発生するとそのモジュール全
てが不良になるため、歩留まりが非常に低下してしまう
からである。Fourthly, since there is a wire bonding process, the whole assembling process takes time, resulting in an increase in cost and a decrease in yield due to the complexity of the process described below. Is. That is, as described above, the module assembling process mainly includes (1)
It is carried out in three steps: bonding of a semiconductor chip to an insulating substrate, (2) wire bonding, and (3) bonding of an insulating substrate to a heat dissipation plate. The joining of (1) and (3) is performed using solder, but at the time of joining of (1), a solder having a higher melting point than that of the joining of (3) is used. Therefore, particularly in the case of (3) joining, extremely careful temperature control is required, but since it is difficult to control, voids are generated in the solder after joining, and the joining portion deteriorates and peels in a short time. The problem occurs. However, it is not possible to adopt a method in which the semiconductor chip is bonded and the heat dissipation plate is bonded to the insulating substrate in one step, and then wire bonding is performed. This is because a plurality of insulating substrates are bonded to the heat sink, so that the outer shape becomes too large and exceeds the movable range of wire bonding, and if a defect occurs in wire bonding, all the modules will be defective, so the yield Is very low.

【００１０】従来、半導体チップと電極との接続方法に
は、ワイヤボンディングの他にＬＳＩの分野ではワイヤ
を使用しないＴＡＢ（Tape-Automated-Bonding）があ
る。しかし、ＴＡＢによる接続は、ＬＳＩ等の極めて微
弱な電流を信号としてやりとりする分野において適用さ
れており、パワー半導体モジュールのように温度上昇に
よる熱歪の発生の問題は無く、したがって、導体は低抵
抗化のみ考慮されるため銅が主に用いられている。Conventionally, as a method of connecting a semiconductor chip and an electrode, there is TAB (Tape-Automated-Bonding) which does not use a wire in the field of LSI in addition to wire bonding. However, the connection by the TAB is applied in the field of exchanging an extremely weak current as a signal in an LSI or the like, and there is no problem of thermal distortion due to temperature rise unlike a power semiconductor module, and therefore the conductor has a low resistance. Copper is mainly used because it is only considered.

【００１１】本発明は、上記のような問題点を解消する
ためになされたもので、温度サイクルにおけるワイヤ接
合部の劣化の抑制、素子損傷による絶縁耐圧低下の防止
及び製造工程の改善による歩留まりの向上並びに製造工
程時間の短縮を達成できるパワー半導体モジュールの実
装構造並びに実装方法を提供することを目的とする。The present invention has been made in order to solve the above problems, and suppresses deterioration of a wire joint portion in a temperature cycle, prevents reduction in dielectric strength due to element damage, and improves yield by improving a manufacturing process. An object of the present invention is to provide a mounting structure and a mounting method for a power semiconductor module that can achieve improvement and reduction in manufacturing process time.

【００１２】[0012]

【課題を解決するための手段】本発明は、シリコン半導
体チップ上のパッドと電極とを絶縁基板やシリコンとの
熱膨張差の小さい導体によって接続すること、シリコン
半導体チップ上のパッド及び電極と導体との接合を半田
によって行うこと、シリコン半導体チップ上のパッドと
電極とを導電性に優れ断面積の大きい導体によって接続
すること、シリコン半導体チップ上のパッドと電極とを
半田を用い、同一の電極に対しては１個の導体で接続す
ること等によって前記目的を達成する。SUMMARY OF THE INVENTION According to the present invention, a pad and an electrode on a silicon semiconductor chip are connected by an insulating substrate or a conductor having a small thermal expansion difference with silicon, and a pad and an electrode and a conductor on the silicon semiconductor chip are connected. To the pad on the silicon semiconductor chip by connecting the electrode and the electrode on the silicon semiconductor chip by a conductor having excellent conductivity and a large cross-sectional area. With respect to, the above object is achieved by connecting with one conductor.

【００１３】より具体的には、本発明は、放熱板と、放
熱板上に固着された複数の電極を備える絶縁基板と、絶
縁基板の電極上に固着されたシリコン半導体チップとを
含み、絶縁基板のシリコン半導体チップが固着されてい
ない電極とシリコン半導体チップ上の複数のパッドとを
導体で接続して成るパワー半導体モジュールにおいて、
導体とパッド及び電極とは半田によって接合され、導体
は絶縁基板及びシリコンとの熱膨張率の差がいずれも１
０×１０-6／℃以下であることを特徴とする。More specifically, the present invention includes a heat sink, an insulating substrate having a plurality of electrodes fixed on the heat sink, and a silicon semiconductor chip fixed on the electrodes of the insulating substrate. In a power semiconductor module in which an electrode to which a silicon semiconductor chip of a substrate is not fixed and a plurality of pads on the silicon semiconductor chip are connected by a conductor,
The conductor, the pad, and the electrode are joined by solder, and the conductor has a difference in thermal expansion coefficient between the insulating substrate and silicon of 1
It is characterized in that it is 0 × 10 −6 / ° C. or less.

【００１４】また、本発明は、放熱板と、放熱板上に固
着された複数の電極を備える絶縁基板と、絶縁基板の電
極上に固着されたシリコン半導体チップとを含み、絶縁
基板のシリコン半導体チップが固着されていない電極と
シリコン半導体チップ上の複数のパッドとを導体で接続
して成るパワー半導体モジュールにおいて、導体とパッ
ド及び電極とは半田によって接合され、導体は放熱板、
絶縁基板及びシリコンとの熱膨張率の差がいずれも１０
×１０-6／℃以下であることを特徴とする。The present invention also includes a heat sink, an insulating substrate having a plurality of electrodes fixed to the heat sink, and a silicon semiconductor chip fixed to the electrodes of the insulating substrate. In a power semiconductor module in which an electrode to which a chip is not fixed and a plurality of pads on a silicon semiconductor chip are connected by a conductor, the conductor, the pad and the electrode are joined by solder, and the conductor is a heat sink,
The difference in the coefficient of thermal expansion between the insulating substrate and silicon is 10
It is characterized in that it is not more than × 10 -6 / ° C.

【００１５】導体は、低膨張率の金属と高導電性の金属
とのクラッド材、低膨張率の金属と高導電性の金属との
複合材、低膨張率の金属に高導電性の金属がメッキされ
たもの、あるいはセラミックに高導電性の金属がメタラ
イズされたものとすることができ、一部に湾曲部を設け
る等、熱歪を緩和、吸収できる形状とすることが好まし
い。低膨張率の金属はＭｏ，Ｗの群から選ばれた金属と
することができ、高導電性の金属はＣｕ，Ａｌ，Ａｕ，
Ａｇの群の中から選ばれた金属とすることができる。The conductor includes a clad material of a low expansion coefficient metal and a high conductivity metal, a composite material of a low expansion coefficient metal and a high conductivity metal, and a high conductivity metal in a low expansion coefficient metal. It may be plated, or may be metallized with highly conductive metal on ceramics, and it is preferable to have a shape capable of relaxing and absorbing thermal strain, such as by providing a curved portion in part. The metal having a low coefficient of expansion can be a metal selected from the group of Mo and W, and the metal having high conductivity can be Cu, Al, Au,
It can be a metal selected from the group of Ag.

【００１６】また、導体は、シリコン半導体チップ上の
複数のパッドに接続される側が個々のパッドに対応して
複数の部分に分離され、共通の電極に接続される側が一
体化されている櫛状のものとすることができる。パッド
の上には、Ｃｒ，Ｎｉ，ＡｇもしくはＴｉ，Ｎｉ，Ａｕ
の３層、又はＮｉ，Ｔｉ，Ｎｉ，Ａｕの４層から成る金
属膜を形成することができる。The conductor has a comb shape in which the side connected to the plurality of pads on the silicon semiconductor chip is divided into a plurality of portions corresponding to the individual pads, and the side connected to the common electrode is integrated. Can be Cr, Ni, Ag or Ti, Ni, Au on the pad
It is possible to form a metal film consisting of three layers or four layers of Ni, Ti, Ni and Au.

【００１７】本発明によるパワー半導体モジュールの製
造方法は、放熱板への絶縁基板の固着、絶縁基板の電極
へのシリコン半導体チップの固着、並びに絶縁基板の電
極及びシリコン半導体チップ上の複数のパッドと導体と
の接合をすべて半田により１回の工程で行うことを特徴
とする。この製造方法においては、シリコン半導体チッ
プ上のパッドと電極とを接続する導体として、前述のよ
うに、パッドに接続される側が個々のパッドに対応して
複数の部分に分離され、共通の電極に接続される側が一
体化されている櫛状の導体を用いのが好都合である。A method of manufacturing a power semiconductor module according to the present invention comprises fixing an insulating substrate to a heat sink, fixing a silicon semiconductor chip to an electrode of the insulating substrate, and electrodes of the insulating substrate and a plurality of pads on the silicon semiconductor chip. It is characterized in that all the joining with the conductor is performed by soldering in one step. In this manufacturing method, as a conductor for connecting the pad and the electrode on the silicon semiconductor chip, as described above, the side connected to the pad is separated into a plurality of parts corresponding to the individual pads, and a common electrode is formed. It is convenient to use comb-shaped conductors whose connecting sides are integrated.

【００１８】[0018]

【作用】パワーサイクル寿命を伸ばすためには、温度変
動に伴って発生する熱歪を小さくすることが最良の解決
策である。そのためには絶縁基板並びにシリコンに近い
熱膨張率を持つ高導電性材料としてモリブデンやタング
ステンを選択するのがよい。しかし、モリブデン又はタ
ングステンワイヤをワイヤボンディングによって接合す
ることは、これらの金属が硬過ぎて変形させることがで
きないため不可能である。In order to extend the life of the power cycle, the best solution is to reduce the thermal strain generated with temperature fluctuation. For that purpose, it is preferable to select molybdenum or tungsten as the highly conductive material having a thermal expansion coefficient close to that of the insulating substrate and silicon. However, joining molybdenum or tungsten wires by wire bonding is not possible because these metals are too hard to deform.

【００１９】また、ボンディング時における素子の損傷
は、ワイヤボンディングで接続する限り避けらない問題
である。導体の低抵抗化を図るには、アルミニウムより
も抵抗の低い銅や貴金属である金や銀ワイヤを選択する
か、さらに太いアルミニウムワイヤを用いる方法が考え
られる。しかし、金や銀の使用はコスト高になるととも
に、いずれのワイヤを選択しても、アルミニウムワイヤ
に比べ硬く、素子の損傷の発生が問題になる。Further, damage to the element during bonding is an unavoidable problem as long as it is connected by wire bonding. In order to reduce the resistance of the conductor, it is conceivable to select copper or a noble metal such as gold or silver wire having a lower resistance than aluminum, or to use a thicker aluminum wire. However, the use of gold or silver increases the cost, and whichever wire is selected, it is harder than the aluminum wire, which causes a problem that the element is damaged.

【００２０】さらに、組立て工程時間の短縮及び歩留ま
りの向上は、ワイヤボンディングで接続する方法による
かぎり極めて困難である。以上述べたように、従来のワ
イヤボンディングによる接続では、前記した４つの問題
点に対して解決策を見出すことは困難である。そこで、
本発明では温度サイクルによるワイヤ接合部の長寿命化
を図るために、ワイヤボンディングによる接続を止め
て、導体として絶縁基板並びにシリコンの熱膨張率に近
い、高導電性材料を半田で接合し、半導体チップが形成
されているシリコン基板、絶縁基板及び放熱板の各部材
間の熱膨張率を揃えた。Furthermore, it is extremely difficult to shorten the assembly process time and improve the yield as long as the method of connecting by wire bonding is used. As described above, it is difficult to find a solution to the above-mentioned four problems in the conventional connection by wire bonding. Therefore,
In the present invention, in order to prolong the life of the wire bonding portion due to the temperature cycle, the connection by wire bonding is stopped, and a highly conductive material having a thermal expansion coefficient close to that of the insulating substrate and silicon as a conductor is bonded by soldering. The coefficient of thermal expansion among the respective members of the silicon substrate on which the chip is formed, the insulating substrate, and the heat dissipation plate was made uniform.

【００２１】低膨張率の材料には、モリブデンあるいは
タングステンがある。導体としてアルミニウムを用いた
場合には、シリコンとアルミニウム並びに絶縁基板であ
るＡｌ2Ｎ3とアルミニウムとの熱膨張率の差が、いずれ
も約２０×１０-6／℃であるのに対し、導体としてモリ
ブデンやタングステンを用いた場合には、シリコン及び
Ａｌ2Ｎ3との熱膨張率差は約２×１０-6／℃となり、後
者の熱歪量は前者の約１／１０に抑えられる。Materials having a low coefficient of expansion include molybdenum and tungsten. When aluminum is used as the conductor, the difference in the coefficient of thermal expansion between silicon and aluminum and the insulating substrate Al 2 N 3 and aluminum is about 20 × 10 −6 / ° C. When molybdenum or tungsten is used as the material, the difference in coefficient of thermal expansion between silicon and Al 2 N 3 is about 2 × 10 −6 / ° C., and the amount of thermal strain of the latter is suppressed to about 1/10 of that of the former.

【００２２】図３は、シリコン半導体チップ上のパッド
に熱膨張率の異なる導体を半田で接合し、この接合部に
実車を走行させた場合と同様の温度差（Δｔ）を繰り返
し与えた時の接合部の寿命を、シリコンと導体との熱膨
張率の差（△α）をパラメータとして示したものであ
る。試験は、３０℃の雰囲気においたチップに通電して
放熱板が７３℃になるまで加熱し、その後通電を止め、
放熱板が３０℃になるまで放熱板を水冷する工程を１サ
イクルとして、この工程を反復して接合部に繰り返し温
度変化（温度差Δｔ＝４３℃）を与えることによって行
った。そして、導体がパッドから剥離して電流が流れな
くなった時を接合部の寿命とし、それまでに与えた温度
変化のサイクルの回数を計数した。この時、４５００サ
イクルを１年として寿命を年数に換算した。従って寿命
２０年は、９万サイクルに相当する。FIG. 3 shows that when a conductor having a different coefficient of thermal expansion is soldered to a pad on a silicon semiconductor chip and a temperature difference (Δt) similar to that in the case of running an actual vehicle is repeatedly applied to this joint. The life of the joint is shown by using the difference (Δα) in the coefficient of thermal expansion between silicon and the conductor as a parameter. In the test, the chip was placed in an atmosphere of 30 ° C to heat the heat sink until the heat sink reached 73 ° C, and then the current was stopped.
The step of cooling the radiator plate with water until the temperature of the radiator plate reached 30 ° C. was set as one cycle, and this step was repeated to repeatedly change the temperature (temperature difference Δt = 43 ° C.). The life of the joint was defined as the time when the conductor was separated from the pad and no current flowed, and the number of cycles of temperature change applied up to that time was counted. At this time, the life was converted into the number of years with 4500 cycles as one year. Therefore, a life of 20 years corresponds to 90,000 cycles.

【００２３】図３から、寿命はシリコンと導体との熱膨
張率の差Δαが小さいほど長くなることがわかる。導体
として従来のアルミニウムワイヤを用いた場合はΔαが
約２０×１０-6／℃であるため寿命は約１０年であり、
目標の２０年には及ばないことがわかる。目標の２０年
を達成するには導体とシリコンの熱膨張率差Δαを１０
×１０-6／℃以下にする必要があることがわかる。It can be seen from FIG. 3 that the life is longer as the difference Δα in the coefficient of thermal expansion between silicon and the conductor is smaller. When a conventional aluminum wire is used as the conductor, Δα is about 20 × 10 -6 / ° C, so the life is about 10 years.
It turns out that the target of 20 years is not reached. To achieve the target of 20 years, the difference in thermal expansion coefficient between conductor and silicon Δα is 10
It can be seen that it is necessary to control the temperature to be not more than × 10 -6 / ° C.

【００２４】モリブデンあるいはタングステン単体を導
体として使用すると導電性に劣るので、必要な導電性
は、導電性の高いＣｕ，Ａｌ，Ａｕ，Ａｇ等の金属と組
み合わせてクラッド化、複合化あるいはメッキ等を施す
ことで確保する。図４はモリブデンを中心に上下とも同
じ厚さの銅で挟んだ導体において、モリブデンの厚さを
１とした場合における銅の片側の厚さｔと導体の熱膨張
率αとの関係を示したものである。この図から、この構
造の導体の熱膨張率を１０×１０ -6／℃以下にするに
は、片側の銅の厚さを１以下にすればよいことが分か
る。また、モリブデンよりも熱膨張率の小さいタングス
テンを銅で挟めば、タングステンの厚さをモリブデンの
場合よりも薄くできる。Conducting molybdenum or tungsten alone
When used as a body, it is inferior in conductivity, so the required conductivity
Is a highly conductive metal such as Cu, Al, Au, Ag, etc.
Cladding, compounding or plating etc.
Secure it. Figure 4 is the same for molybdenum
The thickness of molybdenum in the conductor sandwiched by the same thickness of copper
Thickness t on one side of copper and thermal expansion of conductor when set to 1
It shows the relationship with the rate α. From this figure,
The thermal expansion coefficient of the built conductor is 10 × 10 -6/ Below ℃
Shows that the thickness of copper on one side should be less than 1
You. It also has a smaller coefficient of thermal expansion than molybdenum.
By sandwiching the ten with copper, the thickness of tungsten is
It can be thinner than the case.

【００２５】上記の導体を半田で接続する場合、電極は
ニッケルメッキが施されているので半田が濡れるが、ア
ルミニウムパッドには半田が濡れるようにメタライズを
施す必要がある。アルミニウムパッドに施すメタライズ
層としては、Ｃｒ／Ｎｉ／Ａｇ、Ｔｉ／Ｎｉ／Ａｕある
いはＮｉ／Ｔｉ／Ｎｉ／Ａｕ層が適している。これらの
メタライズ層は、一般に行われている蒸着あるいはスパ
ッタ法で形成可能である。また、アルミニウムパッドに
メタライズしないで導体を接合するには、アルミニウム
パッドに接触する導体の表面にスズ膜を施し、この導体
をアルミニウムパッドに接触させ加熱しアルミニウムと
スズの合金を形成させればよい。When the above conductors are connected by solder, the electrodes are nickel-plated, so the solder gets wet, but the aluminum pads must be metalized so that the solder gets wet. Cr / Ni / Ag, Ti / Ni / Au, or Ni / Ti / Ni / Au layers are suitable as the metallization layer applied to the aluminum pad. These metallized layers can be formed by a commonly used vapor deposition or sputtering method. Further, in order to join the conductor to the aluminum pad without metallizing, a tin film may be formed on the surface of the conductor that contacts the aluminum pad, and the conductor may be brought into contact with the aluminum pad and heated to form an alloy of aluminum and tin. .

【００２６】一方、モジュールの大容量化に対応するた
めの配線抵抗の低減は、導体にアルミニウムよりも低抵
抗の銅を選択し、上記の方法で接続すればよい。導体に
銅を用いることにより電気抵抗を大幅に低減できるの
で、モジュールの電力損失を小さくでき、大容量化を図
ることが可能である。また、半導体チップの損傷の問題
は、半田による接合のため起こらない。On the other hand, in order to reduce the wiring resistance in order to cope with the large capacity of the module, copper having a lower resistance than aluminum may be selected as the conductor and the connection may be made by the above method. Since the electric resistance can be significantly reduced by using copper for the conductor, the power loss of the module can be reduced and the capacity can be increased. Further, the problem of damage to the semiconductor chip does not occur due to the joining by the solder.

【００２７】従来の組立て工程は、絶縁基板への半導体
チップの接合、ワイヤボンデイングによるパッドと電極
とのワイヤ接続、放熱板への絶縁基板の接合の３工程か
らなる。これに対して、本発明の組立て工程はでは、パ
ッド及び電極と導体との接続を半田で行い、かつ、複数
個の半導体チップのパッドと電極とを同一の電極に対し
１個の導体で接続するため、従来は３工程で行っていた
組立て工程を１工程で完了することができ、作業性の向
上とともに歩留まりの向上を図ることができる。The conventional assembling process consists of three processes of bonding a semiconductor chip to an insulating substrate, wire bonding between pads and electrodes by wire bonding, and bonding an insulating substrate to a heat sink. On the other hand, in the assembly process of the present invention, the pads and electrodes are connected to the conductors by soldering, and the pads and electrodes of the plurality of semiconductor chips are connected to the same electrode by one conductor. Therefore, the assembly process, which has conventionally been performed in three steps, can be completed in one step, and the workability as well as the yield can be improved.

【００２８】[0028]

【実施例】以下、本発明の実施例を図面を用いて詳細に
説明する。図１及び図２により、本発明によるパワー半
導体モジュールの一実施例を説明する。図１（ａ）はモ
ジュールの平面図、図１（ｂ）は側面図であり、図２は
導体の接続部分を拡大して示したものである。図におい
て、ニッケルメッキされた銅膜で形成されているコレク
タ、エミッタ及びゲート電極４がＡｌ2Ｎ3絶縁基板３上
に設けられており、コレクタ電極上にはシリコン基板に
形成された半導体チップ１が半田６によって接合されて
いる。半導体チップ１上のＣｒ／Ｎｉ／Ａｇ膜９がメタ
ライズされたアルミニウムパッド２と銅メッキ１０され
たモリブデン１１からなる導体２０，２１とが半田１２
を介して接合され、その導体の一端はエミッタ並びにゲ
ート電極に半田を介して接合されることにより電気的接
続が成され、この絶縁基板３は半田８を介してモリブデ
ン放熱板１７に固着されている。メタライズ層９の厚さ
は、Ｃｒ層が０.１８μｍ、ニッケル層が０.６μｍ、Ａ
ｇ層が１.３μｍである。導体のモリブデン板１１は幅
が１ｍｍ、厚さ０.５ｍｍで、銅メッキ１０の厚さは５
０μｍである。なお、モリブデンの代わりに、同様に低
熱膨張率の金属例えばタングステンを用いてもよい。ま
た、導体のメッキは銅に限らず、半田で接合できる高導
電性の金属、例えば金、銀等でもよい。Embodiments of the present invention will be described below in detail with reference to the drawings. An embodiment of the power semiconductor module according to the present invention will be described with reference to FIGS. 1 and 2. 1A is a plan view of the module, FIG. 1B is a side view thereof, and FIG. 2 is an enlarged view of a connecting portion of the conductor. In the figure, collector, emitter and gate electrodes 4 formed of a nickel-plated copper film are provided on an Al 2 N 3 insulating substrate 3, and a semiconductor chip 1 formed on a silicon substrate on the collector electrode. Are joined by solder 6. The aluminum pad 2 on which the Cr / Ni / Ag film 9 on the semiconductor chip 1 is metallized and the conductors 20 and 21 made of molybdenum 11 plated with copper 10 are soldered 12
, And one end of the conductor is electrically connected to the emitter and the gate electrode via solder, and the insulating substrate 3 is fixed to the molybdenum radiator plate 17 via the solder 8. There is. The metallized layer 9 has a thickness of 0.18 μm for the Cr layer, 0.6 μm for the nickel layer, and A
The g layer has a thickness of 1.3 μm. The conductor molybdenum plate 11 has a width of 1 mm and a thickness of 0.5 mm, and the copper plating 10 has a thickness of 5 mm.
0 μm. Instead of molybdenum, a metal having a low coefficient of thermal expansion, such as tungsten, may be used as well. Further, the plating of the conductor is not limited to copper, and may be a highly conductive metal such as gold or silver that can be joined by solder.

【００２９】次に、本実施例のパワー半導体モジュール
の実装方法について説明する。図５は絶縁基板３を示
し、平面図（ａ）及び側面図（ｂ）に示すように、銅箔
にニッケルメッキした複数の電極４が銀ロウによってあ
らかじめ接着されている。図６は、実装に使用される黒
鉛治具の説明図であり、（ａ）は上面図、（ｂ）は側面
図、（ｃ）は（ａ）のａ−ａ’断面図である。黒鉛治具
２０は、絶縁基板３及び放熱板１７をその上に位置決め
して載置することができるように縁部領域にストッパ３
１，３２が設けられ、また中央部に貫通孔３３が設けら
れている。ストッパ３１，３２の高さは、絶縁基板３の
厚さに放熱板１７の厚さを足した値にほぼ等しくした。
また、貫通孔３３は、絶縁基板３上に半田付けされる半
導体チップ及び導体２０，２１の外形線を結んだ形をし
ている。Next, a method of mounting the power semiconductor module of this embodiment will be described. FIG. 5 shows the insulating substrate 3, and as shown in the plan view (a) and the side view (b), a plurality of electrodes 4 plated with nickel on a copper foil are pre-bonded with silver solder. 6A and 6B are explanatory views of a graphite jig used for mounting. FIG. 6A is a top view, FIG. 6B is a side view, and FIG. 6C is a sectional view taken along the line aa ′ of FIG. The graphite jig 20 has a stopper 3 in the edge region so that the insulating substrate 3 and the heat dissipation plate 17 can be positioned and placed thereon.
1, 32 are provided, and a through hole 33 is provided in the central portion. The heights of the stoppers 31 and 32 were set to be approximately equal to the value obtained by adding the thickness of the heat dissipation plate 17 to the thickness of the insulating substrate 3.
The through hole 33 has a shape in which the semiconductor chip to be soldered on the insulating substrate 3 and the outlines of the conductors 20 and 21 are connected.

【００３０】図１に示した半導体モジュールは、図７に
示す工程によって組立てられる。まず図７（ａ）の断面
図に示すように、黒鉛治具３０のストッパ３１，３２で
定められた領域に電極４側を下にした絶縁基板３、絶縁
基板の面積とほぼ同じ面積のＳｎ−Ｐｂ等の半田シート
２３、及び放熱板１７を重ねて載せる。次に、断面図
（ｂ）に示すように、その上に別の黒鉛治具３５をかぶ
せ、治具３０，３５に対して絶縁基板３及び放熱板１７
を固定する。次いで、全体をひっくり返し、（ｃ）に示
すように、黒鉛治具３０の貫通部を通して露出された絶
縁基板３の電極４上に半田シートを置き、中央の電極上
の定められた位置に半導体チップ１を置く。さらに半導
体チップ１のパッド上に半田を載せる。次いで、導体２
０，２１を所定位置に載置する。この時、半導体チップ
１と導体２０，２１の間にできる隙間に別に用意した黒
鉛治具３６，３７を挿入し、各チップ１及び導体２０，
２１の位置がずれないように固定する。その後、（ｄ）
に示すように、半田付けされる導体２０，２１及び半導
体チップ１の上に重り３８を載せる。なお、（ｅ）は
（ｄ）の要部拡大図である。最後に、全体を水素雰囲気
の電炉中に通し、例えば１９０℃で約３０分間加熱する
ことにより、放熱板１７、絶縁基板３及び導体２０，２
１を半田で同時に接合する。The semiconductor module shown in FIG. 1 is assembled by the steps shown in FIG. First, as shown in the cross-sectional view of FIG. 7A, the insulating substrate 3 with the electrode 4 side down in a region defined by the stoppers 31 and 32 of the graphite jig 30 and Sn having an area substantially the same as the area of the insulating substrate. -The solder sheet 23 of Pb or the like and the heat radiating plate 17 are placed on top of each other. Next, as shown in the cross-sectional view (b), another graphite jig 35 is placed on the insulating board 3 and the heat dissipation plate 17 with respect to the jigs 30 and 35.
Is fixed. Then, the whole is turned over, and as shown in (c), a solder sheet is placed on the electrode 4 of the insulating substrate 3 exposed through the penetrating portion of the graphite jig 30, and the semiconductor is placed at a predetermined position on the central electrode. Place chip 1. Further, solder is placed on the pads of the semiconductor chip 1. Then conductor 2
Place 0, 21 in place. At this time, the separately prepared graphite jigs 36 and 37 are inserted into the gaps formed between the semiconductor chip 1 and the conductors 20 and 21, and the chips 1 and the conductors 20 and
Fix the position of 21 so that it does not shift. After that, (d)
A weight 38 is placed on the conductors 20 and 21 and the semiconductor chip 1 to be soldered, as shown in FIG. Note that (e) is an enlarged view of a main part of (d). Finally, the whole is passed through an electric furnace in a hydrogen atmosphere and heated at 190 ° C. for about 30 minutes, for example, to dissipate the heat dissipation plate 17, the insulating substrate 3 and the conductors 20 and 2.
1 is soldered together.

【００３１】本実施例によれば、導体２０，２１の熱膨
張率は６.１×１０-6／℃であり、導体とシリコンとの
熱膨張率差は２.６×１０-6／℃、導体とＡｌ2Ｎ3との
熱膨張率差は１.７×１０-6／℃と、いずれも１０×１
０-6／℃以下であるため、温度サイクルにおいて接合部
に発生する熱歪を小さくでき、モジュールの長寿命化を
図ることができる。また、アルミニウムパッドとエミッ
タ並びにゲート電極との接続が一体型の導体で行われる
ため、半田付けの作業性に優れている上に導体のパッド
への接続、半導体チップの絶縁基板上への固着並びに絶
縁基板の放熱板への固着を１回の半田付け工程で行うこ
とができ、組立て工程時間の短縮及び歩留まり向上が図
れる。According to this embodiment, the thermal expansion coefficient of the conductors 20 and 21 is 6.1 × 10 -6 / ° C, and the thermal expansion coefficient difference between the conductor and silicon is 2.6 × 10 -6 / ° C. , The thermal expansion coefficient difference between the conductor and Al 2 N 3 is 1.7 × 10 −6 / ° C., which is 10 × 1 in both cases.
Since it is 0 −6 / ° C. or less, the thermal strain generated at the joint during the temperature cycle can be reduced, and the life of the module can be extended. Further, since the aluminum pad is connected to the emitter and the gate electrode by an integral type conductor, the workability of soldering is excellent, the conductor is connected to the pad, and the semiconductor chip is fixed on the insulating substrate. Since the insulating substrate can be fixed to the heat sink in a single soldering step, the assembly process time can be shortened and the yield can be improved.

【００３２】図８に、導体接合部の他の実施例を示す。
図示したのは、Ａｌ2Ｎ3絶縁基板３上にシリコン基板に
形成された半導体チップ１が搭載され、この半導体チッ
プ上のアルミニウムパッド２と絶縁基板上の電極４とが
モリブデン１１を中心に銅１３が上下にクラッドされた
導体で接続された構造である。Ｃｒ／Ｎｉ／Ａｇの蒸着
膜層９がメタライズされたアルミニウムパッド２上に、
モリブデン１１を中心に上下を銅１３で挟んだクラッド
材の導体が半田を介して接合されている。メタライズ層
９の厚さは、Ｃｒ層が０.１８μｍ、Ｎｉ層が０.６μ
ｍ、Ａｇ層が１.３μｍである。導体のモリブデン１１
は幅が１ｍｍ、厚さ０.３ｍｍで、銅１３の厚さは上下
それぞれ０.１ｍｍである。モジュールの組立ては前記
実施例と同様の方法で行い、パッド上にＳｎ−Ｐｂ半田
シート１２を置き、その上に導体を重ね合わせた後、水
素雰囲気中で加熱して接合した。FIG. 8 shows another embodiment of the conductor joint portion.
A semiconductor chip 1 formed on a silicon substrate is mounted on an Al 2 N 3 insulating substrate 3, and an aluminum pad 2 on this semiconductor chip and an electrode 4 on the insulating substrate are made of copper with molybdenum 11 as the center. 13 is a structure in which conductors clad in the upper and lower sides are connected. On the aluminum pad 2 on which the vapor deposition film layer 9 of Cr / Ni / Ag is metallized,
A conductor of a clad material sandwiching copper 13 between the upper and lower sides of molybdenum 11 is joined via solder. The metallized layer 9 has a thickness of 0.18 μm for the Cr layer and 0.6 μm for the Ni layer.
m, Ag layer is 1.3 μm. Conductor molybdenum 11
Has a width of 1 mm and a thickness of 0.3 mm, and the thickness of the copper 13 is 0.1 mm at the top and bottom respectively. The module was assembled in the same manner as in the above-described embodiment, the Sn-Pb solder sheet 12 was placed on the pad, the conductors were superposed on it, and then heated in a hydrogen atmosphere to be joined.

【００３３】本実施例によれば、導体２０，２１の熱膨
張率は７.８×１０-6／℃であり、導体とシリコンとの
熱膨張率の差は４.３×１０-6／℃、導体とＡｌ2Ｎ3と
の熱膨張率の差は３.４×１０-6／℃と、いずれもと１
０×１０-6／℃以下であり、温度サイクルにおける熱歪
を小さくできるためモジュールの長寿命化が図れ、か
つ、低抵抗の銅とクラッドされているので配線抵抗が低
下し、モジュールの電力損失を小さくできることによ
り、大容量化を図ることが可能である。なお、中心の導
体はモリブデンに限らず、低熱膨張率の他の金属例えば
タングステンでもなんら問題がない。また、クラッドす
る金属は銅に限定されず高導電性の銀、金あるいはニッ
ケルでもよい。According to this embodiment, the coefficient of thermal expansion of the conductors 20 and 21 is 7.8 × 10 −6 / ° C., and the difference in coefficient of thermal expansion between the conductor and silicon is 4.3 × 10 −6 /. ℃, the difference in the coefficient of thermal expansion between the conductor and Al 2 N 3 is 3.4 × 10 -6 / ℃, which is originally 1
It is less than 0 × 10 -6 / ° C, and the thermal strain in the temperature cycle can be reduced to extend the life of the module, and because it is clad with low resistance copper, the wiring resistance is reduced and the power loss of the module is reduced. By making it possible to increase the capacity, it is possible to increase the capacity. The conductor at the center is not limited to molybdenum, but another metal having a low coefficient of thermal expansion such as tungsten can be used without any problem. Further, the metal to be clad is not limited to copper and may be highly conductive silver, gold or nickel.

【００３４】図９に、導体接合部の他の実施例を示す。
図示したのは、Ａｌ2Ｎ3絶縁基板３上にシリコン基板に
形成した半導体チップ１が搭載され、この半導体チップ
上のアルミニウムパッド２と絶縁基板上の電極４とがモ
リブデンと銅との複合材１４の導体で接続された構造で
ある。複合材１４は、モリブデン３０〜５０重量％、残
部銅の組成を有し、平均粒径４μｍのモリブデンを金型
に入れて５ｔ／ｃｍ2の圧力を加えて１４００〜１５０
０℃に加熱してモリブデン焼結体を形成し、そのモリブ
デン焼結体に平均粒径１μｍの銅粉をからめ、水素雰囲
気中で１１００℃に加熱して銅をモリブデン中に含浸し
て形成した。この複合材１４の熱膨張率は８〜１０×１
０-6／℃であった。複合材１４からなる導体は、Ｃｒ／
Ｎｉ／Ａｇの蒸着膜層９がメタライズされたアルミニウ
ムパッド２上に、半田１２を介して接合した。FIG. 9 shows another embodiment of the conductor joint portion.
A semiconductor chip 1 formed on a silicon substrate is mounted on an Al 2 N 3 insulating substrate 3, and an aluminum pad 2 on the semiconductor chip and an electrode 4 on the insulating substrate are made of a composite material of molybdenum and copper. The structure is connected by 14 conductors. The composite material 14 has a composition of molybdenum of 30 to 50% by weight and the balance of copper, and molybdenum having an average particle diameter of 4 μm is put into a mold and a pressure of 5 t / cm 2 is applied to 1400 to 150.
A molybdenum sintered body was formed by heating to 0 ° C., a copper powder having an average particle diameter of 1 μm was entangled in the molybdenum sintered body, and the molybdenum sintered body was heated to 1100 ° C. in a hydrogen atmosphere to impregnate copper into molybdenum. . The coefficient of thermal expansion of this composite material 14 is 8 to 10 × 1.
It was 0 -6 / ° C. The conductor made of the composite material 14 is Cr /
The Ni / Ag vapor deposition film layer 9 was bonded to the aluminum pad 2 metallized via solder 12.

【００３５】本実施例によれば、導体とシリコンとの熱
膨張率の差は４.５〜６.５×１０-6／℃、導体とＡｌ2
Ｎ3との熱膨張率の差は３.６〜５.６×１０-6／℃と、
いずれも１０×１０-6／℃以下であるため、温度サイク
ルにおいて接合部に発生する熱歪を小さくでき、モジュ
ールの長寿命化を図ることができる。また、導体を構成
する複合材は、モリブデンと銅との複合材に限定され
ず、低熱膨張の金属と高導電性との複合材、例えばモリ
ブデンと銅、タングステンと銅、モリブデンあるいはタ
ングステンと銀の複合材でもよい。According to this embodiment, the difference in the coefficient of thermal expansion between the conductor and silicon is 4.5 to 6.5 × 10 −6 / ° C., and the conductor and Al 2
The difference in the coefficient of thermal expansion from N 3 is 3.6 to 5.6 × 10 −6 / ° C.,
Since both are 10 × 10 −6 / ° C. or less, the thermal strain generated at the joint portion during the temperature cycle can be reduced, and the life of the module can be extended. Further, the composite material forming the conductor is not limited to a composite material of molybdenum and copper, but a composite material of a low thermal expansion metal and high conductivity, such as molybdenum and copper, tungsten and copper, molybdenum or tungsten and silver. It may be a composite material.

【００３６】図１０に、導体接合部の他の実施例を示
す。図示したのは、Ａｌ2Ｎ3絶縁基板３上にシリコン基
板に形成した半導体チップ１が搭載され、この半導体チ
ップ上のアルミニウムパッド２と絶縁基板上の電極４と
が銅メッキ１０されたＡｌ2Ｎ3セラミック１６からなる
導体で接続された構造である。Ｃｒ／Ｎｉ／Ａｇの蒸着
膜層９がメタライズされたアルミニウムパッド２上に、
Ａｌ2Ｎ3セラミック１６を中心に周囲を銅メッキ１０で
覆ってなる導体が半田１２を介して接合されている。FIG. 10 shows another embodiment of the conductor joint portion. A semiconductor chip 1 formed on a silicon substrate is mounted on an Al 2 N 3 insulating substrate 3, and an aluminum pad 2 on the semiconductor chip and an electrode 4 on the insulating substrate are plated with copper 10 to form an Al 2 film. The structure is such that the conductors made of N 3 ceramic 16 are connected. On the aluminum pad 2 on which the vapor deposition film layer 9 of Cr / Ni / Ag is metallized,
A conductor formed by covering the periphery of the Al 2 N 3 ceramic 16 with a copper plating 10 is joined via a solder 12.

【００３７】本実施例によれば、導体の中心に熱膨張率
が４.４×１０-6／℃と極めて小さいＡｌ2Ｎ3セラミッ
クがあリ、かつ高導電性の銅がメッキされているため、
導電性を損なうことがなく温度サイクルにおける熱歪を
小さくできるため長寿命化を図ることができる。なお、
Ａｌ2Ｎ3に代えて他のセラミック、例えばアルミナを用
いても同様の効果が得られる。According to this embodiment, the center of the conductor is coated with Al 2 N 3 ceramic having a very small coefficient of thermal expansion of 4.4 × 10 −6 / ° C. and copper having high conductivity. For,
Since the thermal strain in the temperature cycle can be reduced without impairing the conductivity, the life can be extended. In addition,
Similar effects can be obtained by using other ceramics such as alumina instead of Al 2 N 3 .

【００３８】図１１及び図１２は、本発明によるパワー
半導体モジュールの他の実施例を示すものである。図１
１（ａ）はモジュールの平面図、図１１（ｂ）は側面図
であり、図１２は導体の接続部分を拡大して示したもの
である。この実施例では、導体とアルミニウムパッドの
接合を半田ではなくスズとアルミニウムとの拡散によっ
て行う。11 and 12 show another embodiment of the power semiconductor module according to the present invention. FIG.
1 (a) is a plan view of the module, FIG. 11 (b) is a side view, and FIG. 12 is an enlarged view of a conductor connecting portion. In this embodiment, the conductor and aluminum pad are joined by diffusion of tin and aluminum rather than solder.

【００３９】本実施例のパワー半導体モジュールにおい
ては、ニッケルメッキされた銅膜で形成されているコレ
クタ、エミッタ及びゲート電極４がＡｌ2Ｎ3絶縁基板３
上に設けられており、コレクタ電極上には半田６で半導
体チップ１が接合されている。半導体チップ１上のアル
ミニウムパッド２と銅メッキ１０されたモリブデン１１
からなる導体とがＡｌ−Ｓｎ化合物層１５により接合さ
れ、その導体の一端はエミッタ並びにゲート電極に半田
を介して接合されて電気的接続が成され、この絶縁基板
３は半田６を介してモリブデン放熱板１７に固着されて
いる。銅メッキ１０の厚さは５０μｍ、モリブデン１１
は幅１ｍｍで厚さが０.５ｍｍである。接合は、銅メッ
キされたモリブデンからなる導体の、少なくともアルミ
ニウムパッド２と接触する部分に厚さ１０μｍのＳｎメ
ッキを施し、この導体をアルミニウムパッドに押し当て
２５０℃程度に加熱する方法で行った。In the power semiconductor module of this embodiment, the collector, emitter and gate electrodes 4 formed of a nickel-plated copper film are made of Al 2 N 3 insulating substrate 3.
The semiconductor chip 1 is provided on the collector electrode and is soldered onto the collector electrode. Aluminum pad 2 on semiconductor chip 1 and copper-plated molybdenum 11
And a conductor made of Al-Sn compound layer 15 are joined together, and one end of the conductor is joined to the emitter and the gate electrode via solder to form an electrical connection. The insulating substrate 3 is molybdenum via solder 6. It is fixed to the heat dissipation plate 17. Copper plating 10 has a thickness of 50 μm, molybdenum 11
Has a width of 1 mm and a thickness of 0.5 mm. The joining was performed by a method in which at least a portion of the copper-plated molybdenum conductor in contact with the aluminum pad 2 was Sn-plated with a thickness of 10 μm, and the conductor was pressed against the aluminum pad and heated to about 250 ° C.

【００４０】本実施例によれば、モリブデンの熱膨張率
が５.２×１０-6／℃と極めて小さいため、銅メッキを
施してもシリコンとの熱膨張率の差は２.６×１０-6／
℃、Ａｌ2Ｎ3との熱膨張率の差は１.７×１０-6／℃
と、いずれも１０×１０-6／℃以下である。その結果、
温度サイクルにおいて接合部に発生する熱歪を小さくで
き、モジュールの長寿命化を図ることができる。また、
アルミニウムパッドとエミッタ並びにゲート電極との接
続が一体型の導体で構成されているため、半田付けの作
業性に優れている上に導体のパッドへの接続、半導体チ
ップの絶縁基板上への固着並びに絶縁基板の放熱板への
固着が１回の半田付け工程で行うことができ、組立て工
程時間の短縮及び歩留まり向上が図れる。According to this embodiment, since the coefficient of thermal expansion of molybdenum is as extremely small as 5.2 × 10 −6 / ° C., the difference in coefficient of thermal expansion from silicon is 2.6 × 10 even when copper plating is applied. -6 /
℃, the difference in coefficient of thermal expansion from Al 2 N 3 is 1.7 × 10 -6 / ℃
And both are 10 × 10 −6 / ° C. or less. as a result,
It is possible to reduce the thermal strain generated at the joint portion in the temperature cycle, and it is possible to extend the life of the module. Also,
Since the connection between the aluminum pad, the emitter and the gate electrode is made of an integral type conductor, the workability of soldering is excellent, the conductor is connected to the pad, and the semiconductor chip is fixed on the insulating substrate. The insulating substrate can be fixed to the heat sink in a single soldering step, and the assembly process time can be shortened and the yield can be improved.

【００４１】[0041]

【発明の効果】低抵抗の金属と低膨張率の材料とを組合
せたシリコン基板並びに絶縁基板との熱膨張率の差が小
さい導体で電気的接続が成されているため、電気抵抗が
下がり、かつ温度サイクル負荷時の熱歪の発生を抑制で
きることにより、接合部の長寿命化が図れ、また、アル
ミニウムパッドとエミッタ並びにゲート電極との接続が
一体型の導体で構成されているため、半田付けの作業性
に優れている上に導体のパッドへの接続、半導体チップ
の絶縁基板上への固着並びに絶縁基板の放熱板への固着
が１回の半田付け工程で行うことができ、組立て工程時
間の短縮及び歩留まり向上が図れるという効果がある。The electrical resistance is lowered because the electrical connection is made by the conductor having a small difference in the coefficient of thermal expansion from the silicon substrate and the insulating substrate in which the metal having the low resistance and the material having the low expansion coefficient are combined. In addition, since the occurrence of thermal strain during temperature cycle load can be suppressed, the life of the joint can be extended, and since the connection between the aluminum pad, the emitter and the gate electrode is made of an integral conductor, soldering is possible. In addition to excellent workability, the conductor can be connected to the pad, the semiconductor chip can be fixed to the insulating substrate, and the insulating substrate can be fixed to the heat sink in a single soldering process. There is an effect that the manufacturing cost can be shortened and the yield can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明によるパワー半導体モジュールの一実施
例を示す平面図及び側面図。FIG. 1 is a plan view and a side view showing an embodiment of a power semiconductor module according to the present invention.

【図２】図１の導体接続部分の拡大図。FIG. 2 is an enlarged view of a conductor connecting portion of FIG.

【図３】シリコン及びＡｌ2Ｎ3絶縁基板と導体の熱膨張
率の差と寿命との関係図。FIG. 3 is a graph showing the relationship between the difference in the coefficient of thermal expansion between silicon and an Al 2 N 3 insulating substrate and the conductor and the life.

【図４】モリブデンを銅で挟んだ導体の熱膨張率をモリ
ブデンと銅との厚さの比で示した図。FIG. 4 is a diagram showing a coefficient of thermal expansion of a conductor in which molybdenum is sandwiched by copper as a ratio of thicknesses of molybdenum and copper.

【図５】絶縁基板の説明図。FIG. 5 is an explanatory diagram of an insulating substrate.

【図６】モジュールの実装に用いる黒鉛治具の説明図。FIG. 6 is an explanatory diagram of a graphite jig used for mounting a module.

【図７】本発明によるパワー半導体モジュールの実装方
法の説明図。FIG. 7 is an explanatory diagram of a method for mounting a power semiconductor module according to the present invention.

【図８】導体としてモリブデンと銅とのクラッドを用い
た実施例を示す図。FIG. 8 is a diagram showing an example in which a clad of molybdenum and copper is used as a conductor.

【図９】導体としてモリブデンと銅との複合体を用いた
実施例を示す図。FIG. 9 is a diagram showing an example using a composite of molybdenum and copper as a conductor.

【図１０】導体として銅メッキを施したＡｌ2Ｎ3を用い
た実施例を示す図。FIG. 10 is a diagram showing an example in which copper-plated Al 2 N 3 is used as a conductor.

【図１１】本発明によるパワー半導体モジュールの他の
実施例を示す平面図及び側面図。FIG. 11 is a plan view and a side view showing another embodiment of the power semiconductor module according to the present invention.

【図１２】図１１の導体接続部分の拡大図。FIG. 12 is an enlarged view of the conductor connecting portion of FIG. 11.

【図１３】従来のパワー半導体モジュールの構造図。FIG. 13 is a structural diagram of a conventional power semiconductor module.

【符号の説明】[Explanation of symbols]

１：半導体チップ、２：電極パッド、３：Ａｌ2Ｎ3絶縁
基板、４：外部電極、 ５：アルミニウムワイヤ、６：
半田、７：放熱板、８：半田、９：Ｃｒ−Ｎｉ−Ａｇ
層、１０：銅メッキ、１１：モリブデン、１２：半田、
１３：銅クラッド、１４：銅とモリブデンの複合材、１
５：Ｓｎ−Ａｌ化合物、１６：Ａｌ2Ｎ3セラミック、１
７：モリブデン放熱板、２０，２１：導体、３０：黒鉛
治具、３１，３２：ストッパ、３３：貫通孔、３８：重
り1: semiconductor chip, 2: electrode pad, 3: Al 2 N 3 insulating substrate, 4: external electrode, 5: aluminum wire, 6:
Solder, 7: Heat sink, 8: Solder, 9: Cr-Ni-Ag
Layer, 10: copper plating, 11: molybdenum, 12: solder,
13: Copper clad, 14: Composite material of copper and molybdenum, 1
5: Sn-Al compound, 16: Al 2 N 3 ceramic, 1
7: Molybdenum heat sink, 20, 21: conductor, 30: graphite jig, 31, 32: stopper, 33: through hole, 38: weight

───────────────────────────────────────────────────── フロントページの続き (72)発明者 高橋 敏幸 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiyuki Takahashi 7-1, 1-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory

Claims (14)

【特許請求の範囲】[Claims] 【請求項１】 放熱板と、前記放熱板上に固着された複
数の電極を備える絶縁基板と、前記絶縁基板の電極上に
固着されたシリコン半導体チップとを含み、前記絶縁基
板のシリコン半導体チップが固着されていない電極と前
記シリコン半導体チップ上の複数のパッドとを導体で接
続して成るパワー半導体モジュールにおいて、 前記導体とパッド及び電極とは半田によって接合され、
前記導体は前記絶縁基板及びシリコンとの熱膨張率の差
がいずれも１０×１０-6／℃以下であることを特徴とす
るパワー半導体モジュール。1. A silicon semiconductor chip of the insulating substrate, comprising: a heat sink, an insulating substrate having a plurality of electrodes fixed on the heat sink, and a silicon semiconductor chip fixed on the electrodes of the insulating substrate. In a power semiconductor module in which electrodes are not fixed and a plurality of pads on the silicon semiconductor chip are connected by a conductor, the conductor, the pads and the electrodes are joined by solder,
The power semiconductor module, wherein the conductor has a difference in thermal expansion coefficient between the insulating substrate and silicon of 10 × 10 −6 / ° C. or less. 【請求項２】 放熱板と、前記放熱板上に固着された複
数の電極を備える絶縁基板と、前記絶縁基板の電極上に
固着されたシリコン半導体チップとを含み、前記絶縁基
板のシリコン半導体チップが固着されていない電極と前
記シリコン半導体チップ上の複数のパッドとを導体で接
続して成るパワー半導体モジュールにおいて、 前記導体とパッド及び電極とは半田によって接合され、
前記導体は前記放熱板、絶縁基板及びシリコンとの熱膨
張率の差がいずれも１０×１０-6／℃以下であることを
特徴とするパワー半導体モジュール。2. A silicon semiconductor chip of the insulating substrate, comprising: a heat sink, an insulating substrate having a plurality of electrodes fixed on the heat sink, and a silicon semiconductor chip fixed on the electrodes of the insulating substrate. In a power semiconductor module in which electrodes are not fixed and a plurality of pads on the silicon semiconductor chip are connected by a conductor, the conductor, the pads and the electrodes are joined by solder,
The power semiconductor module, wherein the conductors have a difference in thermal expansion coefficient between the heat dissipation plate, the insulating substrate and silicon of 10 × 10 −6 / ° C. or less. 【請求項３】 前記導体は、低膨張率の金属と高導電性
の金属とのクラッド材であることを特徴とする請求項１
又は２記載のパワー半導体モジュール。3. The conductor is a clad material made of a metal having a low coefficient of expansion and a metal having a high conductivity.
Alternatively, the power semiconductor module according to item 2. 【請求項４】 前記低膨張率の金属はＭｏ，Ｗの群から
選ばれた金属であり、前記高導電性の金属はＣｕ，Ａ
ｌ，Ａｕ，Ａｇの群の中から選ばれた金属であることを
特徴とする請求項３記載のパワー半導体モジュール。4. The low expansion metal is a metal selected from the group of Mo and W, and the high conductivity metal is Cu and A.
The power semiconductor module according to claim 3, wherein the power semiconductor module is a metal selected from the group consisting of 1, Au, and Ag. 【請求項５】 前記導体は、低膨張率の金属と高導電性
の金属との複合材であることを特徴とする請求項１又は
２記載のパワー半導体モジュール。5. The power semiconductor module according to claim 1, wherein the conductor is a composite material of a metal having a low expansion coefficient and a metal having high conductivity. 【請求項６】 前記低膨張率の金属はＭｏ，Ｗの群から
選ばれた金属であり、前記高導電性の金属はＣｕ，Ａ
ｌ，Ａｕ，Ａｇの群の中から選ばれた金属であることを
特徴とする請求項５記載のパワー半導体モジュール。6. The low expansion metal is a metal selected from the group of Mo and W, and the high conductivity metal is Cu and A.
The power semiconductor module according to claim 5, wherein the power semiconductor module is a metal selected from the group consisting of 1, Au, and Ag. 【請求項７】 前記導体は、低膨張率の金属に高導電性
の金属がメッキされたものであることを特徴とする請求
項１又は２記載のパワー半導体モジュール。7. The power semiconductor module according to claim 1, wherein the conductor is a low-expansion metal plated with a highly conductive metal. 【請求項８】 前記低膨張率の金属はＭｏ，Ｗの群から
選ばれた金属であり、前記高導電性の金属はＣｕ，Ａ
ｌ，Ａｕ，Ａｇの群の中から選ばれた金属であることを
特徴とする請求項５記載のパワー半導体モジュール。8. The low expansion metal is a metal selected from the group of Mo and W, and the high conductivity metal is Cu and A.
The power semiconductor module according to claim 5, wherein the power semiconductor module is a metal selected from the group consisting of 1, Au, and Ag. 【請求項９】 前記導体は、セラミックに高導電性の金
属がメタライズされたものであることを特徴とする請求
項１又は２記載のパワー半導体モジュール。9. The power semiconductor module according to claim 1, wherein the conductor is made of ceramic and metallized with a highly conductive metal. 【請求項１０】 前記導体は、前記シリコン半導体チッ
プ上の複数のパッドに接続される側が個々のパッドに対
応して複数の部分に分離され、共通の電極に接続される
側が一体化されていることを特徴とする請求項１〜９の
いずれか１項記載のパワー半導体モジュール。10. The conductor has a side connected to a plurality of pads on the silicon semiconductor chip separated into a plurality of portions corresponding to individual pads, and a side connected to a common electrode is integrated. The power semiconductor module according to claim 1, wherein the power semiconductor module is a power semiconductor module. 【請求項１１】 前記パッドの上に金属膜が形成されて
成ることを特徴とする請求項１〜１０のいずれか１項記
載のパワー半導体モジュール。11. The power semiconductor module according to claim 1, wherein a metal film is formed on the pad. 【請求項１２】 前記金属膜は、Ｃｒ，Ｎｉ，Ａｇもし
くはＴｉ，Ｎｉ，Ａｕの３層、又はＮｉ，Ｔｉ，Ｎｉ，
Ａｕの４層から成ることを特徴とする請求項１１記載の
パワー半導体モジュール。12. The metal film comprises three layers of Cr, Ni, Ag or Ti, Ni, Au, or Ni, Ti, Ni,
The power semiconductor module according to claim 11, wherein the power semiconductor module comprises four layers of Au. 【請求項１３】 前記導体は、熱歪を緩和する形状を有
することを特徴とする請求項１〜１２のいずれか１項記
載のパワー半導体モジュール。13. The power semiconductor module according to claim 1, wherein the conductor has a shape that alleviates thermal strain. 【請求項１４】 請求項１〜１３のいずれか１項に記載
されたパワー半導体モジュールの製造方法において、放
熱板への絶縁基板の固着、絶縁基板の電極へのシリコン
半導体チップの固着、並びに絶縁基板の電極及びシリコ
ン半導体チップ上の複数のパッドと導体との接合をすべ
て半田により１回の工程で行うことを特徴とするパワー
半導体モジュールの製造方法。14. The method of manufacturing a power semiconductor module according to claim 1, wherein an insulating substrate is fixed to a heat sink, a silicon semiconductor chip is fixed to an electrode of the insulating substrate, and insulation is performed. A method for manufacturing a power semiconductor module, characterized in that all the bonding between the electrodes on the substrate and the plurality of pads on the silicon semiconductor chip and the conductor is performed by soldering in one step.
JP7187446A 1995-07-24 1995-07-24 Power semiconductor module and its mounting method Pending JPH0936186A (en)

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