JPH06232303A - Power semiconductor device - Google Patents

Power semiconductor device

Info

Publication number
JPH06232303A
JPH06232303A JP1775393A JP1775393A JPH06232303A JP H06232303 A JPH06232303 A JP H06232303A JP 1775393 A JP1775393 A JP 1775393A JP 1775393 A JP1775393 A JP 1775393A JP H06232303 A JPH06232303 A JP H06232303A
Authority
JP
Japan
Prior art keywords
container
electrode
terminal
control electrode
plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1775393A
Other languages
Japanese (ja)
Other versions
JP2940328B2 (en
Inventor
Takeharu Koga
丈晴 古閑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=11952501&utm_source=***_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=JPH06232303(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP1775393A priority Critical patent/JP2940328B2/en
Publication of JPH06232303A publication Critical patent/JPH06232303A/en
Application granted granted Critical
Publication of JP2940328B2 publication Critical patent/JP2940328B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To provide a power semiconductor device in compact vessel dimension by a method wherein the end part of a control electrode lead-out terminal fixed on a container is brought into pressure-contact with the control electrode. CONSTITUTION:An integrated chip 1, a source contact plate 3, a coolector contact plate 4 are assembled into the lower vessel part comprising a lower terminal plate 52 and an insulating sidewall 53 and then the end 73 of a gate lead-out terminal 7 is inserted into a hole 31 of the source contact plate 3. Next, the container sidewall 53 is covered with an upper terminal plate 51 having a groove 54 where a gate lead-out terminal 71 is provided and connected to the upper end of the container sidewall 53. At this time, the inner plate part 73 of the gate lead-out terminal 7 at the end of a copper wire 71 is brought into pressure-contact with a gate pad electrode 6 by the force of a disc spring 8 insulated by an insulating plate 81 provided in a recession 55 of the source contact plate 3. Through these procedures, the container dimension can be miniaturized in comparison with that in case of the connection by bonding step of a conductor.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、主電流制御用のゲート
電極をもち、ゲート電圧によりオン・オフ動作をする絶
縁ゲートバイポーラトランジスタ (以下IGBTと略
す) 、MOS型電界効果トランジスタなどの電力用半導
体素子に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power source such as an insulated gate bipolar transistor (hereinafter abbreviated as IGBT) having a gate electrode for controlling a main current, which is turned on / off by a gate voltage, and a MOS field effect transistor. Regarding semiconductor devices.

【0002】[0002]

【従来の技術】上記のような電力用の半導体素子は、半
導体チップを金属などの基板上に固定し、主電極と絶縁
されたゲート電極とゲート端子とは、その電極面に設け
られたゲートパッド部にボンディングされる導線により
接続される。通常、半導体チップの固定基板側は、ドレ
イン電極 (あるいはコレクタ電極) となっており、半導
体チップの表面側、すなわち固定基板側と反対の側の主
電極は、ソース電極 (あるいはエミッタ電極) となって
いる。ソース電極への接続は、導線によるボンディング
方法が用いられることが多い。
2. Description of the Related Art In a power semiconductor device as described above, a semiconductor chip is fixed on a substrate made of metal or the like, and a gate electrode insulated from a main electrode and a gate terminal are provided on a surface of the electrode. It is connected by a conductive wire bonded to the pad portion. Normally, the fixed substrate side of the semiconductor chip is the drain electrode (or collector electrode), and the surface side of the semiconductor chip, that is, the main electrode opposite to the fixed substrate side, is the source electrode (or emitter electrode). ing. For the connection to the source electrode, a bonding method using a conductive wire is often used.

【0003】しかし、ソース電極側も金属などの固定基
板を接触させる構造のものが考えられている。ドレイン
電極およびソース電極の両面に固定基板を接触させるこ
とで、素子の放熱効率をよくすることができ、チップあ
たりの電流容量を向上させることができる。また、従来
のボンディング配線による電圧低下がなくなり、その分
飽和電圧を低くすることができる。同時に、ボンディン
グ配線によるインダクタンス成分もなくなり、電圧の跳
ね上がり等も抑えることができる。さらに、チップが破
壊した場合の爆発をボンディング方法よりも小さく抑え
ることができる。
However, a structure in which a fixed substrate made of metal or the like is also in contact with the source electrode side has been considered. By bringing the fixed substrate into contact with both surfaces of the drain electrode and the source electrode, the heat dissipation efficiency of the device can be improved and the current capacity per chip can be improved. Further, the voltage drop due to the conventional bonding wiring is eliminated, and the saturation voltage can be reduced accordingly. At the same time, the inductance component due to the bonding wiring is eliminated, and the voltage jump can be suppressed. Further, the explosion when the chip is broken can be suppressed smaller than that of the bonding method.

【0004】図2(a) 、(b) は両面加圧接触構造のIG
BT素子を示し、IGBTチップ1の上面のソース電極
2にソース接触板3が、下面の図示しないコレクタ電極
にコレクタ接触板4が接合され、上、下端子板51、52お
よび絶縁性側壁53からなる容器内に収容されている。接
触板3、4および端子板51、52はいずれも金属よりな
る。チップ1上のゲート電極の縁部に設けられたゲート
パッド電極6は、側壁53を貫通するゲート端子71の端部
と導線72により接続されている。上、下端子板51、52と
接触板3、4との間の電気的、熱的導通は、外部からの
圧力による接触によって行われる。
2 (a) and 2 (b) show an IG having a double-sided pressure contact structure.
The BT element is shown. The source contact plate 3 is joined to the source electrode 2 on the upper surface of the IGBT chip 1, and the collector contact plate 4 is joined to the collector electrode (not shown) on the lower surface. The upper and lower terminal plates 51, 52 and the insulating side wall 53 It is housed in a container. The contact plates 3 and 4 and the terminal plates 51 and 52 are made of metal. The gate pad electrode 6 provided on the edge portion of the gate electrode on the chip 1 is connected to the end portion of the gate terminal 71 penetrating the side wall 53 by the conductive wire 72. Electrical and thermal conduction between the upper and lower terminal plates 51 and 52 and the contact plates 3 and 4 is achieved by contact by pressure from the outside.

【0005】[0005]

【発明が解決しようとする課題】図2のようなIGBT
素子を組み立てるには、チップ1のドレイン電極側とソ
ース電極2とにコレクタ接触板4およびソース接触板3
をはんだ付けなどで接着したのち、チップを容器に入れ
る。その後、チップ1のゲートパッド電極6にゲート引
き出し導線72をゲート端子71へとボンディング法により
接続する。容器側壁53は、金属線よりなるゲート端子71
を貫通させる必要があり、またそのゲート端子の位置も
ボンディングの関係からチップ1の近傍で、しかもチッ
プと同程度の高さにする必要がある。また、チップのゲ
ートパッド電極6にゲート引き出し導線72をゲート端子
71と接続のためボンディングするために、ボンディング
ツールがはいるだけのスペースが必要である。このよう
な理由から、容器の寸法が大きくなる。また、ボンディ
ングツールがはいるようにソース接触板3をゲートパッ
ド電極6の部分だけかなり削らなければならないなどの
制約がある。
2. Problem to be Solved by the Invention
To assemble the device, the collector contact plate 4 and the source contact plate 3 are provided on the drain electrode side and the source electrode 2 of the chip 1.
After bonding by soldering etc., put the chip in the container. After that, the gate lead wire 72 is connected to the gate pad electrode 6 of the chip 1 to the gate terminal 71 by a bonding method. The container side wall 53 is a gate terminal 71 made of a metal wire.
Need to be penetrated, and the position of the gate terminal must be near the chip 1 and at the same height as the chip due to bonding. In addition, a gate lead wire 72 is connected to the gate pad electrode 6 of the chip as a gate terminal.
The space for the bonding tool is required to bond with 71. For this reason, the size of the container becomes large. In addition, there is a restriction that the source contact plate 3 must be considerably cut only at the portion of the gate pad electrode 6 so that a bonding tool is put therein.

【0006】本発明の目的は、このような観点から、ゲ
ートパッド電極とゲート端子の接続構造を工夫すること
により、コンパクトな容器寸法の電力用半導体素子を提
供することにある。
From this point of view, it is an object of the present invention to provide a power semiconductor device having a compact container size by devising a connection structure between a gate pad electrode and a gate terminal.

【0007】[0007]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明は、容器に収容される半導体基板が両主面
上にそれぞれ主電極、一主面上に半導体基板と絶縁され
た制御電極を有し、主電極と容器両面の端子板との間に
接触板が介在する電力用半導体素子において、制御電極
に容器に固定される制御電極引き出し端子の先端部が加
圧接触するものとする。あるいは、半導体基板の主面上
に絶縁して設けられ、制御電極と導線によって接続され
た中継電極に制御電極引き出し端子の先端部が加圧接触
するものとする。そして、制御電極と同一主面上に存在
する主電極のための接触板の制御電極引き出し端子に対
向する部分に穴、凹部あるいは切り欠き部を有すること
が有効である。また、加圧接触のための圧力が容器端子
板の凹部に収納されたばねによること、あるいは制御電
極引き出し端子の弾性力によることが有効である。
In order to achieve the above object, according to the present invention, a semiconductor substrate housed in a container is insulated from main electrodes on both main surfaces and insulated from the semiconductor substrate on one main surface. A power semiconductor device having a control electrode and a contact plate interposed between the main electrode and the terminal plates on both sides of the container, in which the tip of the control electrode lead-out terminal fixed to the container comes into pressure contact with the control electrode. And Alternatively, it is assumed that the tip portion of the control electrode lead terminal comes into pressure contact with the relay electrode provided on the main surface of the semiconductor substrate in an insulated manner and connected to the control electrode by the conductive wire. Further, it is effective to have a hole, a concave portion or a cutout portion in a portion of the contact plate for the main electrode existing on the same main surface as the control electrode, the portion facing the control electrode lead terminal. Further, it is effective that the pressure for the pressure contact is caused by the spring housed in the recess of the container terminal plate or by the elastic force of the control electrode lead terminal.

【0008】[0008]

【作用】制御電極と制御電極引き出し端子との接続も直
接あるいは中継電極を介しての加圧接触によることによ
り、導線のボンディングによる場合に比してボンディン
グツールのためのスペースが必要でなく、また引き出し
端子の位置などに対する制約もなくなるので、容器の寸
法が小さくなる。そして、主電極接触板制御電極引き出
し端子に対向して切り欠き部、穴あるいは凹部を形成す
ることにより、もしくは加圧のためのばね収納のための
凹部を容器端子板に形成することにより、一層の小形化
が可能になる。
Since the connection between the control electrode and the control electrode lead-out terminal is made by the pressure contact directly or through the relay electrode, the space for the bonding tool is not required as compared with the case where the conductor wire is bonded, and Since there is no restriction on the position of the lead terminal, the size of the container is reduced. Further, by forming a notch, a hole or a recess facing the main electrode contact plate control electrode lead-out terminal, or by forming a recess for accommodating a spring for pressurization in the container terminal plate, Can be miniaturized.

【0009】[0009]

【実施例】図1(a) 、(b) は本発明の一実施例のIGB
T素子を示し、図2と共通の部分には同一の符号が付さ
れている。図1(b) はIGBTチップ上方から見た平面
図で、チップ1の大きさ20mm角であり、その中央に0.3
mm角のゲートパッド電極6が配置され、その周囲全面に
ソース電極2が設けられている。ソース電極2の点線60
で囲まれた区域にはソース電極2およびシリコン基板と
絶縁されたゲート電極が形成されており、ゲートパッド
電極6はその表面に接触している。また、チップ周辺に
は耐圧向上のためのガードリング11が設けられている。
このチップ1の下面の図示しないコレクタ電極には図1
(a) に示すコレクタ接触板4を、上面のソース電極2に
はソース接触板3をはんだ付け法で接合する。ソース接
触板3には、図3に示すように中央に穴31が明いてい
る。そして図1(b) の線30がソース接触板3とソース電
極2との接合区域を示している。この一体化したチップ
1、ソース接触板3、コレクタ接触板4を、下端子板52
と絶縁性側壁53とからなる容器下部内に組み込んだの
ち、ソース接触板3の穴31にゲート引き出し端子7の先
端部73を挿入する。次いで、ゲート引き出し端子71の入
る溝54を有する上端子板51をかぶせ、容器側壁53の上端
と結合する。ゲート引き出し端子は図4に詳細に示すよ
うに直径0.5mmの銅線71の先端の直径1mmの円板部73
が、ソース接触板3の凹部55内に収容される絶縁板81で
絶縁された皿ばね8の力によりゲートパッド電極6と加
圧接触する。そして、銅線71の周りなどにはふっ素樹脂
のような絶縁物74が取り囲んで、上端子板51およびソー
ス接触板3との絶縁をとっている。上、下端子板51、52
は通常の平形半導体素子と同様にインバータなどの接続
電極体と加圧接触により接続することができ、その際上
端子板51とソース接触板3ならびに下端子板52とコレク
タ接触板4も加圧接触する。しかし、それぞれを加圧し
た状態でろう付けしてもよい。また、外部のゲート配線
は、ゲート引き出し端子7の銅線71の先端と接続する。
1 (a) and 1 (b) show an IGBT according to an embodiment of the present invention.
A T element is shown, and the same parts as those in FIG. 2 are denoted by the same reference numerals. Fig. 1 (b) is a plan view of the IGBT chip seen from above, and the chip 1 is 20 mm square and 0.3 in the center.
The mm-square gate pad electrode 6 is arranged, and the source electrode 2 is provided on the entire surface around the gate pad electrode 6. Source electrode 2 dotted line 60
A gate electrode insulated from the source electrode 2 and the silicon substrate is formed in the area surrounded by, and the gate pad electrode 6 is in contact with the surface thereof. A guard ring 11 is provided around the chip to improve the breakdown voltage.
As shown in FIG.
The collector contact plate 4 shown in (a) is joined to the source electrode 2 on the upper surface of the source contact plate 3 by a soldering method. The source contact plate 3 has a hole 31 at the center as shown in FIG. The line 30 in FIG. 1 (b) shows the joint area between the source contact plate 3 and the source electrode 2. The integrated chip 1, source contact plate 3, and collector contact plate 4 are connected to the lower terminal plate 52.
After being assembled in the lower part of the container consisting of the insulating side wall 53 and the insulating side wall 53, the tip portion 73 of the gate lead terminal 7 is inserted into the hole 31 of the source contact plate 3. Next, the upper terminal plate 51 having the groove 54 into which the gate lead-out terminal 71 is inserted is covered and coupled with the upper end of the container side wall 53. As shown in detail in FIG. 4, the gate lead-out terminal is a 0.5 mm diameter copper wire 71 and a 1 mm diameter disk portion 73 at the tip of the copper wire 71.
However, pressure contact is made with the gate pad electrode 6 by the force of the disc spring 8 insulated by the insulating plate 81 housed in the recess 55 of the source contact plate 3. The copper wire 71 is surrounded by an insulator 74 such as fluororesin to insulate the upper terminal plate 51 and the source contact plate 3 from each other. Upper and lower terminal plates 51, 52
Can be connected by pressure contact to a connecting electrode body such as an inverter as in the case of a normal flat semiconductor device. Contact. However, they may be brazed under pressure. The external gate wiring is connected to the tip of the copper wire 71 of the gate lead terminal 7.

【0010】図5(a) 、(b) 、(c) は本発明の別の実施
例をIGBT素子を示し、(a) が横断面図、(b) は図
(a) の下方から、(c) は図(a) の右方から見た断面図で
あり、前述の各図と共通の部分には同一の符号が付され
ている。この場合は、IGBTチップの一隅にゲート配
線中継板9を接着剤を用いて固定している。この中継板
9は図6に拡大して示すような形状を有し、1辺1mm程
度で厚さ1mm程度のふっ素樹脂基板91の表面にAlよりな
る電極板92を接着したものである。このゲート配線中継
板9の電極板92とチップ一隅のゲートパッド電極6を導
線72のボンディングで接続する。上端子板51には、ゲー
ト引き出し端子用の溝と皿ばね用の凹部があり、絶縁物
74に囲まれたゲート引き出し端子7はその溝54に収容さ
れて固定され、ゲート引き出し端子7の先端部73は、凹
部55に収容された皿ばね8によってゲート配線中継板9
の電極板92に対して加圧される。この素子の使用方法も
上記の実施例の素子と同様である。
FIGS. 5 (a), 5 (b) and 5 (c) show another embodiment of the IGBT element according to the present invention, wherein FIG. 5 (a) is a cross sectional view and FIG.
(a) is a cross-sectional view as viewed from below and (c) is a right-side sectional view of FIG. (a), and the same reference numerals are given to portions common to the above-mentioned drawings. In this case, the gate wiring relay board 9 is fixed to one corner of the IGBT chip using an adhesive. This relay plate 9 has a shape as shown enlarged in FIG. 6, and an electrode plate 92 made of Al is bonded to the surface of a fluororesin substrate 91 having a side of 1 mm and a thickness of 1 mm. The electrode plate 92 of the gate wiring relay plate 9 and the gate pad electrode 6 at one corner of the chip are connected by the conductor wire 72. The upper terminal board 51 has a groove for the gate lead-out terminal and a recess for the disc spring.
The gate lead-out terminal 7 surrounded by 74 is housed and fixed in the groove 54 thereof, and the tip end portion 73 of the gate lead-out terminal 7 is covered by the disc spring 8 housed in the recess 55 to the gate wiring relay plate 9
The electrode plate 92 is pressed. The method of using this element is the same as that of the element of the above embodiment.

【0011】図7は本発明のさらに別の実施例のIGB
T素子を示し、前述の各図と共通の部分には同一の符号
が付されている。この場合は、ソース接触板3の中央に
穴31が明いていることは図1の場合と同様であるが、ゲ
ート引き出し端子7のゲートパッド電極6への加圧を皿
ばねによらないで、ゲート引き出し端子7の金属線75に
弾力性のあるものを使用し、その弾性力によっている。
この素子は、IGBTチップ1の両面にコレクタ接触板
4およびソース接触板をはんだ付け法にて接合したのち
ゲート引き出し端子7の先端部73を手で持ち上げ、それ
と反対側の端部を図(b) に示すように容器側壁53の穴56
に通した後手を離す。手を離したとき、先端部73がチッ
プ1の表面に向かって近づくように金属線が曲がるよう
にすれば、ゲートパット電極6にゲート引き出し端子7
の先端部73が加圧接触し、良好な電気的接続が行われ
る。この構造によれば、皿ばねが不要になると共に、上
端子板51の結合の前にゲート引き出し端子7をゲートパ
ッド電極6に接続することができ、組立てが容易にな
る。またこの構造は、図5に示した構造の素子にも適用
できる。
FIG. 7 shows an IGB according to still another embodiment of the present invention.
The T element is shown, and the same parts as those in the above figures are denoted by the same reference numerals. In this case, the hole 31 is formed in the center of the source contact plate 3 as in the case of FIG. 1, but the gate lead electrode 7 is not pressed against the gate pad electrode 6 by a disc spring. The metal wire 75 of the gate lead-out terminal 7 is made of an elastic material, and its elastic force is used.
In this device, after the collector contact plate 4 and the source contact plate are joined to both surfaces of the IGBT chip 1 by soldering, the tip 73 of the gate lead-out terminal 7 is lifted by hand, and the opposite end is shown in FIG. ) As shown in the
Release the hand after passing through. When the metal wire is bent so that the tip portion 73 approaches the surface of the chip 1 when the hand is released, the gate pad electrode 6 and the gate lead terminal 7 are formed.
The tip end portion 73 of the is brought into pressure contact, and good electrical connection is made. According to this structure, the disc spring is not necessary and the gate lead terminal 7 can be connected to the gate pad electrode 6 before the upper terminal plate 51 is coupled, which facilitates the assembly. This structure can also be applied to the element having the structure shown in FIG.

【0012】[0012]

【発明の効果】本発明によれば、制御電極と制御電極引
き出し端子とを加圧接触によって接続することにより、
導線のボンディングによって接続する場合に比して各種
の制約がなくなり、容器寸法の小形化が可能となった。
また、制御電極と導線によって接続される半導体基板上
の中継電極に引き出し端子を加圧接触させることによ
り、基板の縁部を有効に利用でき、接触板の形状が簡単
となり、容器組み立ても簡単になる効果が生ずる。
According to the present invention, by connecting the control electrode and the control electrode lead terminal by pressure contact,
Compared with the case of connecting by conducting wire bonding, various restrictions are eliminated and the size of the container can be reduced.
In addition, by pressing the lead terminal into pressure contact with the relay electrode on the semiconductor substrate that is connected to the control electrode by the conductor, the edge of the substrate can be effectively used, the shape of the contact plate is simplified, and the container can be easily assembled. The effect of

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例のIGBT素子を示し、(a)
が縦断面図、(b) がチップ平面図
FIG. 1 shows an IGBT element according to an embodiment of the present invention, (a)
Is a vertical section, (b) is a plan view of the chip

【図2】従来のIGBT素子を示し、(a) が横断面図、
(b) が縦断面図
FIG. 2 shows a conventional IGBT device, (a) is a cross-sectional view,
(b) is a vertical section

【図3】図1の素子のソース接触板の斜視図3 is a perspective view of a source contact plate of the device of FIG.

【図4】図1のゲート引き出し端子の斜視図FIG. 4 is a perspective view of the gate lead terminal of FIG.

【図5】本発明の別の実施例のIGBT素子を示し、
(a) はチップ平面図、(b) は縦断面図、(c) は(b) と垂
直の縦断面図
FIG. 5 shows an IGBT device according to another embodiment of the present invention,
(a) is a plan view of the chip, (b) is a vertical sectional view, (c) is a vertical sectional view perpendicular to (b).

【図6】図5の素子のゲート配線中継板の斜視図6 is a perspective view of a gate wiring relay plate of the device of FIG.

【図7】本発明のさらに別の実施例のIGBT素子を示
し、(a) は縦断面図、(b) は(a) のA部斜視図
FIG. 7 shows an IGBT element according to still another embodiment of the present invention, (a) is a longitudinal sectional view, and (b) is a perspective view of part A of (a).

【符号の説明】[Explanation of symbols]

1 IGBTチップ 2 ソース電極 3 ソース接触板 31 穴 4 コレクタ接触板 51 上端子板 52 下端子板 55 凹部 6 ゲートパッド電極 7 ゲート引き出し端子 71 銅線 72 導線 73 ゲート引き出し端子先端部 74 絶縁物 75 弾力性金属線 8 皿ばね 9 ゲート配線中継板 1 IGBT Chip 2 Source Electrode 3 Source Contact Plate 31 Hole 4 Collector Contact Plate 51 Upper Terminal Plate 52 Lower Terminal Plate 55 Recess 6 Gate Pad Electrode 7 Gate Lead Terminal 71 Copper Wire 72 Conductor 73 Gate Lead Terminal Tip 74 Insulator 75 Resilient Metal wire 8 Disc spring 9 Gate wiring relay board

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】容器に収容される半導体基板の両主面上に
それぞれ主電極、一主面上に半導体基板と絶縁された制
御電極を有し、主電極と容器両面の端子板との間に接触
板が介在するものにおいて、制御電極に容器に固定され
る制御電極引き出し端子の先端部が加圧接触することを
特徴とする電力用半導体素子。
1. A semiconductor substrate housed in a container has main electrodes on both main surfaces, and a control electrode insulated from the semiconductor substrate on one main surface, and between the main electrode and the terminal plates on both surfaces of the container. A semiconductor device for electric power, characterized in that the tip of the control electrode lead-out terminal fixed to the container is in pressure contact with the control electrode, with the contact plate interposed therebetween.
【請求項2】容器に収容される半導体基板の両主面上に
それぞれ主電極、一主面上に半導体基板と絶縁された制
御電極を有し、主電極と容器両面の端子板との間に接触
板が介在するものにおいて、半導体基板の主面上に絶縁
して設けられ、制御電極と導線によって接続された中継
電極に制御電極引き出し端子の先端部が加圧接触するこ
とを特徴とする電力用半導体素子。
2. A semiconductor substrate housed in a container has main electrodes on both main surfaces, and a control electrode insulated from the semiconductor substrate on one main surface, and between the main electrode and the terminal plates on both sides of the container. In which the contact plate is interposed, the tip of the control electrode lead terminal comes into pressure contact with the relay electrode which is provided on the main surface of the semiconductor substrate in an insulated manner and which is connected to the control electrode by the conductor. Power semiconductor device.
【請求項3】制御電極と同一主面上に存在する主電極の
ための接触板の制御電極引き出し端子に対向する部分に
穴、凹部あるいは切り欠き部を有する請求項1あるいは
2記載の電力用半導体素子。
3. The electric power according to claim 1, wherein the contact plate for the main electrode existing on the same main surface as the control electrode has a hole, a concave portion or a cutout portion in a portion facing the control electrode lead terminal. Semiconductor device.
【請求項4】加圧接触のための圧力が容器端子板の凹部
に収納されたばねである請求項1、2あるいは3記載の
電力用半導体素子。
4. The power semiconductor device according to claim 1, wherein the pressure for the pressure contact is a spring housed in the recess of the container terminal plate.
【請求項5】加圧接触のための圧力が制御電極引き出し
端子の弾性力である請求項1、2あるいは3記載の電力
用半導体素子。
5. The power semiconductor element according to claim 1, wherein the pressure for the pressure contact is the elastic force of the control electrode lead terminal.
JP1775393A 1993-02-05 1993-02-05 Power semiconductor device Expired - Fee Related JP2940328B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1775393A JP2940328B2 (en) 1993-02-05 1993-02-05 Power semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1775393A JP2940328B2 (en) 1993-02-05 1993-02-05 Power semiconductor device

Publications (2)

Publication Number Publication Date
JPH06232303A true JPH06232303A (en) 1994-08-19
JP2940328B2 JP2940328B2 (en) 1999-08-25

Family

ID=11952501

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1775393A Expired - Fee Related JP2940328B2 (en) 1993-02-05 1993-02-05 Power semiconductor device

Country Status (1)

Country Link
JP (1) JP2940328B2 (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08264765A (en) * 1995-03-27 1996-10-11 Hitachi Ltd Power chip carrier and power semiconductor device using the same
US5661315A (en) * 1995-12-28 1997-08-26 Asea Brown Boveri Ag Controllable power semiconductor component
JPH09260646A (en) * 1996-03-19 1997-10-03 Fuji Electric Co Ltd Semiconductor device
US5705853A (en) * 1995-08-17 1998-01-06 Asea Brown Boveri Ag Power semiconductor module
JP2003218306A (en) * 2002-01-28 2003-07-31 Fuji Electric Co Ltd Semiconductor device and its manufacturing method
JP2012028700A (en) * 2010-07-27 2012-02-09 Denso Corp Semiconductor device
CN103579165A (en) * 2013-11-04 2014-02-12 国家电网公司 Full-pressure-welding power device
KR101482317B1 (en) * 2012-10-30 2015-01-13 삼성전기주식회사 Unit power module and power module package comprising the same
CN104362141A (en) * 2014-11-26 2015-02-18 国家电网公司 High-power crimp-connection type IGBT module
CN107768328A (en) * 2017-10-31 2018-03-06 华北电力大学 A kind of power device for realizing two-side radiation and pressure equilibrium
WO2020152797A1 (en) * 2019-01-23 2020-07-30 三菱電機株式会社 Pressure-contact-type semiconductor device

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08264765A (en) * 1995-03-27 1996-10-11 Hitachi Ltd Power chip carrier and power semiconductor device using the same
US5705853A (en) * 1995-08-17 1998-01-06 Asea Brown Boveri Ag Power semiconductor module
US5661315A (en) * 1995-12-28 1997-08-26 Asea Brown Boveri Ag Controllable power semiconductor component
JPH09260646A (en) * 1996-03-19 1997-10-03 Fuji Electric Co Ltd Semiconductor device
JP2003218306A (en) * 2002-01-28 2003-07-31 Fuji Electric Co Ltd Semiconductor device and its manufacturing method
JP2012028700A (en) * 2010-07-27 2012-02-09 Denso Corp Semiconductor device
US9123683B2 (en) 2012-10-30 2015-09-01 Samsung Electro-Mechanics Co., Ltd. Unit power module and power module package comprising the same
KR101482317B1 (en) * 2012-10-30 2015-01-13 삼성전기주식회사 Unit power module and power module package comprising the same
CN103579165A (en) * 2013-11-04 2014-02-12 国家电网公司 Full-pressure-welding power device
CN103579165B (en) * 2013-11-04 2016-08-31 国家电网公司 A kind of Full-pressure-weldinpower power device
CN104362141A (en) * 2014-11-26 2015-02-18 国家电网公司 High-power crimp-connection type IGBT module
CN107768328A (en) * 2017-10-31 2018-03-06 华北电力大学 A kind of power device for realizing two-side radiation and pressure equilibrium
WO2020152797A1 (en) * 2019-01-23 2020-07-30 三菱電機株式会社 Pressure-contact-type semiconductor device
CN113330580A (en) * 2019-01-23 2021-08-31 三菱电机株式会社 Pressure-bonded semiconductor device
JPWO2020152797A1 (en) * 2019-01-23 2021-09-09 三菱電機株式会社 Pressure welding type semiconductor device

Also Published As

Publication number Publication date
JP2940328B2 (en) 1999-08-25

Similar Documents

Publication Publication Date Title
JP3256636B2 (en) Pressure contact type semiconductor device
US7227259B2 (en) Low-inductance circuit arrangement for power semiconductor modules
JP2801534B2 (en) Power semiconductor module and insulated metal substrate used therefor
US7615854B2 (en) Semiconductor package that includes stacked semiconductor die
JP4384279B2 (en) Semiconductor device
KR100305227B1 (en) Turn-Off High Power Semiconductor Components
JPH10335579A (en) High power semiconductor module device
JP2009512999A (en) Semiconductor package
EP0532244A1 (en) Semiconductor device
JP3129020B2 (en) Semiconductor device
US6285076B1 (en) Press-connection semiconductor device and press-connection semiconductor assembly
JP2940328B2 (en) Power semiconductor device
JP3319569B2 (en) Pressure contact type semiconductor device
US6281569B1 (en) Pressure-contact semiconductor device
KR100820513B1 (en) Circuit arrangement
US5366932A (en) Semi-conductor chip packaging method and semi-conductor chip having interdigitated gate runners with gate bonding pads
JP2001036002A (en) Semiconductor device
JP3629172B2 (en) Pressure contact type semiconductor device
KR101897639B1 (en) power module
JP2993286B2 (en) Semiconductor device
WO2020241239A1 (en) Semiconductor device
JP4077130B2 (en) Gate commutation type turn-off thyristor module
JPH06302734A (en) Semiconductor module for power
US5821616A (en) Power MOS device chip and package assembly
US5798287A (en) Method for forming a power MOS device chip

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080618

Year of fee payment: 9

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080618

Year of fee payment: 9

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080618

Year of fee payment: 9

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090618

Year of fee payment: 10

LAPS Cancellation because of no payment of annual fees