JPH08130379A - Manufacture of multilayer wiring board - Google Patents
Manufacture of multilayer wiring boardInfo
- Publication number
- JPH08130379A JPH08130379A JP26700894A JP26700894A JPH08130379A JP H08130379 A JPH08130379 A JP H08130379A JP 26700894 A JP26700894 A JP 26700894A JP 26700894 A JP26700894 A JP 26700894A JP H08130379 A JPH08130379 A JP H08130379A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- multilayer wiring
- thickness
- counterbore
- inner layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Drilling And Boring (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ハイブリットＩＣの回
路基板に関し、特に、多層の配線層を有する多層配線基
板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board for a hybrid IC, and more particularly to a method for manufacturing a multilayer wiring board having multiple wiring layers.
【０００２】[0002]
【従来の技術】従来、この種の多層配線基板における内
層配線を露呈する座ぐり加工は、工作機の台座を基準と
して座ぐりの残り厚さを規定した方法や、工作機の先端
ツールの降りる量を規制し加工する方法が一般的であっ
た。この座ぐりの残り厚さや先端ツールの降りる量は、
先端ツール位置検出センサで間接的に決められ基板の厚
さや反りによるばらつきを補正し加工することは行なわ
なかった。2. Description of the Related Art Conventionally, counterbore processing for exposing inner layer wiring in a multilayer wiring board of this kind is performed by a method in which the remaining thickness of the counterbore is defined with reference to a pedestal of a machine tool, or the amount by which a tip tool of a machine tool descends. The method of regulating and processing was common. The remaining thickness of this spot facing and the amount of tip tool descending are
The processing was not performed by correcting the variation due to the thickness and warpage of the substrate which is indirectly determined by the tip tool position detection sensor.
【０００３】この方法によると、例えば、一辺が３０ｍ
ｍの正方形状の多層配線基板を例にとってみると、通
常、積層板加工によって成形された多層配線基板は、そ
の反り量が±１００μｍ程度、厚さ精度が約±５０μｍ
程度を含んでいる。そこで、仮に座ぐり後の内層配線の
厚さを最低１０μｍ必要とすると、座ぐり前の初期の内
層配線の厚さは１６０μｍにしなければならなかった。
また、コスト面を無視し高度な技術や材料管理を駆使し
て回路基板反り量を±５０μｍ以下にしさらに厚さ精度
を±３０μｍ以下に抑えたとしても、内層配線の厚さは
９０μｍも必要であった。According to this method, for example, one side is 30 m
Taking an example of a square multilayer wiring board having a square shape of m, a multilayer wiring board formed by laminate processing usually has a warpage of about ± 100 μm and a thickness accuracy of about ± 50 μm.
Including the degree. Therefore, if the thickness of the inner layer wiring after counterbore is required to be at least 10 μm, the thickness of the inner layer wiring before counterbore must be 160 μm.
In addition, even if the amount of warpage of the circuit board is reduced to ± 50 μm or less and the thickness accuracy is controlled to ± 30 μm or less by ignoring the cost and using advanced technology and material management, the thickness of the inner wiring is required to be 90 μm. there were.
【０００４】この結果、内層配線層を厚くするためファ
インパターン化が困難であった。例えば、上述の内層配
線の厚さが１６０μｍの場合では、パターン幅および間
隔がともに１６０μｍ程度で、内層配線の厚さが９０μ
ｍの場合でも、パターン幅と間隔がともに９０μｍ程度
しか得られなかった。As a result, it is difficult to form a fine pattern because the thickness of the inner wiring layer is increased. For example, when the thickness of the inner layer wiring is 160 μm, the pattern width and the interval are both about 160 μm, and the thickness of the inner layer wiring is 90 μm.
Even in the case of m, both the pattern width and the interval were only about 90 μm.
【０００５】さらに、上述したように、座ぐり後の内層
配線の厚さが１０〜１６０μｍあるいは１０〜９０μｍ
もばらつきが生じていた。このため、ワイヤーボンディ
ングを行うＣＯＢ（Ｃｈｉｐ Ｏｎ Ｂｏｒｄ）基板な
どの場合、座ぐり後の内層配線の厚さのばらつきがその
ままボンディングパッドの厚さのばらつきとなってい
た。この厚さのばらつきは、ボンディングパッドの硬度
のばらつきに比例しているため安定したボンディングを
行うことができずボンディング品質に大きく影響してい
た。Further, as described above, the thickness of the inner layer wiring after the spot facing is 10 to 160 μm or 10 to 90 μm.
Also varied. For this reason, in the case of a COB (Chip On Board) substrate for performing wire bonding, the variation in the thickness of the inner layer wiring after the counterbore is directly the variation in the thickness of the bonding pad. Since the thickness variation is proportional to the variation in the hardness of the bonding pad, stable bonding cannot be performed, which greatly affects the bonding quality.
【０００６】[0006]
【発明が解決しようとする課題】上述したように多層配
線基板の製造方法では、内層配線の厚さを少なくとも９
０μｍ以上確保しなければならず、また、そのときの内
層配線のパターン幅・間隔は内層配線の厚さにより制限
されるため少なくとも１００μｍ以上必要であった。さ
らに、座ぐり後の内層配線の厚さのばらつきが大きいた
め特にボンディング品質には大きな影響があった。As described above, in the method for manufacturing the multilayer wiring board, the thickness of the inner wiring is at least 9 mm.
It is necessary to secure 0 μm or more, and the pattern width / interval of the inner layer wiring at that time is at least 100 μm because it is limited by the thickness of the inner layer wiring. Furthermore, since the variation in the thickness of the inner layer wiring after the spot facing is large, the bonding quality is greatly affected.
【０００７】従って、本発明の目的は、基板自体に反り
や厚みのばらつきがあっても座ぐり加工後に露呈する内
層配線層を所望の厚みをに確保しそれによってよりファ
インパターン化が可能な多層配線基板の製造方法を提供
することにある。Therefore, an object of the present invention is to secure a desired thickness of the inner wiring layer exposed after the spot facing even if the substrate itself has a warp or a variation in thickness, and thereby a finer pattern can be formed. It is to provide a method for manufacturing a wiring board.
【０００８】[0008]
【課題を解決するための手段】本発明の第１の特徴は、
多層配線基板を座ぐり加工し内層配線を露呈させる多層
配線基板の製造方法において、前記座ぐり加工を行なう
ツールが前記内層配線に接触するときに得られる電気信
号を検知して前記座ぐりの深さを決定する多層配線基板
の製造方法である。The first feature of the present invention is to:
In the method for manufacturing a multilayer wiring board in which a multilayer wiring board is counterbored to expose inner layer wiring, the depth of the counterbore is detected by detecting an electrical signal obtained when the tool for performing the spot facing contacts the inner layer wiring. Is a method for manufacturing a multilayer wiring board.
【０００９】また、本発明の第２の特徴は、前記多層配
線基板の互に大きく離れた位置に同一内層配線が露呈す
る深さの少なくとも二個所のパイロット座ぐり穴を前記
深さを決める方法で開け、それぞれの前記パイロット座
ぐり穴の深さデータを基に前記多層配線基板の反りや前
記内層配線層の厚みによる前記内装配線面の傾きを算出
して前記パイロット座ぐり穴間の占る領域のそれぞれの
前記座ぐり深さを補正し、補正した深さデータで前記領
域を座ぐり加工を行い前記内層配線を露呈する多層配線
基板の製造方法である。A second feature of the present invention is a method for determining the depth of at least two pilot counterbore holes having a depth at which the same inner layer wiring is exposed at positions greatly separated from each other in the multilayer wiring board. And the inclination of the internal wiring surface due to the warp of the multi-layer wiring board and the thickness of the inner wiring layer is calculated based on the depth data of each pilot counterbore hole and the space between the pilot counterbore holes is calculated. A method of manufacturing a multilayer wiring board, wherein the counterbore depth of each region is corrected, and the region is counterbored with the corrected depth data to expose the inner layer wiring.
【００１０】さらに、本発明の第３の特徴は、前記パイ
ロット座ぐり穴の少なくとも一つが座ぐり加工されずに
残る多層配線基板である。A third feature of the present invention is a multilayer wiring board in which at least one of the pilot counterbore holes remains without being counterbored.
【００１１】[0011]
【実施例】次に、本発明について図面を参照して説明す
る。Next, the present invention will be described with reference to the drawings.
【００１２】図１（ａ）および（ｂ）は本発明の多層配
線基板の製造方法の第１の実施例を説明するための多層
配線基板の断面図である。この多層配線基板の製造方法
は、図１（ａ）に示すように、まず、工作機の台座３の
上に多層回路基板６を装着し、工作機のツール１の先端
と内層配線５が接触したとき電気的に導通を検出するた
めの探針２を内層配線５からの引き出し電極１０に接触
させる。1A and 1B are sectional views of a multilayer wiring board for explaining a first embodiment of the method for manufacturing a multilayer wiring board according to the present invention. In this method of manufacturing a multilayer wiring board, as shown in FIG. 1A, first, a multilayer circuit board 6 is mounted on a pedestal 3 of a machine tool, and the tip of the tool 1 of the machine tool and the inner layer wiring 5 are in contact with each other. Then, the probe 2 for detecting electrical conduction is brought into contact with the lead electrode 10 from the inner wiring 5.
【００１３】次に、多層配線基板６の任意の１箇所にツ
ール１を当てツール１を回転させながら下降させる。そ
して、ツール１が下降し座ぐり加工が進み内層配線５と
ツール１の先端が接触すると、内層配線５にツール１と
の接触により電気回路が閉回路になり電池からの電流が
流れ分圧抵抗の電位差がツール下降停止の電気信号とし
て工作機の制御部に送られる。このことによりツール１
の下降を停止させ引続きプログラム通りに台座３がＸＹ
方向に移動し所望の面積の座ぐり８を加工し内層配線５
を露呈させる。Next, the tool 1 is applied to an arbitrary portion of the multilayer wiring board 6 and is lowered while rotating the tool 1. When the tool 1 descends and the counterbore processing proceeds and the inner layer wiring 5 and the tip of the tool 1 come into contact with each other, the electric circuit becomes a closed circuit due to the contact with the tool 1 on the inner layer wiring 5 and the current from the battery flows and the voltage dividing resistance. Is sent to the control unit of the machine tool as an electric signal for stopping the descent of the tool. This allows Tool 1
And the pedestal 3 is XY as programmed.
In the direction to process the counterbore 8 of a desired area
Expose.
【００１４】この方法によれば、少なくとも回路基板６
の厚さ精度を無視することができるため通常仕様の場合
は、予じめ製作する内層配線５の厚さは例えば、１１０
μｍでよく、このときの内層配線の幅と間隔はそれぞれ
１１０μｍが可能となった。According to this method, at least the circuit board 6
In the case of the normal specification, the thickness of the inner wiring 5 to be manufactured in advance is, for example, 110
μm, and the width and interval of the inner layer wiring at this time can be 110 μm.
【００１５】また、特別な管理を行い回路基板６の反り
量を±５０μｍに抑えた場合、予じめ形成する内層配線
５の厚さは６０μｍで済み、さらに、内層配線５の幅と
間隔はそれぞれ６０μｍにすることができた。このよう
に、内層配線５のファイン化が１１０μｍ程度であれば
通常仕様で十分実現できるため、特別な技術や管理を必
要とせずコストダウンの効果もある。さらに、ファイン
化が必要な場合は、上述のように６０μｍまで実現でき
る。When the warp amount of the circuit board 6 is suppressed to ± 50 μm by special management, the thickness of the inner layer wiring 5 formed beforehand is 60 μm, and the width and the interval of the inner layer wiring 5 are It could be 60 μm in each case. In this way, if the fineness of the inner layer wirings 5 is about 110 μm, it can be sufficiently realized by the normal specifications, so that no special technique or management is required and there is an effect of cost reduction. Further, when finer fineness is required, it can be realized up to 60 μm as described above.
【００１６】図２は図１の多層配線基板の変形例を示す
断面図である。図２に示すように、内層配線５と接続し
基板を貫通するスルーホール電極４をもつ多層配線基板
の場合は、上述の実施例と基本的には製造方法が同じで
あるが、前述の実施例で先端ツール１と内層配線５が接
触したことを電気的に検出するための探針の代わりに、
内層配線５と接続しているスルーホール電極４と電気的
に接触する台座電極３ａを設けたことである。FIG. 2 is a sectional view showing a modification of the multilayer wiring board of FIG. As shown in FIG. 2, in the case of a multilayer wiring board having a through-hole electrode 4 connected to the internal wiring 5 and penetrating the board, the manufacturing method is basically the same as that of the above-described embodiment, In the example, instead of the probe for electrically detecting the contact between the tip tool 1 and the inner layer wiring 5,
The pedestal electrode 3a is provided in electrical contact with the through-hole electrode 4 connected to the inner layer wiring 5.
【００１７】図３（ａ）および（ｂ）は本発明の多層配
線基板の製造方法の第２の実施例を説明するための多層
配線基板の断面図である。まず、図３（ａ）に示すよう
に、多層配線基板６の任意にそれぞれ大きく離れた場所
に少なくとも２ヵ所の複数箇所にパイロット座ぐり穴７
ａ，７ｂ，７ｃの穴明け加工を行なう。ここで、ツール
１の送り量の決定は図２に示した検知回路で行なわれて
いる。また、この図面では３ヵ所のパイロット座ぐりを
行った例である。FIGS. 3A and 3B are cross-sectional views of a multilayer wiring board for explaining a second embodiment of the method for manufacturing a multilayer wiring board according to the present invention. First, as shown in FIG. 3 (a), pilot counterbore holes 7 are formed in at least two locations at arbitrarily large locations on the multilayer wiring board 6.
The holes a, 7b and 7c are drilled. Here, the determination of the feed amount of the tool 1 is performed by the detection circuit shown in FIG. Also, this drawing shows an example in which three pilot spots are carried out.
【００１８】次に、それぞれのパイロット座ぐり穴７
ａ，７ｂ，７ｃの深さデータをツール１の送り量（パル
スモータへの送りパルス数）から求めそれぞれを計算部
の記憶部に入力する。計算部はこれらデータの元に、例
えば、パイロット座ぐり穴７ａのデータを基準にし、パ
イロット座ぐり穴７ｂ，７ｃのＸＹ座標値とそれぞれの
深さデータから増減分の有無および量を演算しＸＹ方向
への傾きを求める。そして、求められた傾きによりパイ
ロット座ぐり穴７ａを基準にしＸ方向への増減分とＹ方
向への増減分を予じめプログラミングされた内装配線５
の領域内の各点のツール１の送りデータに加え補正す
る。Next, each pilot counterbore 7
Depth data of a, 7b, and 7c are obtained from the feed amount of the tool 1 (the number of pulses sent to the pulse motor) and input to the storage unit of the calculation unit. Based on the data of the pilot counterbore hole 7a, the calculation unit calculates the presence / absence and amount of the increase / decrease from the XY coordinate values of the pilot counterbore holes 7b and 7c and the respective depth data based on the data. Find the tilt in the direction. Based on the obtained inclination, the interior wiring 5 is programmed in advance to increase or decrease in the X direction and increase or decrease in the Y direction with reference to the pilot counterbore hole 7a.
Correction is performed in addition to the feed data of the tool 1 at each point in the area.
【００１９】次に、図３（ｂ）に示すように、パイロッ
ト座ぐり穴７ａを基準にしツール１をパイロット座ぐり
穴７ａ，７ｂ，７ｃを含む領域内でＸＹ方向に移動しな
がら補正された増減分でツール１を上下させ座ぐり加工
し内層配線５を露呈させる。Next, as shown in FIG. 3B, the correction is performed while moving the tool 1 in the XY directions within the region including the pilot counterbore holes 7a, 7b, 7c based on the pilot counterbore hole 7a. The tool 1 is moved up and down by the increment or decrement to perform the counterbore processing to expose the inner layer wiring 5.
【００２０】なお、この実施例では内層配線層の厚みの
ばらつきだけでなく基板自体の反りにより内層配線面が
傾いている場合をも適用できる方法である。ここで、座
ぐりの深さ制御精度を±５μｍとした場合、計算上では
内層配線５の厚さは薄くても２０μｍあれば良いことに
なる。実際の内層配線５の厚さは３６μｍ程度に形成さ
れており、この方法によれば、内層配線５の厚みを十分
確保できる。また、この方法によると座ぐり後の内層配
線の厚さのばらつきが最小となり、ワイヤーボンディン
グなど特に配線パターンの硬度に影響される工程に対
し、品質が安定する効果もある。In this embodiment, the method is applicable not only to the variation in the thickness of the inner wiring layer but also to the case where the inner wiring surface is inclined due to the warpage of the substrate itself. Here, when the spot control accuracy of the counterbore depth is set to ± 5 μm, it is sufficient in calculation that the thickness of the inner layer wiring 5 is at least 20 μm. The actual thickness of the inner wiring 5 is formed to be about 36 μm. According to this method, the thickness of the inner wiring 5 can be sufficiently ensured. Further, according to this method, variation in the thickness of the inner layer wiring after counterbore is minimized, and there is also an effect of stabilizing the quality especially in a process such as wire bonding which is affected by the hardness of the wiring pattern.
【００２１】図４（ａ）および（ｂ）は第２の実施例の
変形例を説明するための多層配線基板の平面図である。
上述した実施例では、反り・厚みによる深さデータを算
出するためのパイロット座ぐり穴がその後の座ぐり加工
で無くなるが、本実施例では、必ず一つのパイロット座
ぐり穴が残すことである。FIGS. 4A and 4B are plan views of a multilayer wiring board for explaining a modification of the second embodiment.
In the above-described embodiment, the pilot counterbore for calculating the depth data based on the warpage / thickness is eliminated in the subsequent counterbore machining. However, in the present embodiment, one pilot counterbore is always left.
【００２２】この実施例を、例えば、図４（ａ）に示す
ように、スルーホール電極４ａ，４ｂと接続する内層配
線５ａ，５ｂが形成された多層配線基板６の場合を挙げ
て述べる。まず、内装配線５ａの領域で互に離れた位置
に上述した方法で、パイロット座ぐり穴７ｄ，７ｅを開
ける。次に、上述したように、これらパイロット座ぐり
穴７ａ，７ｂの深さデータよりパイロット座ぐり穴７ｄ
を基準にしＸＹ方向への移動に対する増減分を演算す
る。This embodiment will be described with reference to, for example, a case of a multilayer wiring board 6 having inner wirings 5a and 5b connected to through-hole electrodes 4a and 4b, as shown in FIG. First, pilot counterbore holes 7d and 7e are opened at positions separated from each other in the area of the interior wiring 5a by the above-described method. Next, as described above, from the depth data of these pilot counterbore holes 7a, 7b, pilot counterbore hole 7d is obtained.
Is calculated with respect to the movement in the XY directions.
【００２３】次に、演算されたＸＹ方向に対し補正され
たツールの移動に伴なう上下動によりパイロット座ぐり
穴７ｅを含む領域を座ぐり加工を行ない座ぐり８ａを形
成し内装配線５ａを露呈させる。この結果、多層配線基
板６にパイロット座ぐり穴７ｄは捨座ぐり穴として残
る。この捨穴は、装置本体への組込みの際に多層配線基
板の向きあるいは位置決めに利用されるので組込みが容
易であるとともに取付けの誤りを起さないという別の効
果を得ることができる。Next, the area including the pilot counterbore hole 7e is spotted by the vertical movement accompanying the movement of the tool corrected in the calculated XY directions to form a spotbore 8a, and the interior wiring 5a is formed. Expose. As a result, the pilot counterbore 7d remains in the multilayer wiring board 6 as a counterbore. Since the discarded holes are used for orientation or positioning of the multilayer wiring board when being incorporated into the apparatus main body, it is possible to obtain another effect that it is easy to assemble and does not cause mounting errors.
【００２４】[0024]
【発明の効果】以上説明したように本発明は、削りなが
ら下降し座ぐり加工するツールと多層配線基板の内層配
線面と接触したことを電気的に検出し座ぐり深さを決定
することによって、内線配線への削り込みを最小限に留
めることができるので、多層配線基板の厚みにばらつき
があっても一定の所望の厚みを残して内層配線を基板よ
り露呈することができるという効果がある。As described above, according to the present invention, the tool for descending and counter boring while cutting and the contact with the inner layer wiring surface of the multilayer wiring board are electrically detected to determine the counter boring depth. Since the shaving into the internal wiring can be minimized, there is an effect that the internal wiring can be exposed from the substrate while leaving a certain desired thickness even if the thickness of the multilayer wiring board varies. .
【００２５】また、多層配線基板の厚みのばらつきに加
えて反りがある場合は、内層配線面を露呈する少なくと
も二つのパイロット座ぐり穴を出来るだけ大きく離間し
て開け、これらの座ぐり穴の深さデータから基板の反り
あるいは厚みのばらつきによる内層配線面のＸＹ方向で
の傾きを演算して座ぐり深さを補正する値を求めること
によって、基板の反りあるいは厚みのばらついても内層
配線面の傾きに応じて一定に削り込みができるので、内
線配線層の厚みを薄く形成しても一定の所望の厚みを残
して内層配線を基板より露呈することができるという効
果がある。If there is a warp in addition to the variation in the thickness of the multilayer wiring board, at least two pilot counterbore holes exposing the inner wiring surface are opened as widely as possible, and the depth of these counterbore holes is increased. By calculating the inclination of the inner wiring surface in the XY directions due to the warpage or thickness variation of the substrate from the data, the value for correcting the counterbore depth can be obtained. Since the trimming can be made uniformly according to the inclination, there is an effect that even when the thickness of the internal wiring layer is formed thin, the internal wiring can be exposed from the substrate while maintaining a predetermined desired thickness.
【００２６】さらに、この内層配線層を薄く形成できる
ことはよりファインパターン化ができるこという効果が
ある。Furthermore, the fact that the inner wiring layer can be formed thin has an effect that a finer pattern can be formed.
【図面の簡単な説明】[Brief description of drawings]
【図１】本発明の多層配線基板の製造方法の第１の実施
例を説明するための多層配線基板の断面図である。FIG. 1 is a cross-sectional view of a multilayer wiring board for explaining a first embodiment of a method for manufacturing a multilayer wiring board of the present invention.
【図２】図１の多層配線基板の変形例を示す断面図であ
る。FIG. 2 is a cross-sectional view showing a modified example of the multilayer wiring board of FIG.
【図３】本発明の多層配線基板の製造方法の第２の実施
例を説明するための多層配線基板の断面図である。FIG. 3 is a cross-sectional view of a multilayer wiring board for explaining a second embodiment of the method for manufacturing a multilayer wiring board according to the present invention.
【図４】第２の実施例の変形例を説明するための多層配
線基板の平面図である。FIG. 4 is a plan view of a multilayer wiring board for explaining a modification of the second embodiment.
１ ツール ２ 探針 ３ 台座 ３ａ 台座電極 ４，４ａ，４ｂ スルーホール電極 ５，５ａ，５ｂ 内層配線 ６ 多層配線基板 ７ａ，７ｂ，７ｃ，７ｄ，７ｅ パイロット座ぐり穴 ８，８ａ 座ぐり １０ 引出し電極 Reference Signs List 1 tool 2 probe 3 pedestal 3a pedestal electrode 4, 4a, 4b through-hole electrode 5, 5a, 5b inner-layer wiring 6 multilayer wiring board 7a, 7b, 7c, 7d, 7e pilot counterbore hole 8, 8a counterbore 10 extraction electrode
Claims (3)
露呈させる多層配線基板の製造方法において、前記座ぐ
り加工を行なうツールが前記内層配線に接触するときに
得られる電気信号を検知して前記座ぐりの深さを決定す
ることを特徴とする多層配線基板の製造方法。1. A method for manufacturing a multi-layer wiring board, comprising: spot-working a multi-layer wiring board to expose inner layer wirings, by detecting an electric signal obtained when a tool for performing the spot-making processing contacts the inner layer wirings. A method for manufacturing a multilayer wiring board, characterized in that the depth of the spot facing is determined.
置に同一内層配線が露呈する深さの少なくとも二個所の
パイロット座ぐり穴を請求項１記載の方法で深さを決め
て開け、それぞれの前記パイロット座ぐり穴の深さデー
タを基に前記多層配線基板の反りや前記内層配線層の厚
みによる前記内装配線面の傾きを算出して前記パイロッ
ト座ぐり穴間の占る領域のそれぞれの前記座ぐり深さを
補正し、補正した深さデータで前記領域を座ぐり加工を
行い前記内層配線を露呈することを特徴とする多層配線
基板の製造方法。2. At least two pilot counterbore holes, each having a depth at which the same inner layer wiring is exposed, at positions greatly separated from each other in the multilayer wiring board, the depth is determined by the method according to claim 1, and each of them is opened. Based on the depth data of the pilot counterbore hole, the inclination of the internal wiring surface due to the warp of the multilayer wiring board and the thickness of the inner wiring layer is calculated based on the depth data of the pilot counterbore hole. A method for manufacturing a multilayer wiring board, wherein the counterbore depth is corrected, and the region is counterbored with the corrected depth data to expose the inner layer wiring.
なくとも一つが座ぐり加工されずに残ることを特徴とす
る多層配線基板。3. The multi-layer wiring board according to claim 2, wherein at least one of the pilot counterbore holes according to claim 2 remains without being counterbored.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6267008A JP2609825B2 (en) | 1994-10-31 | 1994-10-31 | Method for manufacturing multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6267008A JP2609825B2 (en) | 1994-10-31 | 1994-10-31 | Method for manufacturing multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08130379A true JPH08130379A (en) | 1996-05-21 |
| JP2609825B2 JP2609825B2 (en) | 1997-05-14 |
Family
ID=17438782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6267008A Expired - Fee Related JP2609825B2 (en) | 1994-10-31 | 1994-10-31 | Method for manufacturing multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2609825B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1093251A (en) * | 1996-09-10 | 1998-04-10 | Airex:Kk | Method of machining multilayer printed board |
| WO2002001928A1 (en) * | 2000-06-26 | 2002-01-03 | 3M Innovative Properties Company | Vialess printed circuit board |
| KR100342845B1 (en) * | 1999-11-12 | 2002-07-10 | 박철호 | The equipment grinding system ang connestion of small size PCB bold |
| JP2006173146A (en) * | 2004-12-10 | 2006-06-29 | Hitachi Via Mechanics Ltd | Multilayer circuit board and method for manufacturing the same |
| JP2017135297A (en) * | 2016-01-29 | 2017-08-03 | ローランドディー．ジー．株式会社 | Processing device and processing method |
| JP2018018963A (en) * | 2016-07-28 | 2018-02-01 | ビアメカニクス株式会社 | Depth measuring method for back drill processing, and measuring device |
| JP2019204877A (en) * | 2018-05-23 | 2019-11-28 | 日立化成株式会社 | Wiring board, manufacturing method of wiring board, and manufacturing method of electronic component element package |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS624880A (en) * | 1985-06-28 | 1987-01-10 | Nippon Kokan Kk <Nkk> | Surface treatment of galvanized or alloyed galvanized steel sheet |
| JPS63245995A (en) * | 1987-04-01 | 1988-10-13 | 株式会社 イ−スタン | Method of forming intermediate layer terminal of multilayer printed interconnection board |
| JPH06112659A (en) * | 1992-09-24 | 1994-04-22 | Nippondenso Co Ltd | Multilayer wiring board processor and processing method |
-
1994
- 1994-10-31 JP JP6267008A patent/JP2609825B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS624880A (en) * | 1985-06-28 | 1987-01-10 | Nippon Kokan Kk <Nkk> | Surface treatment of galvanized or alloyed galvanized steel sheet |
| JPS63245995A (en) * | 1987-04-01 | 1988-10-13 | 株式会社 イ−スタン | Method of forming intermediate layer terminal of multilayer printed interconnection board |
| JPH06112659A (en) * | 1992-09-24 | 1994-04-22 | Nippondenso Co Ltd | Multilayer wiring board processor and processing method |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1093251A (en) * | 1996-09-10 | 1998-04-10 | Airex:Kk | Method of machining multilayer printed board |
| KR100342845B1 (en) * | 1999-11-12 | 2002-07-10 | 박철호 | The equipment grinding system ang connestion of small size PCB bold |
| WO2002001928A1 (en) * | 2000-06-26 | 2002-01-03 | 3M Innovative Properties Company | Vialess printed circuit board |
| JP2006173146A (en) * | 2004-12-10 | 2006-06-29 | Hitachi Via Mechanics Ltd | Multilayer circuit board and method for manufacturing the same |
| JP4611010B2 (en) * | 2004-12-10 | 2011-01-12 | 日立ビアメカニクス株式会社 | Multilayer circuit board manufacturing method |
| JP2017135297A (en) * | 2016-01-29 | 2017-08-03 | ローランドディー．ジー．株式会社 | Processing device and processing method |
| JP2018018963A (en) * | 2016-07-28 | 2018-02-01 | ビアメカニクス株式会社 | Depth measuring method for back drill processing, and measuring device |
| JP2019204877A (en) * | 2018-05-23 | 2019-11-28 | 日立化成株式会社 | Wiring board, manufacturing method of wiring board, and manufacturing method of electronic component element package |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2609825B2 (en) | 1997-05-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6116955B2 (en) | Multi-layer printed wiring board back drilling method, drill therefor and board drilling device | |
| US20030178396A1 (en) | Automated trim processing system | |
| TWI554176B (en) | A device and a method for machining printed circuit boards | |
| JP2007509487A (en) | Closed loop back drilling system | |
| TW201605315A (en) | Backdrilling method, and backdrilling apparatus | |
| JP2016122825A (en) | Back drilling method and back drilling device | |
| JP2609825B2 (en) | Method for manufacturing multilayer wiring board | |
| JP4046058B2 (en) | Multilayer printed wiring board, stub counterboring device and method thereof | |
| JPH07285097A (en) | Device for punching printed circuit board,etc | |
| CN110893629B (en) | Method for manufacturing circuit board and drilling machine | |
| JP3286522B2 (en) | Printed circuit board processing equipment | |
| JPS61131804A (en) | Drilling method of spot facing of internal layer reference section in multilayer circuit substrate | |
| JPH054105A (en) | Working of hole on printed circuit board | |
| JPH1022643A (en) | Printed wiring board with cavity, its manufacture and its manufacturing equipment | |
| CN113079638B (en) | Back drilling method and device for PCB | |
| TWI680704B (en) | Back drilling method of circuit board | |
| JPH0715147A (en) | Method and device for forming blind hole of multilayer wiring board | |
| KR930012264B1 (en) | Grinding guide and method | |
| JP2777425B2 (en) | Method of manufacturing pin grid array having multi-stage bonding terminal structure, apparatus for cutting out inner layer terminal thereof, and multilayer substrate for pin grid array | |
| CN1816251B (en) | Method of forming periphery of substrate | |
| CN112770498B (en) | Circuit board processing method | |
| JPH08150599A (en) | Hole machining method of printed wiring board and hole machining device using the hole machining method of printed wiring board | |
| JPS5831422Y2 (en) | Semiconductor device assembly board | |
| JP3425251B2 (en) | Apparatus and method for cutting out inner layer circuit for electronic component package | |
| JPH01246011A (en) | Reference hole boring method for multilayer circuit board and device thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19961224 |
|
| LAPS | Cancellation because of no payment of annual fees |