JP2777425B2 - Method of manufacturing pin grid array having multi-stage bonding terminal structure, apparatus for cutting out inner layer terminal thereof, and multilayer substrate for pin grid array - Google Patents

Method of manufacturing pin grid array having multi-stage bonding terminal structure, apparatus for cutting out inner layer terminal thereof, and multilayer substrate for pin grid array

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Publication number
JP2777425B2
JP2777425B2 JP1265845A JP26584589A JP2777425B2 JP 2777425 B2 JP2777425 B2 JP 2777425B2 JP 1265845 A JP1265845 A JP 1265845A JP 26584589 A JP26584589 A JP 26584589A JP 2777425 B2 JP2777425 B2 JP 2777425B2
Authority
JP
Japan
Prior art keywords
inner layer
bonding terminal
work
eddy current
spindle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1265845A
Other languages
Japanese (ja)
Other versions
JPH03126235A (en
Inventor
隆次 小松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NIPPON MIKURON KK
Original Assignee
NIPPON MIKURON KK
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Application filed by NIPPON MIKURON KK filed Critical NIPPON MIKURON KK
Priority to JP1265845A priority Critical patent/JP2777425B2/en
Publication of JPH03126235A publication Critical patent/JPH03126235A/en
Application granted granted Critical
Publication of JP2777425B2 publication Critical patent/JP2777425B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01072—Hafnium [Hf]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing Of Electrical Connectors (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はボンディング端子が多段に構成されたピング
リッドアレーの製造方法に関し、更に詳しくは、内層側
のボンディング端子を座ぐり切削加工によって露出させ
ることによって、このような多段ボンディング端子構造
のピングリッドアレーを製造する方法に関するものであ
る。Description: FIELD OF THE INVENTION The present invention relates to a method for manufacturing a pin grid array in which bonding terminals are configured in multiple stages, and more particularly, to expose inner side bonding terminals by spot facing. Accordingly, the present invention relates to a method of manufacturing such a pin grid array having a multi-stage bonding terminal structure.

また、本発明は、このような製造方法に使用するのに
適したピングリッドアレーの内層ボンディング端子の削
り出し装置及びピングリッドアレー用多層基板に関する
ものである。Further, the present invention relates to a device for cutting an inner layer bonding terminal of a pin grid array suitable for use in such a manufacturing method and a multilayer substrate for a pin grid array.

〔従来の技術〕[Conventional technology]

近年においては、ICチップの高集積化及び多機能化に
伴って、これを搭載するICパッケージの側のピン数も多
く必要とされるようになってきている。ICパッケージの
一形式として利用されているピングリッドアレー（PG
A）は、このような多ピン化に対応できるものである。
ここに、このPGAにおいては、表面に表層ボンディング
端子回路を形成し、この端子回路の端子数を増加させる
ことによって多ピン化に対応できる。しかし、このよう
な平面１段のボンディング端子配列によって多ピン化に
対応するには限度がある。そのために、表面に形成した
表層ボンディング端子配列に加えて、基板内に内層ボン
ディング端子配列を形成し、このような多段の端子配列
構造を採用することによって、多ピン化に対応してい
る。In recent years, with higher integration and more functions of an IC chip, the number of pins on an IC package side on which the IC chip is mounted is also required to be larger. Pin grid array (PG) used as a type of IC package
A) can cope with such an increase in the number of pins.
Here, in this PGA, a surface bonding terminal circuit is formed on the surface, and by increasing the number of terminals of this terminal circuit, it is possible to cope with an increase in the number of pins. However, there is a limit in responding to the increase in the number of pins by the bonding terminal arrangement in one plane on such a plane. To this end, in addition to the surface bonding terminal arrangement formed on the surface, an inner layer bonding terminal arrangement is formed in the substrate, and such a multi-stage terminal arrangement structure is adopted to cope with the increase in the number of pins.

このような多段のボンディング端子配列構造のPGAの
製造は一般的に次の手順によって行われている。すなわ
ち、第３図（Ａ）に示すように、有機絶縁材などから成
る基材層１を用意し、この裏面には銅箔層２を形成し、
表面側には、その中央部分に位置するICチップ装着部３
の外周部分に内層ボンディング端子回路４を形成する。
また、上記のチップ装着部３よりも一回り大きな窓５が
開けられた銅箔層７のある表層材６を用意し、さらに、
上記の窓５と同一寸法の窓８が開けられたプリプレグあ
るいは接着シート９を用意し、この接着シート９を挟
み、上記の基材層１および表層材６を、内層ボンディン
グ端子回路４の端子部分4aが露出した状態に重ね合わせ
て接着する。このようにして、第３図（Ｂ）に示す断面
構造の積層基板10を構成する。この後は、積層基板10に
おけるチップ装着部３の外周位置に、格子状に、積層基
板を貫通して延びるピン挿通穴11を複数個開け、これら
の穴の内周面に銅メッキを施こす。しかる後に、表面の
銅箔層７をエッチングして、表層ボンデイング端子回路
12を形成した後に、この端子回路12の端子部分12aおよ
び内層側の端子部分4aに金メッキを施こし、また、裏面
側の銅箔層２をエッチングして回路パターンを形成す
る。そして、ピン13を装着することによって、第３図
（Ｃ）に示す２段の端子配列構造のPGAを構成する。こ
の後は、ICチップ装着部３にICチップが装着され、この
チップの外部端子と、PGAの側の２段の端子との間が金
線によってボンディングされることになる。The manufacture of such a PGA having a multi-stage bonding terminal arrangement structure is generally performed by the following procedure. That is, as shown in FIG. 3 (A), a base layer 1 made of an organic insulating material or the like is prepared, and a copper foil layer 2 is formed on the back surface thereof.
On the front side, the IC chip mounting part 3 located at the center
Is formed on the outer peripheral portion of the substrate.
In addition, a surface layer material 6 having a copper foil layer 7 having a window 5 slightly larger than the above-mentioned chip mounting portion 3 is prepared.
A prepreg or an adhesive sheet 9 having a window 8 of the same size as the above-mentioned window 5 is prepared. The adhesive sheet 9 is sandwiched, and the base layer 1 and the surface material 6 are connected to the terminal portion of the inner layer bonding terminal circuit 4. 4a is superposed and bonded in a state where it is exposed. Thus, the laminated substrate 10 having the sectional structure shown in FIG. 3 (B) is formed. Thereafter, a plurality of pin insertion holes 11 extending through the laminated substrate are formed in a lattice shape at the outer peripheral position of the chip mounting portion 3 in the laminated substrate 10, and copper plating is applied to the inner peripheral surfaces of these holes. . Thereafter, the copper foil layer 7 on the surface is etched to form a surface bonding terminal circuit.
After the formation of 12, the terminal portion 12a of the terminal circuit 12 and the terminal portion 4a on the inner layer side are plated with gold, and the copper foil layer 2 on the rear surface side is etched to form a circuit pattern. Then, by mounting the pins 13, a PGA having a two-stage terminal arrangement structure shown in FIG. 3C is formed. Thereafter, the IC chip is mounted on the IC chip mounting portion 3, and the external terminals of the chip and the two-stage terminals on the PGA side are bonded by gold wires.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

しかしながら、このように予めチップ装着部用の窓開
けをした表層材を、接着シートを用いて基材層の側に接
着することによって多段のボンディング端子配列を構成
する方法においては次にような問題点がある。However, the following problem arises in the method of forming a multi-stage bonding terminal array by bonding the surface layer material which has been opened in advance for the chip mounting portion to the side of the base material layer using an adhesive sheet. There is a point.

まず、積層基板を構成する場合に、基材層に対して接
着シートおよび表層材を正確に位置合わせしてこれらを
接着する必要があるが、このような位置合わせ作業は困
難である。また、正確に位置合わせされない状態で、基
材層と表層材とが接着されると、基材層の表面に形成し
た内層ボンディング端子回路の端子部分が必要とされる
長さだけ露出していない事態が発生する。First, when forming a laminated substrate, it is necessary to precisely position and bond the adhesive sheet and the surface layer material to the base material layer, but such a positioning operation is difficult. Also, when the base material layer and the surface material are bonded in a state where they are not accurately aligned, the terminal portion of the inner layer bonding terminal circuit formed on the surface of the base material layer is not exposed for a required length. Things happen.

また、基材層と表層材とは、これらの間の接着シート
を加熱溶融させて接着する訳であるが、この接着シート
を過度に溶融すると、溶融した接着シートの樹脂が、内
層端子部分にまで流れ出し、そこを覆った状態で固化す
るという弊害が発生する。これとは逆に、接着シートの
溶融不足が生ずると、基材層と表層材との間に接着剤が
充填されていない空隙部ができ、基材層の表面に形成し
た内層ボンディング端子回路を構成する回路パターン間
に接着剤の樹脂が充分に充填されない事態が発生する。
このような空隙部が存在すると、金メッキ処理の際に、
メッキ液がこれらの空隙部内に侵入し、内層ボンディン
グ端子回路の絶縁劣化などを引き起こすおそれがある。In addition, the base material layer and the surface layer material are bonded by heating and melting the adhesive sheet therebetween, but when the adhesive sheet is excessively melted, the resin of the molten adhesive sheet is applied to the inner layer terminal portion. Effluent, and solidify while covering it. Conversely, when the adhesive sheet is insufficiently melted, a gap is formed between the base material layer and the surface material that is not filled with the adhesive, and the inner layer bonding terminal circuit formed on the surface of the base material layer is formed. A situation occurs in which the resin of the adhesive is not sufficiently filled between the circuit patterns to be formed.
When such a gap exists, during the gold plating process,
There is a possibility that the plating solution may enter the gaps and cause the insulation deterioration of the inner layer bonding terminal circuit.

さらに、前述したように、内層ボンディング端子回路
の端子部分が露出した状態に積層基板を形成した後に、
この積層基板に対して、銅メッキやパターニングの形成
を行うようにしているので、これらの各作業工程におい
ては、露出している内層側の端子部分を保護する必要あ
る。このために、作業が困難となり、歩留りも低下する
傾向がある。Further, as described above, after forming the laminated substrate in a state where the terminal portion of the inner layer bonding terminal circuit is exposed,
Since copper plating and patterning are performed on the laminated substrate, it is necessary to protect the exposed inner layer side terminal portions in each of these working steps. For this reason, work becomes difficult, and the yield tends to decrease.

このように、従来の製造方法による場合には、製造価
格が高くなり、製品の信頼性も低いという問題点があ
る。As described above, according to the conventional manufacturing method, there is a problem that the manufacturing cost is high and the reliability of the product is low.

本発明の課題は、このような従来の製造方法の欠点に
鑑みて、予め窓開けした表層材を基材層の側に接着シー
トによって接着する工程を経ることなく、多段のボンデ
ィング端子配列構造を有するピングリッドアレーを製造
することの可能となった方法を提案することにある。ま
た、本発明の課題は、この新規な方法を実施するのに適
した製造装置及び基板を提案することにある。An object of the present invention is to provide a multi-stage bonding terminal array structure without passing through a step of bonding a window-opened surface layer material to a base material layer side with an adhesive sheet in view of the drawbacks of the conventional manufacturing method. It is an object of the present invention to propose a method capable of manufacturing a pin grid array having the same. Another object of the present invention is to propose a manufacturing apparatus and a substrate suitable for performing the novel method.

〔課題を解決するための手段〕[Means for solving the problem]

上記の課題を解決するために、本発明の多段のボンデ
ィング端子構造のピングリッドアレーの製造方法におい
ては、予め、絶縁層間に内層ボンディング端子回路が挟
まれた層構成の積層基板を用意し、この積層基板の表面
に表層ボンディング端子回路を形成した後に、積層基板
をその表面側からNCルータマシーンなどの工作機械を用
いて座ぐり加工して、内層ボンディング端子回路の端子
部分を露出させるようにしている。In order to solve the above problems, in the method of manufacturing a pin grid array having a multi-stage bonding terminal structure of the present invention, a laminated substrate having a layer configuration in which an inner layer bonding terminal circuit is sandwiched between insulating layers is prepared in advance. After forming the surface bonding terminal circuit on the surface of the laminated substrate, the laminated substrate is counterbored from the surface side using a machine tool such as an NC router machine so that the terminal portion of the inner layer bonding terminal circuit is exposed. I have.

ここに、工作機械を用いて内層ボンディング端子回路
の端子部分を削り出すように、積層基板全体の厚さを測
定して切削深さを算出する構成のNCルータマシーンが従
来から知られている。しかし、積層基板において、内層
ボンディング端子回路と表面に形成した表層ボンディン
グ端子回路との間の距離は、各積層基板毎に約±25μ〜
約±60μものばらつきがあり、これに対して内層ボンデ
ィング端子回路の層厚は約18μ〜70μと大変薄い。この
ため、従来の工作機械を使用して、一義的に切削深さを
設定し、この深さとなるように積層基板を切削したのみ
では、内層ボンディング端子回路まで正確に積層基板を
削り、しかも必要な厚さの内層ボンディング端子回路の
層厚を残すことができるような切削を常に期待すること
は不可能である。Here, there is conventionally known an NC router machine configured to measure the thickness of the entire laminated substrate and calculate the cutting depth so as to cut out the terminal portion of the inner layer bonding terminal circuit using a machine tool. However, in the laminated board, the distance between the inner layer bonding terminal circuit and the surface layer bonding terminal circuit formed on the surface is about ± 25 μ
There is a variation of about ± 60 μ, whereas the layer thickness of the inner bonding terminal circuit is very thin, about 18 μ to 70 μ. For this reason, by simply setting the cutting depth using a conventional machine tool and cutting the laminated board to this depth, the laminated board is accurately cut down to the inner layer bonding terminal circuit, and It is not possible to always expect a cutting that can leave a layer thickness of the inner layer bonding terminal circuit having a large thickness.

そこで、本発明の製造方法においては、積層基板の表
面側に高周波電流が印加された高さ検出用プローブを接
近させることによって、前記積層基板の内層ボンディン
グ端子回路等に渦電流を発生させ、前記積層基板の表層
側からこの発生した渦電流によって生ずる高周波磁界の
強さを測定し、その測定データに基づいて工作機械の主
軸を送って、この主軸の先端に支持された回転切削刃に
よって前記積層基板に対しての表層側から座ぐり切削加
工を施し、前記高周波磁界の変動に基づき、前記工作機
械の主軸の送り量を制御して、前記内層ボンディング端
子回路を露出させるようにしている。Therefore, in the manufacturing method of the present invention, an eddy current is generated in an inner layer bonding terminal circuit or the like of the laminated substrate by bringing a height detection probe to which a high-frequency current is applied close to the surface side of the laminated substrate. The strength of the high-frequency magnetic field generated by the generated eddy current is measured from the surface layer side of the laminated substrate, and the main shaft of the machine tool is fed based on the measured data, and the lamination is performed by the rotary cutting blade supported at the tip of the main shaft. A counterbore cutting process is performed on the substrate from the surface layer side, and the inner-layer bonding terminal circuit is exposed by controlling the feed amount of the main shaft of the machine tool based on the fluctuation of the high-frequency magnetic field.

また、本発明における上記の製造方法に用いる内層ボ
ンディング端子の削り出し装置は、主軸支持機構に支持
された座ぐり用回転切削刃と、この主軸支持機構に対し
てその主軸の送り方向に向けて移動可能のプローブと、
このプローブに高周波電流を印加して、被切削部下又は
その近傍に渦電流を発生させる渦電流発生手段と、発生
した渦電流による高周波磁界の強さを検出する検出手段
と、検出された高周波磁場に基づき前記回転切削刃と前
記被切削部との距離を算出し、この算出値に基づき前記
主軸の送り量を制御する送り制御手段とを有することを
特徴としている。Further, the apparatus for cutting out the inner layer bonding terminal used in the above manufacturing method of the present invention includes a counterbore rotary cutting blade supported by a spindle support mechanism and a feed direction of the spindle with respect to the spindle support mechanism. A movable probe,
An eddy current generating means for applying a high-frequency current to the probe to generate an eddy current below or near the cut portion, a detecting means for detecting the strength of the high-frequency magnetic field due to the generated eddy current, and a detected high-frequency magnetic field And a feed control means for calculating a distance between the rotary cutting blade and the portion to be cut based on the calculated value, and controlling a feed amount of the spindle based on the calculated value.

絶縁層の厚さを測定するために、渦電流の発生が必須
であるが、渦電流の発生する導電部として内層ボンディ
ング端子回路自体を利用できるものの、回路配線が極細
であることから効果的な渦電流の発生を期待しにくい。
そこで、内層ボンディング端子回路形成面上においてこ
の回路に対して孤立的ないし島状に形成された１又は２
以上の渦電流発生用導電層を予め備えたピングリッドア
レー用多層基板を使用することで、高精度の削り出しが
実現される。In order to measure the thickness of the insulating layer, it is necessary to generate an eddy current.However, although the inner layer bonding terminal circuit itself can be used as the conductive part where the eddy current is generated, it is effective because the circuit wiring is extremely fine. It is difficult to expect generation of eddy current.
Therefore, on the inner layer bonding terminal circuit forming surface, 1 or 2 formed in an isolated or island shape with respect to this circuit.
By using the multi-layer substrate for the pin grid array provided with the above-mentioned conductive layer for eddy current generation in advance, high-precision shaving is realized.

〔作用〕[Action]

本発明の方法および装置においては、積層基板の表面
にプローブが近接配置されて、このプローブに高周波電
流が印加される。プローブに高周波電流が印加される
と、積層基板の側の内層ボンディング端子回路等に渦電
流が発生する。この渦電流により高周波磁界が発生す
る。ここに、この高周波磁界は、内層ボンディング端子
回路から積層基板表面までの絶縁膜厚に応じて異なる。
従って、上記のプローブの先端で測定された高周波磁界
の強さに基づき、このプローブ先端から積層基板の内層
ボンディング端子回路までの距離が算出される。よっ
て、主軸方向に送られる回転切削刃の先端位置から積層
基板の内層ボンディング端子回路までの距離も算出され
る。この場合における算出された距離の精度誤差は約５
μ未満の小さな量である。この算出された距離に基づ
き、回転切削刃の主軸方向の送り量が制御されながら、
この回転切削刃によって積層基板の表層材が座ぐりさ
れ、内層ボンディング端子回路の端子部分が削り出され
る。In the method and the apparatus according to the present invention, a probe is arranged close to the surface of the laminated substrate, and a high-frequency current is applied to the probe. When a high-frequency current is applied to the probe, an eddy current is generated in the inner layer bonding terminal circuit and the like on the side of the laminated substrate. This eddy current generates a high-frequency magnetic field. Here, the high-frequency magnetic field varies depending on the insulating film thickness from the inner layer bonding terminal circuit to the surface of the laminated substrate.
Therefore, based on the strength of the high-frequency magnetic field measured at the tip of the probe, the distance from the tip of the probe to the inner layer bonding terminal circuit of the laminated substrate is calculated. Therefore, the distance from the tip position of the rotary cutting blade sent in the main axis direction to the inner layer bonding terminal circuit of the laminated substrate is also calculated. In this case, the accuracy error of the calculated distance is about 5
It is a small amount less than μ. Based on the calculated distance, the feed amount of the rotary cutting blade in the main spindle direction is controlled,
The surface material of the laminated substrate is spotted by the rotary cutting blade, and the terminal portion of the inner bonding terminal circuit is cut out.

このようにして、本例の製造方法および装置によれ
ば、約５μ未満の高精度で積層基板の座ぐりを行うこと
ができ、従って、内層ボンディング端子の端子部分を、
必要な層厚を有する状態で削り出すことができる。In this manner, according to the manufacturing method and apparatus of the present example, it is possible to perform the counterbore of the laminated substrate with high accuracy of less than about 5 μm.
It can be cut out with the required layer thickness.

〔実施例〕〔Example〕

以下、図面を参照して本発明の実施例を説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

第１図には本発明の製造方法に用いるのに適した削り
出し装置の全体構成を示してある。この装置21は、一般
的に知られてるNCルータマシーンから構成されており、
図においては、本発明に関係のある主要部分の構成のみ
を示してある。図において、22は主軸であり、この主軸
22の基端側には主軸モータ23が連結されており、このモ
ータの回転によって、主軸22はその軸線方向、すなわち
Ｚ軸方向に向けて往復移動される。この主軸の先端に
は、チャックを介して回転切削刃であるルータ刃（超硬
又はダイヤモンド）24が固着されており、このルータ刃
は不図示の駆動モータによって回転駆動することによっ
て、ワーク31の被切削領域32の座ぐり加工が行われるよ
うになっている。FIG. 1 shows the entire configuration of a cutting device suitable for use in the manufacturing method of the present invention. This device 21 is composed of a generally known NC router machine,
In the figure, only the configuration of the main parts related to the present invention is shown. In the figure, reference numeral 22 denotes a spindle, and this spindle is
A spindle motor 23 is connected to the base end side of the spindle 22, and the rotation of the motor causes the spindle 22 to reciprocate in its axial direction, that is, in the Z-axis direction. A router blade (carbide or diamond) 24, which is a rotary cutting blade, is fixed to the tip of the main shaft via a chuck, and the router blade is rotated by a drive motor (not shown) to rotate the work 31. Counterboring of the area to be cut 32 is performed.

ここに、ワーク31は、表層ボンディング端子および内
層ボンディング端子を備えた多段端子配列構造のPGA基
板である。このPGA基板は、本例の装置21によって、そ
の表層側の中央部に矩形の凹部を形成するようになって
いる。凹部が形成された後は、この凹部にICチップが装
着され、しかる後に、チップの外部端子とPCA基板の側
の表層および内層ボンディング端子とがボンディングさ
れる。Here, the work 31 is a PGA substrate having a multi-stage terminal arrangement structure including a surface layer bonding terminal and an inner layer bonding terminal. In this PGA substrate, a rectangular concave portion is formed in the central portion on the surface layer side by the device 21 of the present example. After the concave portion is formed, the IC chip is mounted in the concave portion, and thereafter, the external terminal of the chip is bonded to the surface layer and the inner layer bonding terminal on the side of the PCA substrate.

次に、上記のルータ刃24の隣接位置にはプローブ41が
設置されている。このプローブ41は、ブラケット42を以
て主軸支持機構30に取付けたサーボ機構30aに対し昇降
可能に支持されている。つまり、プローブ41は主軸と平
行に配列され、ルータ刃24と同様に、主軸方向に移動さ
れるようになっている。Next, a probe 41 is installed at a position adjacent to the router blade 24 described above. The probe 41 is supported by a bracket 42 so as to be able to move up and down with respect to a servo mechanism 30a attached to the spindle support mechanism 30. That is, the probes 41 are arranged in parallel with the main axis, and like the router blade 24, are moved in the main axis direction.

すなわち、高さ測定時にはルータ刃24を上昇させると
共に、プローブ41を下降させて測定し、切削時にはプロ
ーブ41を上昇させると共に、ルータ刃24を下降させてこ
れで切削する。なお、プローブ41の高さ位置を一定にし
てプローブ先端から内層銅箔までの位置を測定すること
によって内層銅箔の高さ絶縁値を算出する方法と、プロ
ーブ41を表層に接するまで下降し絶縁層の厚さを測定
し、内層銅箔の高さ絶対値を算出する方法とがある。That is, when measuring the height, the router blade 24 is raised and the probe 41 is moved down for measurement, and when cutting, the probe 41 is raised and the router blade 24 is moved down for cutting. In addition, a method of calculating the height insulation value of the inner copper foil by measuring the position from the probe tip to the inner copper foil while keeping the height position of the probe 41 constant, and lowering and insulating the probe 41 until it comes into contact with the surface layer There is a method of measuring the thickness of the layer and calculating the absolute value of the height of the inner layer copper foil.

このプローブ41は、高周波電流発生源43によって高周
波電流を印加可能であり、ここに高周波電流を印加する
ことによって、ワーク31の側に形成された導電層である
内層ボンディング端子回路に渦電流が発生する。また、
このプローブ41は、渦電流によって生じたワーク被切削
領域上の高周波磁界の強さを電流値の変化として検出す
るための検出端子としても機能する。このプローブ41に
よって検出された高周波磁界による電流は、抵抗44の両
端から電圧値として検出され、この電圧値が入力処理回
路51に供給されるようになっている。入力処理回路51に
入力された電圧は、ここで増幅およびデジタル化され、
入力インターフェース52を介して中央処理装置（CPU）5
3に供給される。CPU53においては、供給されたデジタル
信号に基づき、予め固定記憶装置（ROM）54内に格納さ
れているルックアップテーブルから、ルータ刃24の先端
位置からワーク31内の導電層までの距離を算出する。算
出された値に基づき、主軸の送り量が算出され、この算
出値は、主軸の送り制御信号として、このCPU53から出
力インターフェース55を介して駆動回路56に出力され
る。この駆動回路56では、主軸の送り制御信号に基づ
き、主軸送りモータ23を駆動して、主軸先端に支持され
ているルータ刃24を一定の距離だけワークの側あるいは
その反対方向に向けて送る。The probe 41 can apply a high-frequency current by a high-frequency current generation source 43. By applying the high-frequency current to the probe 41, an eddy current is generated in the inner bonding terminal circuit, which is a conductive layer formed on the work 31 side. I do. Also,
The probe 41 also functions as a detection terminal for detecting the intensity of the high-frequency magnetic field on the workpiece cutting region caused by the eddy current as a change in current value. The current due to the high-frequency magnetic field detected by the probe 41 is detected as a voltage value from both ends of the resistor 44, and this voltage value is supplied to the input processing circuit 51. The voltage input to the input processing circuit 51 is amplified and digitized here,
Central processing unit (CPU) 5 via input interface 52
Supplied to 3. The CPU 53 calculates the distance from the position of the tip of the router blade 24 to the conductive layer in the work 31 from a look-up table stored in advance in a fixed storage device (ROM) 54 based on the supplied digital signal. . The feed amount of the spindle is calculated based on the calculated value, and the calculated value is output from the CPU 53 to the drive circuit 56 via the output interface 55 as a feed control signal of the spindle. In the drive circuit 56, the spindle feed motor 23 is driven based on the feed control signal of the spindle, and the router blade 24 supported at the tip of the spindle is sent a fixed distance toward the work or in the opposite direction.

次に、第２図を参照して、上記構成の削り出し装置を
用いて、多段のボンディング端子を持ったPGA基板の製
造方法を説明する。Next, with reference to FIG. 2, a method of manufacturing a PGA substrate having a multi-stage bonding terminal using the above-described scraping device will be described.

まず、ワーク31であるPGA基板として、絶縁層間に内
層ボンディング端子回路が形成された層構成の積層基板
を製造する。すなわち、第２図（Ａ）に示すように、基
材層61と表層材66との間に内層ボンディング端子回路64
が形成された積層基板31を製造する。次に、この積層基
板31の表面に表層ボンディング端子回路用の銅箔層67を
形成すると共に、裏面にも銅箔層62を形成する。ここ
に、内層ボンディング端子回路64は、中央部分に矩形の
窓64aが開けられており、この窓64aの外周縁に面してい
る部分が、内層ボンディング端子64bとされる。本例に
おいては、この窓64aの中心部分には、他の内層ボンデ
ィング端子回路部分とは孤立した渦電流発生領域たるタ
ーゲット導電層64cを形成してある。First, as a PGA substrate serving as the work 31, a laminated substrate having a layer configuration in which an inner layer bonding terminal circuit is formed between insulating layers is manufactured. That is, as shown in FIG. 2A, the inner bonding terminal circuit 64 is provided between the base material layer 61 and the surface material 66.
The laminated substrate 31 on which is formed is manufactured. Next, a copper foil layer 67 for a surface layer bonding terminal circuit is formed on the surface of the laminated substrate 31, and a copper foil layer 62 is also formed on the back surface. Here, in the inner layer bonding terminal circuit 64, a rectangular window 64a is opened in a central portion, and a portion facing the outer peripheral edge of the window 64a is used as an inner layer bonding terminal 64b. In the present example, a target conductive layer 64c, which is an eddy current generation region isolated from other inner layer bonding terminal circuit portions, is formed at the center of the window 64a.

次に、第２図（Ｂ）に示すように、積層体31に、ピン
装着用のスルーホール71を開け、この内周面に銅メッキ
（スルホールメッキ）を施す。この後、表面側の銅箔層
67をエッチングして、表層ボンディング端子回路67aを
形成すると共に、裏面側の銅箔層62もエッチングして回
路パターンを形成する。形成された表層ボンディング端
子回路67aは、その中央位置に矩形の窓67bが開いている
回路パターンとなっており、この窓67bの外周縁に面し
ている部分が表層ボンディング端子67cとされる。ここ
に、この窓67bは上記の内層ボンディング端子回路に形
成された窓64aよりも一回り大きな寸法に設定されてい
る。Next, as shown in FIG. 2 (B), through holes 71 for mounting pins are formed in the laminate 31 and copper plating (through hole plating) is applied to the inner peripheral surface thereof. After this, the copper foil layer on the front side
The surface bonding terminal circuit 67a is formed by etching the 67, and the copper foil layer 62 on the back side is also etched to form a circuit pattern. The formed surface bonding terminal circuit 67a has a circuit pattern in which a rectangular window 67b is opened at the center thereof, and a portion facing the outer peripheral edge of the window 67b is a surface bonding terminal 67c. Here, the size of the window 67b is set to be slightly larger than the size of the window 64a formed in the inner layer bonding terminal circuit.

次に、プローブ41の先端41aが積層体31の中央直上の
位置となるように設定する。この状態で、プローブ41に
対して高周波電流を印加すると、これによって、積層体
内部のターゲット導電層64cに渦電流が発生する。この
渦電流によって発生する高周波磁界がプローブ41によっ
て検出され、検出された高周波磁界の強さに対応する電
圧値が、デジタル量としてCPU53に入力される。CPU53で
は、前述したように入力されたデジタル値に基づき、プ
ローブ先端41aからターゲット導線層64cまでの距離を算
出する。ここに、プローブ先端41aとルータ刃先端まで
の距離は常に同じ支持機構30によって保持されているの
で、この算出された距離に基づき、積層基板31の表面か
らターゲット導電層64cまでの距離が算出できる。Next, the tip 41a of the probe 41 is set so as to be located immediately above the center of the multilayer body 31. When a high-frequency current is applied to the probe 41 in this state, an eddy current is generated in the target conductive layer 64c inside the multilayer body. The high-frequency magnetic field generated by the eddy current is detected by the probe 41, and a voltage value corresponding to the strength of the detected high-frequency magnetic field is input to the CPU 53 as a digital value. The CPU 53 calculates the distance from the probe tip 41a to the target conductive layer 64c based on the digital value input as described above. Here, since the distance between the probe tip 41a and the router blade tip is always held by the same support mechanism 30, the distance from the surface of the laminated substrate 31 to the target conductive layer 64c can be calculated based on the calculated distance. .

このようにしてルータ刃先端からターゲット導電層64
cまでの距離を測定した後に、ルータ刃24による座ぐり
加工を行う。In this way, the target conductive layer 64
After measuring the distance to c, counterboring with the router blade 24 is performed.

従って、座ぐりの深さは、丁度この内層ボンディング
端子64bが露出した位置までとなるように正確に制御で
きる。Accordingly, the depth of the counterbore can be accurately controlled so as to reach just the position where the inner layer bonding terminal 64b is exposed.

この後は、第２図（Ｄ）に示すように、内層ボンディ
ング端子回路の窓64aの内側部分を一定の深さに座ぐ
り、ICチップの装着用凹部61aを形成する。この場合の
座ぐりにおいては、ターゲット導電層も合わせて削られ
る。しかし、内層ボンディング端子64bが露出した後
は、それほど正確な座ぐりの深さ制御は必要とされない
ので、従来一般的に行われている制御態様で座ぐりの深
さ制御を行えばよい。Thereafter, as shown in FIG. 2 (D), the inside portion of the window 64a of the inner layer bonding terminal circuit is seated at a certain depth to form a recess 61a for mounting an IC chip. In the spot facing in this case, the target conductive layer is also cut together. However, after the inner bonding terminal 64b is exposed, it is not necessary to control the counterbore depth so accurately, so that the counterbore depth control may be performed in a control mode generally performed conventionally.

次に、座ぐり加工が終了した後は、表層ボンディング
端子67cおよび内層ボンディング端子回路64bに金メッキ
を施こす。このようにして、多段のボンディング端子を
有するPGA基板が形成される。この後は、ICチップ74を
装着して、その外部端子と、上記の基板側の端子とが金
線によってボンディングされることになる。Next, after the counterbore processing is completed, the surface layer bonding terminal 67c and the inner layer bonding terminal circuit 64b are plated with gold. In this way, a PGA substrate having multi-stage bonding terminals is formed. Thereafter, the IC chip 74 is mounted, and the external terminals and the terminals on the substrate are bonded by gold wires.

他の実施態様 なお、上記の例においては、PGA基板の座ぐり加工の
場合を説明したが、本発明の削り出し装置は、その他の
多層板において内部に形成された回路部分を露出させる
ための使用することができる。また、ブラインドホール
の穴開け加工にも使用することができる。要するに、本
発明の削り出し装置は、正確な深さの削り加工が必要な
場合に適用することができる。Other Embodiments In the above example, the case of counterbore processing of the PGA substrate was described, but the cutting device of the present invention is used for exposing a circuit portion formed inside other multilayer boards. Can be used. It can also be used for drilling blind holes. In short, the shaving apparatus of the present invention can be applied to the case where shaving at an accurate depth is required.

また、上記の例においては、ワークとしてのPGA基板
には、ターゲット導電層64cを予め配置したものを使用
したが、このような導電層64cを使用しない場合であっ
ても、PGA基板の内層ボンディング端子回路に生ずる過
電流に基づき削り深さの制御を行うこともできる。Further, in the above example, the PGA substrate as the work used was a substrate in which the target conductive layer 64c was previously arranged, but even when such a conductive layer 64c was not used, the inner layer bonding of the PGA substrate was performed. The cutting depth can be controlled based on the overcurrent generated in the terminal circuit.

なお、このような測定プローブと削り刃用主軸を何組
も備え各軸毎に高さ制御できる多軸削り出し装置を構成
できることは云う迄もない。It goes without saying that a multi-axis shaving apparatus can be constructed which has a number of sets of such a measuring probe and a main shaft for the shaving blade and can control the height for each axis.

〔発明の効果〕〔The invention's effect〕

以上説明したように、本発明においては、予め内層ボ
ンディング端子回路が形成されたPGA積層基板を座ぐり
加工を施して、その内層ボンディング端子を露出させる
ようにすると共に、その座ぐり加工に当たっては、高周
波電流が印加されたプローブを積層基板に接近させて、
この基板内の内層ボンディング端子回路部分に発生した
渦電流による高周波磁界の強さを測定し、この測定値に
基づき座ぐり深さを制御している。従って、従来のよう
に予め窓開けをした表層材を接着剤を介して基材層に重
ねることによって多段のボンディング端子を形成する方
法に比べて、積層時の位置合わせ作業が不要となり、ま
た接着材の過剰溶融あるいは溶融不足に起因した弊害は
発生しない。As described above, in the present invention, a counterboring process is performed on a PGA laminated substrate on which an inner layer bonding terminal circuit is formed in advance, so that the inner layer bonding terminals are exposed, and in the counterboring process, Move the probe to which the high-frequency current is applied close to the laminated substrate,
The strength of the high-frequency magnetic field due to the eddy current generated in the inner bonding terminal circuit portion in the substrate is measured, and the spot facing depth is controlled based on the measured value. Therefore, compared to the conventional method of forming a multi-stage bonding terminal by laminating a surface layer material that has been previously opened with a window on a base material layer with an adhesive, the positioning work at the time of lamination becomes unnecessary, and bonding No adverse effects due to excessive melting or insufficient melting of the material occur.

また、本発明によれば、従来の座ぐり深さの制御方法
と比べて、正確に積層基板内の内層ボンディング端子回
路の位置を測定できるので、この内層ボンディング端子
部分を適正な状態に露出させることができる。Further, according to the present invention, since the position of the inner layer bonding terminal circuit in the laminated substrate can be accurately measured as compared with the conventional counterbore depth control method, the inner layer bonding terminal portion is exposed in an appropriate state. be able to.

さらに、本発明によれば、上記のPGA積層基板の座ぐ
り加工に留まらず、導電層部分を有するワークの座ぐ
り、ブラインドホールの穴開け加工などを精度良く行う
ことができるという効果が得られる。Further, according to the present invention, it is possible to obtain not only the above-described counterboring of the PGA laminated substrate, but also the effect that the counterboring of the work having the conductive layer portion and the boring of the blind hole can be performed with high accuracy. .

【図面の簡単な説明】[Brief description of the drawings]

第１図は本発明の一実施例に係る削り出し装置の主要構
成を示す概略ブロック図、第２図（Ａ）ないし（Ｄ）は
第１図の装置を用いたPGA積層基板の製造方法の各工程
をそれぞれ説明するための断面図、第３図（Ａ）ないし
（Ｃ）は従来のPGA積層基板の製造方法を示す断面図で
ある。 〔符号の説明〕 21……削り出し装置 22……主軸 24……ルータ刃 30……主軸支持機構 31……ワーク（PGA積層基板） 41……プローブ 43……高周波電流発生源 53……CPU 54……ROM 61……基材層 64……内層ボンティング端子回路 64a……窓部分 64b……内層ボンディング端子 64c……ターゲット導電層 66……表層材 67a……表層ボンディング端子回路 67b……窓部分 67c……表層ボンディング端子 71……スルーホール 73……ピン。FIG. 1 is a schematic block diagram showing a main configuration of a cutting apparatus according to one embodiment of the present invention, and FIGS. 2 (A) to 2 (D) show a method of manufacturing a PGA laminated substrate using the apparatus of FIG. FIG. 3A to FIG. 3C are cross-sectional views illustrating a conventional method for manufacturing a PGA laminated substrate. [Explanation of Signs] 21: Cutting machine 22: Spindle 24: Router blade 30: Spindle support mechanism 31: Work (PGA laminated board) 41: Probe 43: High-frequency current source 53: CPU 54 ROM 61 Base layer 64 Inner bonding terminal circuit 64a Window part 64b Inner bonding terminal 64c Target conductive layer 66 Surface material 67a Surface bonding terminal circuit 67b Window 67c Surface bonding terminal 71 Through hole 73 Pin.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｈ０１Ｌ 23/12 Ｎ ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 6 Identification code FI H01L 23/12 N

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】絶縁層間に内層ボンディング端子回路が挟
まれた層構成の積層基板を形成し、この積層基板の表面
に表層ボンディング端子回路を形成し、前記積層基板の
表面側に高周波電流が印加された高さ検出用プローブを
接近させることによって、前記積層基板の内層ボンディ
ング端子回路等に渦電流を発生させ、前記積層基板の表
層側からこの発生した渦電流によって生ずる高周波磁界
の強さを測定し、その測定データに基づいて主軸の先端
に支持された回転切削刃によって前記積層基板に対して
その表層側から座ぐり切削加工を施し、前記内層ボンデ
ィング端子回路を露出させるようにすることを特徴とす
る多段ボンディング端子構造のピングリットアレーの製
造方法。1. A laminated substrate having a layer structure in which an inner layer bonding terminal circuit is sandwiched between insulating layers, a surface layer bonding terminal circuit is formed on the surface of the laminated substrate, and a high-frequency current is applied to the surface side of the laminated substrate. By bringing the height detection probe approached, an eddy current is generated in the inner layer bonding terminal circuit and the like of the laminated substrate, and the intensity of a high-frequency magnetic field generated by the generated eddy current from the surface layer side of the laminated substrate is measured. Then, based on the measurement data, a counterbore cutting process is performed on the laminated substrate from the surface side thereof by a rotary cutting blade supported at the tip of the main shaft, so that the inner layer bonding terminal circuit is exposed. A method for manufacturing a pinglit array having a multi-stage bonding terminal structure. 【請求項２】請求項第１項に記載の方法に用いる前記内
層ボンディング端子の削り出し装置であって、 この削り出し装置は、主軸支持機構に支持された座ぐり
用回転切削刃と、この主軸支持機構に対してその主軸の
送り方向に向けて移動可能のプローブと、このプローブ
に高周波電流を印加して、前記内層ボンディング端子回
路等に渦電流を発生させる渦電流発生手段と、発生した
渦電流による高周波磁界を検出する検出手段と、検出さ
れた高周波磁界の強さに基づき前記回転切削刃と前記被
切削部との距離を算出し、この算出値に基づき前記主軸
の送り量を制御する送り制御手段とを有することを特徴
とするピングリッドアレーの内層ボンディング端子の削
り出し装置。2. An apparatus for cutting the inner layer bonding terminal used in the method according to claim 1, wherein the cutting apparatus comprises a counterbore rotary cutting blade supported by a spindle support mechanism; A probe movable with respect to the spindle support mechanism in the feed direction of the spindle, an eddy current generating means for applying a high-frequency current to the probe to generate an eddy current in the inner layer bonding terminal circuit and the like; Detecting means for detecting a high-frequency magnetic field due to eddy current; calculating a distance between the rotary cutting blade and the cut portion based on the strength of the detected high-frequency magnetic field; and controlling a feed amount of the main spindle based on the calculated value. And a feed control means for cutting the inner layer bonding terminals of the pin grid array. 【請求項３】少なくとも内層の一部に導電層が形成され
ているワークに対して削り加工を施すための削り出し方
法において、前記ワークの表面側に高周波電流が印加さ
れて高さ検出用プローブを接近させることによって、前
記導電層に渦電流が発生させ、前記ワークの表面側か
ら、この発生した渦電流によって生ずる高周波磁界の強
さを測定し、その測定データに基づいて、ワーク削り出
し装置の主軸先端に支持された回転切削刃と前記ワーク
の導電層との距離を算出し、この算出値に基づき、前記
主軸の送り量を制御して、前記回転切削刃によって前記
ワークに対してその表面側から削り加工を施すことを特
徴とする導電層を備えたワークの削り出し方法。3. A shaving method for shaving a work in which a conductive layer is formed on at least a part of an inner layer, wherein a high-frequency current is applied to a surface side of the work, and a height detecting probe is provided. , An eddy current is generated in the conductive layer, the strength of a high-frequency magnetic field generated by the generated eddy current is measured from the surface side of the work, and based on the measured data, a work shaving device is used. The distance between the rotary cutting blade supported at the spindle tip and the conductive layer of the work is calculated, and based on the calculated value, the feed amount of the main spindle is controlled, and the rotary cutting blade controls the feed amount for the work. A method for shaving a work having a conductive layer, characterized by shaving from the front side. 【請求項４】請求項第３項に記載の方法を用いる前記ワ
ークの削り出し装置であって 少なくとも内層の一部に導電層が形成されているワーク
に対して削り加工を施すための削り出し装置であって、
この削り出し装置は、主軸支持機構に支持された回転切
削刃と、この主軸支持機構に対してその主軸の送り方向
に向けて移動可能のプローブと、このプローブに高周波
電流を印加して前記ワークの導電層に渦電流を発生させ
るための高周波電流印加手段と、前記ワークの導電層に
発生した渦電流による高周波磁界の強さを検出する検出
手段と、検出された高周波磁界の強さに基づき前記回転
切削刃と前記ワークの導電層との距離を算出し、この算
出値に基づき前記主軸の送り量を制御する送り制御手段
とを有することを特徴とする導電層を備えたワークの削
り出し装置。4. An apparatus for cutting out a workpiece using the method according to claim 3, wherein the workpiece is provided with a conductive layer on at least a part of an inner layer. A device,
The shaving apparatus includes a rotary cutting blade supported by a spindle support mechanism, a probe movable in a feed direction of the spindle with respect to the spindle support mechanism, and applying a high-frequency current to the probe to apply the workpiece to the workpiece. A high-frequency current applying means for generating an eddy current in the conductive layer, a detecting means for detecting the strength of the high-frequency magnetic field due to the eddy current generated in the conductive layer of the work, and Cutting a work having a conductive layer, comprising: a feed control unit that calculates a distance between the rotary cutting blade and the conductive layer of the work, and controls a feed amount of the spindle based on the calculated value. apparatus.
JP1265845A 1989-10-12 1989-10-12 Method of manufacturing pin grid array having multi-stage bonding terminal structure, apparatus for cutting out inner layer terminal thereof, and multilayer substrate for pin grid array Expired - Fee Related JP2777425B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1265845A JP2777425B2 (en) 1989-10-12 1989-10-12 Method of manufacturing pin grid array having multi-stage bonding terminal structure, apparatus for cutting out inner layer terminal thereof, and multilayer substrate for pin grid array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1265845A JP2777425B2 (en) 1989-10-12 1989-10-12 Method of manufacturing pin grid array having multi-stage bonding terminal structure, apparatus for cutting out inner layer terminal thereof, and multilayer substrate for pin grid array

Publications (2)

Publication Number Publication Date
JPH03126235A JPH03126235A (en) 1991-05-29
JP2777425B2 true JP2777425B2 (en) 1998-07-16

Family

ID=17422871

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1265845A Expired - Fee Related JP2777425B2 (en) 1989-10-12 1989-10-12 Method of manufacturing pin grid array having multi-stage bonding terminal structure, apparatus for cutting out inner layer terminal thereof, and multilayer substrate for pin grid array

Country Status (1)

Country Link
JP (1) JP2777425B2 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61125715A (en) * 1984-11-26 1986-06-13 Matsushita Electric Works Ltd Method for detecting hole mark position on multi-layer printing wiring board
JPS61136710A (en) * 1984-12-03 1986-06-24 Matsushita Electric Works Ltd Manufacturing method of substrate for multi-layer printed circuit

Also Published As

Publication number Publication date
JPH03126235A (en) 1991-05-29

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