JPH06338536A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06338536A JPH06338536A JP5127626A JP12762693A JPH06338536A JP H06338536 A JPH06338536 A JP H06338536A JP 5127626 A JP5127626 A JP 5127626A JP 12762693 A JP12762693 A JP 12762693A JP H06338536 A JPH06338536 A JP H06338536A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- semiconductor device
- metal layer
- semiconductor chip
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、金属バンプを使用して
インナー部を半導体チップのパッドに接続し、はんだを
使用してアウター部を半導体装置実装基板の端子に接続
する半導体装置のリードに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead of a semiconductor device in which a metal bump is used to connect an inner part to a pad of a semiconductor chip and a solder is used to connect an outer part to a terminal of a semiconductor device mounting substrate. .
【０００２】[0002]
【従来の技術】図４は半導体チップを樹脂封止した半導
体装置の側断面図、図５は半導体チップをキャリアテー
プに搭載したテープキャリアパッケージの斜視図であ
る。2. Description of the Related Art FIG. 4 is a side sectional view of a semiconductor device in which a semiconductor chip is resin-sealed, and FIG. 5 is a perspective view of a tape carrier package in which the semiconductor chip is mounted on a carrier tape.
【０００３】図４において、表面実装型半導体装置１の
半導体チップ２は、金属バンプ４を介してリード５のイ
ンナー部を半導体チップ２のパッドに接続した後、樹脂
パッケージ３により封止される。In FIG. 4, the semiconductor chip 2 of the surface-mounted semiconductor device 1 is sealed with a resin package 3 after connecting the inner portion of the lead 5 to the pad of the semiconductor chip 2 via the metal bump 4.
【０００４】リード５の表面には、表面の安定化，金属
バンプ４との接着力確保および回路基板に対する実装の
ため、はんだまたはすずをめっきした金属層 (図６(イ)
参照）６が、厚さ１μm 程度に被着されている。A metal layer plated with solder or tin is formed on the surface of the lead 5 in order to stabilize the surface, to secure the adhesive force with the metal bump 4 and to mount it on the circuit board (see FIG. 6A).
6) is deposited to a thickness of about 1 μm.
【０００５】図中において10は、リード５の固定および
樹脂 (パッケージ３）の流れ止め用であり、リード５の
形成過程に際して使用したポリイミドフィルムの一部を
利用する。In the figure, reference numeral 10 is for fixing the lead 5 and for preventing the resin (package 3) from flowing, and utilizes a part of the polyimide film used in the process of forming the lead 5.
【０００６】図５において、テープキャリアパッケージ
（半導体装置）７は、リード５を可撓性絶縁テープ（一
般にポリイミドテープ）８に貼着したキャリアテープに
半導体チップ（図示せず）を搭載し、該半導体チップを
樹脂パッケージ３内に封入したのち、ポリイミドテープ
８のリード貼着面に、保護膜（ソルダーレジスト）９を
被着してなる。In FIG. 5, a tape carrier package (semiconductor device) 7 has a semiconductor chip (not shown) mounted on a carrier tape in which leads 5 are attached to a flexible insulating tape (generally a polyimide tape) 8. After encapsulating the semiconductor chip in the resin package 3, a protective film (solder resist) 9 is adhered to the lead adhering surface of the polyimide tape 8.
【０００７】一般に、ポリイミドテープ８の厚さは0.12
mm程度であり、スクリーン印刷による保護膜９の厚さは
0.２μm 〜0.６μm 程度である。Generally, the thickness of the polyimide tape 8 is 0.12.
mm, and the thickness of the protective film 9 formed by screen printing is
It is about 0.2 μm to 0.6 μm.
【０００８】[0008]
【発明が解決しようとする課題】図６は従来技術の問題
点の説明図であり、(イ),(ロ) は図４に示す半導体装置の
問題点の説明図、(ハ) は図５に示すテープキャリアパッ
ケージの問題点の説明図である。FIG. 6 is an explanatory view of the problems of the prior art, (a) and (b) are explanatory views of the problems of the semiconductor device shown in FIG. 4, and (c) is a FIG. It is explanatory drawing of the problem of the tape carrier package shown in FIG.
【０００９】図６(イ),(ロ) において、バンプ４とリード
５との接続には、リード５のインナー部を 400℃程度に
加熱する熱圧着法が利用され、回路基板11の端子12とリ
ード５とのはんだ接続は、リード５のアウター部に被着
するはんだ（金属）層６と端子12に被着するはんだを利
用することになる。In FIGS. 6A and 6B, a thermocompression bonding method of heating the inner portion of the lead 5 to about 400 ° C. is used to connect the bump 4 and the lead 5, and the terminal 12 of the circuit board 11 is connected. The solder connection between the lead 5 and the lead 5 uses the solder (metal) layer 6 attached to the outer portion of the lead 5 and the solder attached to the terminal 12.
【００１０】リード５のインナー部を 400℃程度に加熱
したとき、そのインナー部に被着するめっき層６が溶融
し、図６(イ) に示すような溶融塊13ができる。溶融塊13
の大きさははんだ層６の厚さに影響し、リード５の全面
に渡って厚さ１μm 程度としたはんだ層６の溶融塊13
は、半導体チップ２に接触することがあった。When the inner part of the lead 5 is heated to about 400 ° C., the plating layer 6 adhered to the inner part is melted to form a molten mass 13 as shown in FIG. Molten mass 13
Influences the thickness of the solder layer 6, and the molten mass 13 of the solder layer 6 having a thickness of about 1 μm over the entire surface of the lead 5 is formed.
Sometimes contacted the semiconductor chip 2.
【００１１】そこで、溶融塊13を小さくするためはんだ
層６を薄くすると、リード５と基板端子12との接続に必
要なはんだ14の量が不足し、図６(ロ) に示すように接続
されないリード５がでたり、接続されてもその強度不足
で端子12から簡単に解離するリード５が生じ易いという
問題点があった。Therefore, if the solder layer 6 is thinned in order to make the molten mass 13 small, the amount of the solder 14 necessary for connecting the lead 5 and the substrate terminal 12 is insufficient, and the connection is not made as shown in FIG. 6B. There is a problem in that even if the lead 5 comes out or is connected, the lead 5 is easily detached from the terminal 12 due to insufficient strength thereof.
【００１２】図６(ハ) において、保護膜９を形成したテ
ープキャリアパッケージ７は、パッケージ３の形成時に
保護膜９も加熱される。その際、1.2 ×10-5程度である
ポリイミドテープ８の熱膨張率に対し、保護膜（ソルダ
ーレジスト）９の熱膨張率は6.5 ×10-5程度であるた
め、図示する如く保護膜９が凹状になる反りが発生す
る。In FIG. 6C, the tape carrier package 7 having the protective film 9 formed thereon is also heated when the package 3 is formed. At this time, the thermal expansion coefficient of the protective film (solder resist) 9 is about 6.5 × 10 -5 , whereas the thermal expansion coefficient of the protective film 9 is about 1.2 × 10 -5. A warp that becomes concave occurs.
【００１３】かかる反りは、テープキャリアパッケージ
７を回路基板等に実装するに際し、その作業性が損なわ
れると共に、接続不良が生じ易くするように作用する。[0013] The warp acts to impair the workability of the tape carrier package 7 when it is mounted on a circuit board or the like, and to easily cause a connection failure.
【００１４】[0014]
【課題を解決するための手段】従来の溶融塊をなくす本
発明の第１の手段とし、半導体装置実装基板の端子に接
続するアウター部には、該端子とアウター部との接続の
ための加熱によって溶融し、該端子との接続に必要な量
を提供する厚さの第１の金属層24を形成し、該アウター
部に連通し金属バンプ４を介して半導体チップ２に接続
するインナー部には、半導体チップ２とインナー部との
接続のための加熱により溶融し生じる溶融塊の成長をチ
ップ２に接触しない範囲に抑制するように第１の金属層
24より薄い第２の金属層23を形成する。As a first means of the present invention for eliminating a conventional molten lump, an outer portion connected to a terminal of a semiconductor device mounting substrate is provided with heating for connecting the terminal and the outer portion. The first metal layer 24 having a thickness that provides a necessary amount for connection with the terminal is formed by melting and is connected to the semiconductor chip 2 via the metal bump 4 through the metal bump 4. Is the first metal layer so as to suppress the growth of a molten lump that is melted by heating for connecting the semiconductor chip 2 and the inner portion to a range not in contact with the chip 2.
A second metal layer 23 thinner than 24 is formed.
【００１５】従来の溶融塊をなくす本発明の第２の手段
とし、半導体装置実装基板の端子に接続するアウター部
には、該端子とアウター部との接続のための加熱によっ
て溶融し、該アウター部との接続に必要な量を提供する
厚さの第１の金属層34を形成し、該アウター部に連通し
金属バンプ４を介して半導体チップ２に接続するインナ
ー部には、第１の金属層34とほぼ同一厚さ，かつ，半導
体チップ２とインナー部との接続のための加熱により溶
融し生じる溶融塊の成長をチップ２に接触しない範囲に
抑制するように第１の金属層34より高融点である第２の
金属層33を形成する。As the second means of the present invention for eliminating the conventional molten lump, the outer portion connected to the terminal of the semiconductor device mounting substrate is melted by heating for connecting the terminal and the outer portion, and the outer portion The first metal layer 34 having a thickness that provides a necessary amount for connection to the outer portion is formed, and the first inner metal layer 34 is connected to the outer portion and connected to the semiconductor chip 2 via the metal bumps 4. The first metal layer 34 has substantially the same thickness as the metal layer 34 and suppresses the growth of a molten mass produced by heating for connecting the semiconductor chip 2 and the inner portion to a range not contacting the chip 2. A second metal layer 33 having a higher melting point is formed.
【００１６】リードを貼着した絶縁フィルムの反りをな
くす本発明の第１の手段としては、一端が半導体チップ
に接続し，該半導体チップを封止するパッケージ３より
導出するリード５を耐熱性絶縁フィルム８に貼着し、リ
ード５の導出部を貼着したフィルム８の表面および裏面
に、ほぼ同一厚さの絶縁保護膜9,28を被着する。As the first means of the present invention for eliminating the warp of the insulating film to which the leads are attached, one end is connected to the semiconductor chip, and the lead 5 led out from the package 3 for sealing the semiconductor chip is heat-resistant insulated. The insulating protective films 9 and 28 having substantially the same thickness are adhered to the front surface and the back surface of the film 8 adhered to the film 8 and the lead-out portion of the lead 5 adhered thereto.
【００１７】リードを貼着した絶縁フィルムの反りをな
くす本発明の第２の手段としては、一端が半導体チップ
に接続し，該半導体チップを封止するパッケージより導
出するリード５を耐熱性絶縁フィルム８に貼着し、リー
ド５の導出部を貼着した絶縁フィルム８の表面には適当
間隔の所望ピッチで複数の絶縁保護膜36が被着する。As a second means of the present invention for eliminating the warp of the insulating film having the leads attached, one end is connected to the semiconductor chip, and the lead 5 led out from the package for sealing the semiconductor chip is made of a heat-resistant insulating film. A plurality of insulating protective films 36 are adhered to the surface of the insulating film 8 which is adhered to No. 8 and the lead-out portion of the lead 5 is adhered to the surface of the insulating film 8 at a desired pitch with appropriate intervals.
【００１８】[0018]
【作用】リードの溶融塊をなくす前記第１の手段は、リ
ードに被着させる金属（一般にはんだ）の量をアウター
部よりインナー部で少なくした構成であり、そのことに
よってリードと半導体チップとを従来と同一方法で接続
しても、リードと基板端子との接続に支障をもたらすこ
となく、リードを半導体チップに接続したときの溶融塊
は、半導体チップに接触しないように小さくすることが
できる。The first means for eliminating the molten mass of the lead is a structure in which the amount of metal (generally solder) applied to the lead is smaller in the inner part than in the outer part, whereby the lead and the semiconductor chip are separated from each other. Even if they are connected by the same method as the conventional method, the molten mass when the leads are connected to the semiconductor chip can be made small so as not to come into contact with the semiconductor chip, without disturbing the connection between the leads and the substrate terminals.
【００１９】リードの溶融塊をなくす前記第２の手段
は、リードに被着させる金属（一般にはんだ）の融点
を、アウター部とインナー部とで違えた構成、即ちイン
ナー部の金属を溶融し難くした構成であり、そのことに
よってリードと半導体チップとを従来と同一方法で接続
しても、リードと基板端子との接続に支障をもたらすこ
となく、リードを半導体チップに接続したときの溶融塊
は、半導体チップに接触しないように小さくすることが
できる。The second means for eliminating the molten mass of the lead is such that the melting point of the metal (generally solder) applied to the lead is different between the outer part and the inner part, that is, it is difficult to melt the metal in the inner part. Even if the lead and the semiconductor chip are connected by the same method as in the conventional method, the molten mass when the lead is connected to the semiconductor chip is prevented without causing a hindrance to the connection between the lead and the substrate terminal. , Can be made small so as not to contact the semiconductor chip.
【００２０】絶縁フィルム８の反りをなくす前記第１の
手段は、絶縁フィルム８の両面に均等な応力を生じせし
める構成であり、そのことによって、絶縁フィルム８の
反りの無害化（抑制）を可能にする。The first means for eliminating the warp of the insulating film 8 is a constitution for producing uniform stress on both sides of the insulating film 8, and thereby the warp of the insulating film 8 can be made harmless (suppressed). To
【００２１】絶縁フィルム８の反りをなくす前記第２の
手段は、絶縁フィルム８の表面に被着した保護膜による
曲げ応力を分割させた構成であり、そのことによって、
絶縁フィルム８の反りを無害化（抑制）を可能にする。The second means for eliminating the warp of the insulating film 8 is a structure in which the bending stress due to the protective film adhered to the surface of the insulating film 8 is divided, and by this,
The warp of the insulating film 8 can be made harmless (suppressed).
【００２２】[0022]
【実施例】図１は本発明の実施例による半導体装置の説
明図、図２は本発明の他の実施例による半導体装置の説
明図、図３は本発明の他の実施例による半導体装置の説
明図である。1 is an explanatory diagram of a semiconductor device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of a semiconductor device according to another embodiment of the present invention, and FIG. 3 is a diagram of a semiconductor device according to another embodiment of the present invention. FIG.
【００２３】図１(イ) およびその一部分を拡大した図１
(ロ) において、従来技術における溶融塊障害をなくす表
面実装型の半導体装置21は、半導体チップ２を樹脂パッ
ケージ３に収容する。金属バンプ４を介して半導体チッ
プ２のパッドに接続するリード22のインナー部および中
間部の表面には、表面の安定化，金バンプ４との接着力
を確保する金属（はんだ）層23を形成し、回路基板の端
子にはんだ接続するリード22のアウター部表面には、表
面の安定化，該端子との接着力を確保する金属（はん
だ）層24を形成する。FIG. 1A and a partially enlarged view of FIG.
In (b), the surface mount type semiconductor device 21 which eliminates the melted block problem in the prior art stores the semiconductor chip 2 in the resin package 3. A metal (solder) layer 23 is formed on the surfaces of the inner portion and the intermediate portion of the leads 22 that are connected to the pads of the semiconductor chip 2 via the metal bumps 4, to stabilize the surface and secure the adhesive force with the gold bumps 4. Then, a metal (solder) layer 24 is formed on the surface of the outer portion of the lead 22 to be soldered to the terminal of the circuit board, which stabilizes the surface and secures an adhesive force with the terminal.
【００２４】はんだ層23は、バンプ４に熱圧着させたと
き発生する溶融塊がチップ２に接触しないような厚さ、
例えば0.１μm 〜１μm とする。はんだ層24は、回路基
板の端子にはんだ接続させたとき必要なはんだ量を確保
する厚さ、例えば３μm 〜1.5 μm とする。The solder layer 23 has a thickness such that a molten mass generated when the bump 4 is thermocompression-bonded does not come into contact with the chip 2.
For example, the thickness is 0.1 μm to 1 μm. The solder layer 24 has a thickness that secures a required amount of solder when soldered to the terminals of the circuit board, for example, 3 μm to 1.5 μm.
【００２５】かかるはんだ層23および24の製造工程は、
例えばポリイミドフィルムに銅箔を貼着し、その銅箔を
エッチングしてリード22を形成したのち、リード22の全
面にはんだ層23を被着せしめ、しかるのちリード22のア
ウター部にはんだを重ねめっきしてはんだ層24を形成す
る。The manufacturing process of the solder layers 23 and 24 is as follows.
For example, a copper foil is attached to a polyimide film, the copper foil is etched to form the leads 22, then the solder layer 23 is applied to the entire surface of the leads 22, and then the outer portions of the leads 22 are plated with solder. Then, the solder layer 24 is formed.
【００２６】なお半導体装置21は、ポリイミドフィルム
に貼着されたリード22のインナー部に半導体チップ２を
接続し、不要なポリイミドフィルムを除去してから各リ
ード22をほぼＺ字形に曲げ加工して完成する。In the semiconductor device 21, the semiconductor chip 2 is connected to the inner portion of the lead 22 attached to the polyimide film, the unnecessary polyimide film is removed, and then each lead 22 is bent into a substantially Z shape. Complete.
【００２７】図１(ハ) において、テープキャリアパッケ
ージ（半導体装置）27は、リード５を可撓性絶縁テープ
（一般にポリイミドテープ）８に貼着したキャリアテー
プに半導体チップ（図示せず）を搭載し、該半導体チッ
プを樹脂パッケージ３内に封入したのち、ポリイミドテ
ープ８のリード貼着面である表面に保護膜（ソルダーレ
ジスト）９を、裏面に保護膜（ソルダーレジスト）28を
被着してなる。In FIG. 1C, a tape carrier package (semiconductor device) 27 has a semiconductor chip (not shown) mounted on a carrier tape in which leads 5 are attached to a flexible insulating tape (generally a polyimide tape) 8. Then, after encapsulating the semiconductor chip in a resin package 3, a protective film (solder resist) 9 is applied to the surface of the polyimide tape 8 that is the lead sticking surface, and a protective film (solder resist) 28 is applied to the back surface. Become.
【００２８】スクリーン印刷により塗付し被着させた保
護膜９と28の厚さは、なるべく同一寸法とし、例えば0.
２μm 〜0.６μm 程度とする。なお、テープキャリアパ
ッケージ27において、インナー部およびアウター部に同
一厚さのはんだ層６を被着させたリード５に替え、図１
(イ),(ロ) を用いて説明したリード22または32を使用し、
有害なはんだ溶融塊を生じないテープキャリアパッケー
ジ（半導体装置）を構成することができる。The thicknesses of the protective films 9 and 28 applied and applied by screen printing should have the same dimensions as much as possible.
It is about 2 μm to 0.6 μm. In the tape carrier package 27, the lead 5 having the solder layer 6 of the same thickness adhered to the inner and outer parts is replaced by the one shown in FIG.
Use the lead 22 or 32 described in (a) and (b),
It is possible to configure a tape carrier package (semiconductor device) that does not generate harmful solder molten mass.
【００２９】図２において、表面実装型の半導体装置31
は、半導体チップ２を樹脂パッケージ３に収容する。金
属バンプ４を介して半導体チップ２のパッドに接続する
リード32のインナー部および中間部の表面には、表面の
安定化，金バンプ４との接着力を確保する金属（はん
だ）層33を形成し、回路基板の端子にはんだ接続するリ
ード32のアウター部表面には、表面の安定化，該端子と
の接着力を確保する金属（はんだ）層34を形成する。In FIG. 2, a surface mount type semiconductor device 31
Accommodates the semiconductor chip 2 in the resin package 3. A metal (solder) layer 33 is formed on the surfaces of the inner and middle portions of the leads 32 that are connected to the pads of the semiconductor chip 2 via the metal bumps 4 to stabilize the surface and secure the adhesive force with the gold bumps 4. Then, a metal (solder) layer 34 is formed on the surface of the outer portion of the lead 32 that is connected to the terminals of the circuit board by soldering, to stabilize the surface and secure the adhesive force with the terminals.
【００３０】従来技術における溶融塊障害をなくす半導
体装置31において、はんだ層33は従来よりも高融点はん
だ例えば９−１はんだを使用し、はんだ層33とほぼ同一
厚さのはんだ層34には低融点はんだ例えば６−４はんだ
を使用する。In the semiconductor device 31 which eliminates the melted block failure in the prior art, the solder layer 33 uses a higher melting point solder, for example, 9-1 solder, and the solder layer 33 having a thickness substantially the same as that of the solder layer 33 has a low thickness. A melting point solder such as 6-4 solder is used.
【００３１】従来技術におけるテープキャリアパッケー
ジ７の反りを無くす構成例を示す図３において、テープ
キャリアパッケージ35は、リード５をポリイミドテープ
８に貼着したキャリアテープに半導体チップ（図示せ
ず）を搭載し、該半導体チップを樹脂パッケージ３内に
封入したのち、ポリイミドテープ８のリード貼着面表面
に複数の保護膜 (ソルダーレジスト)36 を適当な間隔で
被着してなる。In FIG. 3 showing an example of the structure for eliminating the warp of the tape carrier package 7 in the prior art, the tape carrier package 35 has a semiconductor chip (not shown) mounted on a carrier tape in which the leads 5 are attached to the polyimide tape 8. Then, after encapsulating the semiconductor chip in a resin package 3, a plurality of protective films (solder resists) 36 are attached to the surface of the polyimide tape 8 on which the leads are attached at appropriate intervals.
【００３２】保護膜36は、例えばスクリーン印刷により
厚さ0.２μm 〜0.６μm 程度に被着する。なお、テープ
キャリアパッケージ36において、インナー部およびアウ
ター部に同一厚さのはんだ層６を被着させたリード５に
替え、図１(イ),(ロ) を用いて説明したリード22または32
を使用し、有害なはんだ溶融塊を生じないテープキャリ
アパッケージ（半導体装置）を構成することができる。The protective film 36 is applied by, for example, screen printing so as to have a thickness of about 0.2 μm to 0.6 μm. In the tape carrier package 36, instead of the lead 5 in which the solder layer 6 having the same thickness is applied to the inner portion and the outer portion, the lead 22 or 32 described with reference to FIGS.
Can be used to form a tape carrier package (semiconductor device) that does not generate harmful solder molten lumps.
【００３３】[0033]
【発明の効果】以上説明したように本発明によれば、リ
ードと半導体チップとを接続したときリードに形成され
る溶融塊は、半導体チップと接触しないように小さくす
ることを可能とすると共に、リードを貼着した絶縁フィ
ルムの反りを抑制可能とし、半導体装置の製造歩留りを
向上せしめた効果がある。As described above, according to the present invention, when the lead and the semiconductor chip are connected, the molten mass formed on the lead can be made small so as not to come into contact with the semiconductor chip. This has the effect of suppressing the warpage of the insulating film to which the leads are attached and improving the manufacturing yield of semiconductor devices.
【図１】 本発明の実施例による半導体装置の説明図FIG. 1 is an explanatory diagram of a semiconductor device according to an embodiment of the present invention.
【図２】 本発明の他の実施例による半導体装置の説明
図FIG. 2 is an explanatory view of a semiconductor device according to another embodiment of the present invention.
【図３】 本発明のさらに他の実施例による半導体装置
の説明図FIG. 3 is an explanatory view of a semiconductor device according to still another embodiment of the present invention.
【図４】 半導体チップを樹脂封止した従来の半導体装
置の側断面図FIG. 4 is a side sectional view of a conventional semiconductor device in which a semiconductor chip is resin-sealed.
【図５】 従来のテープキャリアパッケージの斜視図FIG. 5 is a perspective view of a conventional tape carrier package.
【図６】 従来技術の問題点の説明図FIG. 6 is an explanatory diagram of problems in the conventional technology.
２は半導体チップ ３はパッケージ ４は金属バンプ 5,22,32 はリード ８は絶縁フィルム 9,28,36 は保護膜 21,27,31,35 は半導体装置 23,24,33,34 はリードに被着した金属層（はんだ層） 2 is a semiconductor chip 3 is a package 4 is a metal bump 5,22,32 is a lead 8 is an insulating film 9,28,36 is a protective film 21,27,31,35 is a semiconductor device 23,24,33,34 is a lead Deposited metal layer (solder layer)
Claims (6)
ウター部には、該端子とアウター部との接続のための加
熱によって溶融し、該端子との接続に必要な量を提供す
る厚さの第１の金属層(24)を形成し、該アウター部に連
通し金属バンプ(4) を介して半導体チップ(2) に接続す
るインナー部には、該半導体チップとインナー部との接
続のための加熱により溶融し生じる溶融塊の成長を該チ
ップに接触しない範囲に抑制するように該第１の金属層
より薄い第２の金属層(23)を形成してなること、を特徴
とする半導体装置。1. An outer portion connected to a terminal of a semiconductor device mounting board is melted by heating for connecting the terminal and the outer portion, and has a thickness that provides a necessary amount for connection with the terminal. In order to connect the semiconductor chip to the inner part, the inner part that forms the first metal layer (24) and communicates with the outer part and connects to the semiconductor chip (2) through the metal bump (4) A second metal layer (23) thinner than the first metal layer is formed so as to suppress the growth of a molten lump that is melted by the heating of (1) to a range where it does not come into contact with the chip. apparatus.
ウター部には、該端子とアウター部との接続のための加
熱によって溶融し、該アウター部との接続に必要な量を
提供する厚さの第１の金属層(34)を形成し、該アウター
部に連通し金属バンプを介して半導体チップに接続する
インナー部には、該第１の金属層とほぼ同一厚さ，か
つ，該半導体チップとインナー部との接続のための加熱
により溶融し生じる溶融塊の成長を該チップに接触しな
い範囲に抑制するように該第１の金属層より高融点であ
る第２の金属層(33)を形成したこと、を特徴とする半導
体装置。2. The outer portion connected to a terminal of a semiconductor device mounting board has a thickness which is melted by heating for connecting the terminal and the outer portion and provides an amount necessary for connection with the outer portion. The first metal layer (34) is formed, and the inner portion which communicates with the outer portion and is connected to the semiconductor chip through the metal bumps has the same thickness as that of the first metal layer and the semiconductor layer. A second metal layer (33) having a melting point higher than that of the first metal layer so as to suppress the growth of a molten mass generated by melting for the connection between the chip and the inner part to a range not contacting the chip. Forming a semiconductor device.
(3) より導出するリード(5) の導出部を貼着した絶縁フ
ィルム(8) の表面および該絶縁フィルムの裏面には、ほ
ぼ同一厚さの絶縁保護膜(9,28)が被着されてなること、
を特徴とする半導体装置。3. A package in which a semiconductor chip (2) is sealed.
An insulating protective film (9, 28) of approximately the same thickness is applied to the front surface of the insulating film (8) to which the lead-out portion of the lead (5) derived from (3) is attached and the back surface of the insulating film. What to do,
A semiconductor device characterized by:
項１または請求項２記載のリード(22,32) を使用したこ
と、を特徴とする請求項３記載の半導体装置。4. The semiconductor device according to claim 3, wherein the leads (22, 32) according to claim 1 or 2 are used in place of the leads (5) according to claim 3.
チップを封止するパッケージより導出するリードの該導
出部が絶縁フィルムが貼着されており、該リードの導出
部の表面には適当間隔の所望ピッチで複数の保護膜ィル
ム(36)が形成されてなること、を特徴とする半導体装
置。5. An insulating film is attached to the lead-out portion of the lead which is connected to the semiconductor chip at one end thereof and which is led out from the package for encapsulating the semiconductor chip, and the lead-out portion of the lead has a suitable spacing on the surface thereof. 2. A semiconductor device comprising a plurality of protective film films (36) formed at a desired pitch.
項１または請求項２記載のリード(22,32) を使用したこ
と、を特徴とする請求項５記載の半導体装置。6. The semiconductor device according to claim 5, wherein the lead (5) according to claim 5 is replaced by the lead (22, 32) according to claim 1 or 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5127626A JPH06338536A (en) | 1993-05-31 | 1993-05-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5127626A JPH06338536A (en) | 1993-05-31 | 1993-05-31 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06338536A true JPH06338536A (en) | 1994-12-06 |
Family
ID=14964743
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5127626A Withdrawn JPH06338536A (en) | 1993-05-31 | 1993-05-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06338536A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0930646A3 (en) * | 1998-01-19 | 1999-07-28 | NEC Corporation | Lead-on-chip type semicoductor device having thin plate and method for manufacturing the same |
-
1993
- 1993-05-31 JP JP5127626A patent/JPH06338536A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0930646A3 (en) * | 1998-01-19 | 1999-07-28 | NEC Corporation | Lead-on-chip type semicoductor device having thin plate and method for manufacturing the same |
| US6093958A (en) * | 1998-01-19 | 2000-07-25 | Nec Corporation | Lead-on-chip type semiconductor device having thin plate and method for manufacturing the same |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20000801 |