JPH0837204A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Semiconductor device and method of manufacturing semiconductor device

Info

Publication number
JPH0837204A
JPH0837204A JP17265694A JP17265694A JPH0837204A JP H0837204 A JPH0837204 A JP H0837204A JP 17265694 A JP17265694 A JP 17265694A JP 17265694 A JP17265694 A JP 17265694A JP H0837204 A JPH0837204 A JP H0837204A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor chip
conductor pattern
semiconductor device
tab
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17265694A
Other languages
Japanese (ja)
Inventor
Atsushi Fukui
淳 福井
Takashi Nakajima
高士 中島
Keiji Takai
啓次 高井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
Original Assignee
Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP17265694A priority Critical patent/JPH0837204A/en
Publication of JPH0837204A publication Critical patent/JPH0837204A/en
Priority to US08/757,639 priority patent/US5717252A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/79—Apparatus for Tape Automated Bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To provide a semiconductor device that is easy to mount and excellent in reliability when bonding pads are arranged at small patches. CONSTITUTION:In a first semiconductor device, onto an insulation tape 2 formed with a conductive pattern 1 on the surface, namely on the rear surface side of a TAB substrate, a support substrate 4 of heat conductivity in which is a semiconductor chip 3 is fixed to a recess part is mounted, and on the surface side of the insulation tape, solder balls 5 are arranged so as to connect with the conductive pattern 1 on the surface side via a hole.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体装置および半導
体装置の製造方法に係り、特に、ＳＢＣ（ソルダボール
コネクト）法を用いた半導体装置の実装に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly to mounting of the semiconductor device using an SBC (solder ball connect) method.

【０００２】[0002]

【従来の技術】ＩＣ、ＬＳＩ等の半導体装置は、実装基
板上の回路パターンに半田等を用いて接続されている。
近年、素子の微細化および装置の小型化に対応して、Ｓ
ＢＣ法と指称される、半田ボールを用いて回路基板上に
半導体パッケージを接続する方法が提案されている。こ
の方法によれば、実装基板上の回路パターンに位置決め
を行い、載置して加熱し固着すればよく、実装が容易で
あることから、注目されている。2. Description of the Related Art Semiconductor devices such as ICs and LSIs are connected to a circuit pattern on a mounting board by using solder or the like.
In recent years, in response to miniaturization of elements and downsizing of devices, S
A method called a BC method for connecting a semiconductor package on a circuit board using solder balls has been proposed. According to this method, positioning is performed on the circuit pattern on the mounting substrate, and it is sufficient that the circuit pattern is mounted, heated and fixed, and the mounting is easy, and therefore, it is drawing attention.

【０００３】この一例として、図８に示すように、スル
ーホールを有し、両面に回路パターンの形成されたＰＣ
Ｂ基板１０１上に半導体チップ１０２を搭載し、ワイヤ
１０３によって電気的接続を行うとともに、該ＰＣＢ基
板１０１の裏面側にソルダーボール１０４を配設し、表
面側を封止樹脂１０５によって封止してなるいわゆるＰ
ＢＧＡ（Plate Ball Grid Aray）方式がある。As an example of this, as shown in FIG. 8, a PC having through holes and circuit patterns formed on both sides
The semiconductor chip 102 is mounted on the B board 101, electrical connection is made by the wires 103, the solder balls 104 are arranged on the back surface side of the PCB board 101, and the front surface side is sealed by the sealing resin 105. Become so-called P
There is a BGA (Plate Ball Grid Aray) system.

【０００４】また、他の例として、図９に示すように両
面に回路パターンの形成されたＴＡＢテープ２０１上に
フェイスダウンで半導体チップ２０２を接続し、この周
囲に金属板からなる支持体２０３を接着剤を介して固着
するとともに、このＴＡＢテープ２０１に形成されたス
ルーホールＨを介して裏面にソルダーボール２０４を配
設し、表面側を封止樹脂２０５によって封止してなるい
わゆるＴＢＧＡ（TapeBall Grid Aray ）方式がある。As another example, as shown in FIG. 9, a semiconductor chip 202 is connected face down on a TAB tape 201 having circuit patterns formed on both sides, and a support 203 made of a metal plate is provided around the semiconductor chip 202. A so-called TBGA (TapeBall) in which the solder ball 204 is fixed on the back surface through a through hole H formed in the TAB tape 201 and the front surface side is sealed by a sealing resin 205 while being fixed by an adhesive. Grid Aray) method is available.

【０００５】しかしながら、いずれも両面に回路パター
ンの形成されたＰＣＢ基板あるいはＴＡＢ基板（Tape A
utomated Bonding）を用いているため、コストが高いと
いう問題があった。また、近年ではパッドピッチは７５
μm から６０μm 程度と微細化が進む一方であり、上述
した２つの方式では、ソルダーボールの形成ピッチの微
細化が困難であるため、微細パターンの接続に対応でき
ないという問題があった。However, in either case, a PCB substrate or a TAB substrate (Tape A
Since utomated Bonding) is used, there is a problem that the cost is high. In recent years, the pad pitch is 75
As the miniaturization continues to progress from about μm to about 60 μm, there is a problem that the above-mentioned two methods cannot cope with the connection of fine patterns because it is difficult to reduce the solder ball formation pitch.

【０００６】[0006]

【発明が解決しようとする課題】上述したように、従来
の方法では、コストが高くまた、ボンディングパッドの
狭ピッチ化に対応するのは困難であるという問題があっ
た。As described above, the conventional method has a problem that the cost is high and it is difficult to cope with the narrowing of the pitch of the bonding pads.

【０００７】本発明は、前記実情に鑑みてなされたもの
で、ボンディングパッドの狭ピッチ化に際しても、実装
が容易で信頼性の高い半導体装置を提供することを目的
とする。The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device which is easy to mount and has high reliability even when the pitch of the bonding pads is narrowed.

【０００８】[0008]

【課題を解決するための手段】そこで本発明の第１の半
導体装置の特徴は、凹部を形成した熱伝導性の支持基板
に半導体チップを搭載するとともに、この半導体チップ
およびこの支持基板の凹部の周縁部にＴＡＢ基板の絶縁
性テープ面側を固着し、さらにこのＴＡＢ基板の導体パ
ターン形成面側に、孔を形成した絶縁膜を形成し、この
絶縁膜の裏面側に、孔を介して表面側の前記導体パター
ンに接続するように半田ボールを配設したことにある。
すなわち本発明の第１の半導体装置は、チップ搭載領域
に凹部を形成するとともに熱伝導性材料で構成された支
持基板と、前記支持基板の前記凹部に接着剤を介して固
着せしめられた半導体チップと、前記半導体チップと電
気的接続のなされた導体パターンを表面側に担持した絶
縁性テープからなり、裏面側を前記支持基板の前記凹部
の周縁部に固着せしめられたＴＡＢ基板と、前記絶縁性
テープの前記導体パターン形成面側を被覆する絶縁膜
と、前記絶縁膜に形成されたスルーホールを介して前記
導体パターンに接続せしめられ、前記絶縁膜表面に突出
せしめられた半田ボールとを具備している。Therefore, the first semiconductor device of the present invention is characterized in that a semiconductor chip is mounted on a thermally conductive support substrate having a recess, and the semiconductor chip and the recess of the support substrate are The insulating tape surface side of the TAB substrate is fixed to the peripheral edge portion, and an insulating film having a hole is formed on the conductive pattern forming surface side of the TAB substrate. The solder balls are arranged so as to be connected to the conductor pattern on the side.
That is, a first semiconductor device of the present invention is a semiconductor chip in which a recess is formed in a chip mounting region and a supporting substrate made of a heat conductive material is fixed to the recess of the supporting substrate via an adhesive. And a TAB substrate having a back surface side fixed to a peripheral portion of the recess of the support substrate, the TAB board having an insulating tape carrying a conductor pattern electrically connected to the semiconductor chip on the front surface side, and the insulating property. An insulating film covering the surface of the tape on which the conductive pattern is formed; and a solder ball connected to the conductive pattern through a through hole formed in the insulating film and protruding from the surface of the insulating film. ing.

【０００９】望ましくは、この導体パターンは、その先
端が前記半導体チップのボンディングパッドの直上まで
延在せしめられ、前記ボンディングパッドに直接接続せ
しめられている。Desirably, the tip of the conductor pattern extends directly above the bonding pad of the semiconductor chip and is directly connected to the bonding pad.

【００１０】また望ましくは、この導体パターンは、前
記半導体チップのボンディングパッドにボンディングワ
イヤを介して接続せしめられている。Also, preferably, the conductor pattern is connected to a bonding pad of the semiconductor chip via a bonding wire.

【００１１】さらに本発明の第２の特徴は、熱伝導性の
支持基板に凹部を形成しこの凹部に半導体チップを固着
したのち、片面に導体パターンを形成したＴＡＢ基板
を、導体パターン形成面側が外側となるように支持基板
の平坦面上に固着し、さらにこのＴＡＢ基板の導体パタ
ーン側を孔を有する絶縁膜で被覆し、この孔を介して表
面側の前記導体パターンに接続するように半田ボールを
配設するようにしたことにある。すなわち、チップ搭載
領域に凹部を形成してなる熱伝導性の支持基板を用意す
る基板形成工程と、前記支持基板の前記凹部に接着剤を
介して半導体チップを固着せしめる半導体チップ搭載工
程と、絶縁性テープ上に導体パターンを形成してなるＴ
ＡＢ基板を用意するＴＡＢ基板形成工程と、前記ＴＡＢ
基板を前記支持基板上に固着し、前記半導体チップとの
電気的接続を達成するＴＡＢ基板搭載工程と、さらにこ
の上層に、表面に複数の孔が穿設せしめられた絶縁膜を
形成する絶縁膜形成工程と、前記絶縁膜上に半田ボール
を載せ、加熱により前記孔内の導体パターンと前記半田
ボールとを固溶せしめ、前記半田ボールを固着せしめる
ボール固着工程とを含む。Further, a second feature of the present invention is that a concave portion is formed in a heat conductive support substrate, a semiconductor chip is fixed to the concave portion, and then a TAB substrate having a conductor pattern formed on one side thereof It is fixed on the flat surface of the supporting substrate so that it is on the outside, and the conductor pattern side of this TAB substrate is covered with an insulating film having a hole, and solder is used to connect to the conductor pattern on the surface side through this hole. There is a ball. That is, a substrate forming step of preparing a thermally conductive support substrate having a concave portion formed in a chip mounting region, a semiconductor chip mounting step of fixing a semiconductor chip to the concave portion of the supporting substrate with an adhesive, and insulating T formed by forming a conductor pattern on the flexible tape
A TAB substrate forming step of preparing an AB substrate, and the TAB
A TAB substrate mounting step of fixing a substrate on the supporting substrate to achieve electrical connection with the semiconductor chip, and an insulating film for forming an insulating film having a plurality of holes formed on the surface on the TAB substrate mounting step. A forming step and a ball fixing step of fixing a solder ball by placing a solder ball on the insulating film and solidifying the conductor pattern in the hole and the solder ball by heating are fixed.

【００１２】望ましくは、前記基板形成工程は、金属基
板に絞り加工を行うことにより凹部を形成する工程を含
む。Preferably, the substrate forming step includes a step of forming a recess by drawing a metal substrate.

【００１３】また望ましくは、前記絶縁膜形成工程は、
前記絶縁性テープ表面を感光性樹脂フィルムで被覆する
被覆工程と、フォトリソグラフィにより前記感光性樹脂
フィルムの所定の領域に孔を形成する穿孔工程とを含
む。Preferably, the insulating film forming step is
The method includes a covering step of covering the surface of the insulating tape with a photosensitive resin film, and a perforating step of forming a hole in a predetermined region of the photosensitive resin film by photolithography.

【００１４】また本発明の第３の半導体装置の特徴は、
チップ搭載領域に凹部を形成してなる熱伝導性基板に、
ＴＡＢテープの導体パターン形成面側が固着せしめら
れ、このＴＡＢテープの絶縁性テープに穿設された孔に
半田ボールが固着せしめられていることにある。すなわ
ち、チップ搭載領域に凹部を形成するとともに熱伝導性
材料で構成された支持基板と、前記支持基板の前記凹部
に接着剤を介して固着せしめられた半導体チップと、前
記導体パターンが前記半導体チップ搭載面側に位置する
ように、前記支持基板の前記凹部の周縁部に固着せしめ
られ、前記半導体チップと電気的接続がなされた導体パ
ターンを担持する絶縁性テープと、前記絶縁テープに形
成されたスルーホールを介して前記導体パターンに接続
せしめられ、前記絶縁性テープ表面に突出せしめられた
半田ボールとを具備している。The third semiconductor device of the present invention is characterized in that
On a heat conductive substrate that has a recess in the chip mounting area,
This is because the conductor pattern forming surface side of the TAB tape is fixed, and the solder balls are fixed to the holes formed in the insulating tape of the TAB tape. That is, a support substrate formed of a heat conductive material and having a recess in the chip mounting region, a semiconductor chip fixed to the recess of the support substrate via an adhesive, and the conductor pattern having the semiconductor chip An insulating tape, which is fixed to the peripheral portion of the concave portion of the support substrate so as to be located on the mounting surface side, and which carries a conductive pattern electrically connected to the semiconductor chip, and formed on the insulating tape. And a solder ball connected to the conductor pattern through a through hole and protruding from the surface of the insulating tape.

【００１５】望ましくは、前記導体パターンは、前記半
導体チップのボンディングパッドの直上まで延在せしめ
られ、前記ボンディングパッドに直接接続せしめられて
いる。 また望ましくは、前記導体パターンは、前記半
導体チップのボンディングパッドにボンディングワイヤ
を介して接続せしめられている。Preferably, the conductor pattern is extended to a position right above a bonding pad of the semiconductor chip and is directly connected to the bonding pad. Further preferably, the conductor pattern is connected to a bonding pad of the semiconductor chip via a bonding wire.

【００１６】本発明の第４の半導体装置の製造方法の特
徴は、絶縁性テープ上に導体パターンを形成してなるＴ
ＡＢ基板上に、半導体チップを搭載した後、チップ搭載
領域に凹部を形成した熱伝導性の支持基板を、半導体チ
ップとＴＡＢ基板との両方を覆うように固着したことを
特徴とする。すなわち、チップ搭載領域に凹部を形成し
てなる熱伝導性の支持基板を用意する基板形成工程と、
絶縁性テープ上に導体パターンを形成してなるＴＡＢ基
板を用意するＴＡＢ基板形成工程と、前記ＴＡＢ基板の
導体パターン上に、半導体チップをフェ−スダウンで搭
載し直接接続により電気的接続を達成する半導体チップ
搭載工程と、前記支持基板の前記凹部に接着剤を介して
半導体チップを固着せしめるとともに、前記支持基板と
前記ＴＡＢ基板とを絶縁性接着剤を介し固着する支持基
板固着工程と、前記ＴＡＢ基板の絶縁性テープに複数の
孔を穿設する穿孔工程と、前記絶縁性テープ上に半田ボ
ールを載せ、加熱により前記孔内の導体パターンと前記
半田ボールとを固溶せしめ、前記半田ボールを固着せし
めるボール固着工程とを含む。A feature of the fourth method of manufacturing a semiconductor device of the present invention is that the conductive pattern is formed on an insulating tape.
After the semiconductor chip is mounted on the AB substrate, a thermally conductive support substrate having a recess in the chip mounting region is fixed so as to cover both the semiconductor chip and the TAB substrate. That is, a substrate forming step of preparing a thermally conductive support substrate having a recess formed in the chip mounting region,
A TAB substrate forming step of preparing a TAB substrate in which a conductor pattern is formed on an insulating tape, and a semiconductor chip is mounted on the conductor pattern of the TAB substrate by facedown to achieve electrical connection by direct connection. A step of mounting a semiconductor chip; a step of fixing a semiconductor chip to the concave portion of the support substrate with an adhesive agent; and a step of fixing the support substrate and the TAB substrate with an insulating adhesive agent; A perforating step of forming a plurality of holes in the insulating tape of the substrate, placing a solder ball on the insulating tape, and solidifying the conductor pattern and the solder ball in the hole by heating, the solder ball And a ball fixing step of fixing.

【００１７】[0017]

【作用】本発明によれば、凹部を形成した金属基板など
の熱伝導性基板に半導体チップを搭載しているため、放
熱性が極めて良好である。また、片面に導体パターンを
形成した絶縁性テープすなわちＴＡＢ基板を用いて実装
しているため、表面と裏面のパターンのマスク合わせの
必要もなくまた、スルーホールめっきも不要であり、絶
縁性テープあるいはこれを覆う絶縁膜に形成した孔に半
田ボールを充填し、加熱等により導体パターン表面に固
着するのみでよく、製造が容易かつ高精度で安価であ
る。さらに半導体チップ搭載面側が、支持基板によって
完全に被覆保護されているため、支持強度が向上し信頼
性が高いものとなる。According to the present invention, since the semiconductor chip is mounted on the heat conductive substrate such as the metal substrate having the concave portion formed therein, the heat dissipation is extremely good. Further, since mounting is performed using an insulating tape having a conductor pattern formed on one surface, that is, a TAB substrate, there is no need to align the masks of the patterns on the front surface and the back surface, and through-hole plating is not necessary. It suffices to fill the holes formed in the insulating film covering this with solder balls and fix them to the surface of the conductor pattern by heating or the like, which is easy, highly accurate, and inexpensive. Furthermore, since the semiconductor chip mounting surface side is completely covered and protected by the supporting substrate, the supporting strength is improved and the reliability is high.

【００１８】本発明の第１の半導体装置によれば、凹部
を形成した金属基板などの熱伝導性基板上に半導体チッ
プを搭載しこれをＴＡＢ基板に接続し、表面を平坦にし
た状態で、孔を有する絶縁膜を形成し、この孔内に半田
ボールを固着するようにしているため、極めて高精度で
微細な半田ボールの形成が可能となり、パッドピッチを
微細化することが可能となる。望ましくは、ＴＡＢ基板
を半導体チップ上まで延ばし、ダイレクトボンディング
によって半導体チップとの電気的接続を達成するように
すれば、実装が極めて容易となる。また、ＴＡＢ基板と
半導体チップとの接続はワイヤボンディングを用いるよ
うにしてもよい。According to the first semiconductor device of the present invention, a semiconductor chip is mounted on a heat conductive substrate such as a metal substrate in which a recess is formed, the semiconductor chip is connected to a TAB substrate, and the surface is flattened. Since the insulating film having holes is formed and the solder balls are fixed in the holes, it is possible to form fine solder balls with extremely high precision, and it is possible to reduce the pad pitch. Desirably, if the TAB substrate is extended onto the semiconductor chip and the electrical connection with the semiconductor chip is achieved by direct bonding, mounting becomes extremely easy. Wire bonding may be used to connect the TAB substrate and the semiconductor chip.

【００１９】また、本発明の第２の半導体装置の製造方
法によれば、凹部を形成した熱伝導性基板上に半導体チ
ップを搭載したのち、これをＴＡＢ基板に接続し、表面
を平坦にした状態で、孔を有する絶縁膜で被覆し、この
孔内に、半田ボールを固着せしめることにより、極めて
容易に実装を行うことができる。望ましくはここで半田
ボールの形成に先だち、孔内にフラックス層を形成し、
このフラックス層上に半田ボールを供給し加熱すること
により、スルーホール内に露呈する導体パターンと固溶
状態になり、半田ボールはスルーホール内にのみ選択性
よく、良好に固着せしめられる。そして最後に、余剰の
フラックスを除去する工程を付加するようにしてもよ
い。このようにして高精度の半田ボールの形成が可能と
なる。Further, according to the second method of manufacturing a semiconductor device of the present invention, a semiconductor chip is mounted on a heat conductive substrate having a recess, and then the semiconductor chip is connected to a TAB substrate to make the surface flat. In this state, by covering with an insulating film having a hole and fixing a solder ball in this hole, mounting can be performed very easily. Desirably here, prior to the formation of the solder balls, a flux layer is formed in the holes,
By supplying and heating the solder balls on the flux layer, the solder balls are brought into a solid solution with the conductor patterns exposed in the through holes, and the solder balls can be well fixed in the through holes only with good selectivity. And finally, a step of removing excess flux may be added. In this way, highly accurate solder balls can be formed.

【００２０】また本発明の第３の半導体装置によれば、
ＴＡＢ基板の導体パターン形成面側に半導体チップをダ
イレクトボンディングにより搭載するとともに、絶縁性
テープに孔を形成し、半田ボールを固着せしめているた
め、金属基板との接続が一度に行われ、またＴＡＢ基板
表面を絶縁膜で被覆する必要がなく、製造が容易であ
る。According to the third semiconductor device of the present invention,
Since the semiconductor chip is mounted on the surface of the TAB substrate on which the conductor pattern is formed by direct bonding, holes are formed in the insulating tape and the solder balls are fixed, the connection to the metal substrate is made at once, and the TAB is also formed. Since it is not necessary to cover the surface of the substrate with an insulating film, manufacturing is easy.

【００２１】さらに本発明の第４の半導体装置の製造方
法によれば、生産性が高く、製造が容易である。Further, according to the fourth semiconductor device manufacturing method of the present invention, the productivity is high and the manufacturing is easy.

【００２２】[0022]

【実施例】以下、本発明の実施例について、図面を参照
しつつ詳細に説明する。Embodiments of the present invention will now be described in detail with reference to the drawings.

【００２３】本発明の第１の実施例の半導体装置は図１
に示すように、凹部を有する金属基板４と、この凹部に
搭載された半導体チップ３と、この凹部を覆うように、
金属基板および半導体チップの両方に接続され、片面に
導体パターン１を形成したＴＡＢ基板と、ＴＡＢ基板の
裏面側に突出せしめられた半田ボール５とから構成され
たことを特徴とするものである。ここでＴＡＢ基板は、
チップ搭載領域に開口を有する絶縁性テープ２の片面に
導体パターン１を形成して構成されている。そしてこの
ＴＡＢ基板の導体パターン形成面側は、半導体チップ３
を凹部に搭載した金属基板４が配設されている。また、
ＴＡＢ基板の裏面側は孔Ｈを有するポリイミド樹脂膜１
３で覆われ、この孔Ｈを介して、表面側の前記導体パタ
ーン１に接続するように半田ボール５が配設されポリイ
ミド樹脂膜１３上に突出せしめられている。さらに半導
体チップ３は金からなるボンディングワイヤ７を介して
導体パターン１に接続されている。また金属基板４はそ
の周縁部でポリイミド樹脂からなる絶縁性の接着剤６を
介してＴＡＢ基板に固着されておりまた、中央部の凹部
でもこの絶縁性接着剤を介して半導体チップ３に固着せ
しめられている。また、この孔Ｈは、格子状をなすよう
に全面に形成されている。The semiconductor device of the first embodiment of the present invention is shown in FIG.
, The metal substrate 4 having a recess, the semiconductor chip 3 mounted in the recess, and the recess so as to cover the recess.
It is characterized in that it is composed of a TAB substrate which is connected to both a metal substrate and a semiconductor chip and has a conductor pattern 1 formed on one surface thereof, and a solder ball 5 which is projected to the back surface side of the TAB substrate. Here, the TAB substrate is
A conductive pattern 1 is formed on one surface of an insulating tape 2 having an opening in a chip mounting area. The side of the TAB substrate on which the conductor pattern is formed is the semiconductor chip 3
The metal substrate 4 is mounted on the concave portion. Also,
Polyimide resin film 1 having holes H on the back side of the TAB substrate
3, the solder balls 5 are arranged so as to be connected to the conductor pattern 1 on the front surface side through the holes H and are projected onto the polyimide resin film 13. Further, the semiconductor chip 3 is connected to the conductor pattern 1 via a bonding wire 7 made of gold. Further, the metal substrate 4 is fixed to the TAB substrate at its peripheral portion via an insulating adhesive 6 made of a polyimide resin, and is also fixed to the semiconductor chip 3 at this central concave portion via this insulating adhesive. Has been. Further, the holes H are formed on the entire surface so as to form a lattice shape.

【００２４】図２(a) 乃至(d) はこの半導体装置の製造
工程図である。FIGS. 2A to 2D are manufacturing process diagrams of this semiconductor device.

【００２５】まず、図２(a) に示すように、銅箔にニッ
ケルメッキ層を形成してなる金属基板４にディプレス加
工を行い、チップ搭載領域に凹部を形成する。次に膜厚
５０μm のポリイミド樹脂からなる絶縁性テープ２のチ
ップ搭載領域に開口Ｏを形成すると共に、厚さ１８μm
の銅箔を貼着し、この銅箔をフォトリソグラフィにより
パターニングした後、膜厚０．５μm ニッケルめっき層
および膜厚０．５μmの金めっき層を形成し導体パター
ン１を有するＴＡＢ基板を構成する。そしてこのＴＡＢ
基板を前記金属基板４の平坦部に絶縁性の接着剤として
ポリイミド樹脂６を介して固着する。さらにこの金属基
板４の前記凹部に絶縁性の接着剤としてポリイミド樹脂
６を介して半導体チップ３を固着し、この後ボンディン
グワイヤ７を介してこの半導体チップ３のボンディング
パッドと導体パターン１との間の電気的接続を行う。First, as shown in FIG. 2 (a), a metal substrate 4 formed by forming a nickel plating layer on a copper foil is depressurized to form a recess in the chip mounting region. Next, an opening O is formed in the chip mounting region of the insulating tape 2 made of polyimide resin having a film thickness of 50 μm and the thickness is 18 μm.
Of the copper foil is adhered, the copper foil is patterned by photolithography, and then a nickel plating layer having a film thickness of 0.5 μm and a gold plating layer having a film thickness of 0.5 μm are formed to form a TAB substrate having a conductor pattern 1. . And this TAB
The substrate is fixed to the flat portion of the metal substrate 4 via a polyimide resin 6 as an insulating adhesive. Further, the semiconductor chip 3 is fixed to the concave portion of the metal substrate 4 through a polyimide resin 6 as an insulating adhesive, and then the bonding pad between the semiconductor chip 3 and the conductor pattern 1 is interposed through a bonding wire 7. Make electrical connection.

【００２６】そして図２(b) に示すように、この上層に
前記半導体チップ３を完全に覆うようにポリイミド樹脂
膜１３を塗布し、フォトリソグラフィにより面全体に格
子状をなすようにピッチ１．２７mm、孔径０．６５mmの
孔Ｈを形成する。Then, as shown in FIG. 2 (b), a polyimide resin film 13 is applied to the upper layer so as to completely cover the semiconductor chip 3, and photolithography is performed to form a pitch of 1. A hole H having a diameter of 27 mm and a diameter of 0.65 mm is formed.

【００２７】この後図２(c) に示すようにこの孔Ｈ内に
フラックスを印刷し、Ｐｂ１０％、Ｓｎ９０％の半田か
らなる直径０．７mmの半田ボール５を供給し、３２０℃
１０秒間（ピーク温度維持時間）の加熱工程を経て、表
面を導体パターン１に固着する。Thereafter, as shown in FIG. 2 (c), a flux is printed in the hole H, and a solder ball 5 having a diameter of 0.7 mm and made of a solder containing 10% Pb and 90% Sn is supplied at 320 ° C.
The surface is fixed to the conductor pattern 1 through a heating process for 10 seconds (peak temperature maintaining time).

【００２８】そして最後に必要に応じて、イソプロピル
アルコール（ＩＰＡ）に浸漬して超音波洗浄を行い、余
剰のフラックスを除去する。Finally, if necessary, it is immersed in isopropyl alcohol (IPA) for ultrasonic cleaning to remove excess flux.

【００２９】このようにして低コストでかつ高精度の半
田ボールが形成される。In this way, a low-cost and highly accurate solder ball is formed.

【００３０】なお、ここで絶縁膜としてポリイミド樹脂
膜１３を塗布したのちに孔を形成したが、あらかじめ孔
を形成してなる樹脂膜を貼着したりあるいは、パターン
印刷により絶縁膜を形成するようにしてもよい。またＴ
ＡＢ基板２上のみポリイミド樹脂膜１３を形成し、半導
体チップ搭載領域はポッティングにより樹脂を充填する
ようにしてもよい。Although the holes are formed after the polyimide resin film 13 is applied as the insulating film here, the resin film having the holes formed in advance may be attached, or the insulating film may be formed by pattern printing. You may See also T
The polyimide resin film 13 may be formed only on the AB substrate 2, and the semiconductor chip mounting region may be filled with resin by potting.

【００３１】また、孔ピッチや孔径は前記実施例に限定
されることなく適宜変形可能であり、例えば格子ピッチ
が１mmであれば、孔径は０．５５mm、格子ピッチが１．
５mmであれば、孔径は０．７５mmというふうに適宜変更
可能である。Further, the hole pitch and the hole diameter are not limited to those in the above embodiment, and can be appropriately changed. For example, if the grating pitch is 1 mm, the hole diameter is 0.55 mm and the grating pitch is 1.
If it is 5 mm, the hole diameter can be appropriately changed to 0.75 mm.

【００３２】さらに半田ボールの組成についても適宜選
択可能であり、例えばＰｂ３７％Ｓｎ６３％の共晶半田
を用いた場合には固着工程での加熱温度は２３０℃程度
でよい。Further, the composition of the solder balls can be appropriately selected. For example, when Pb37% Sn63% eutectic solder is used, the heating temperature in the fixing step may be about 230.degree.

【００３３】また、前記実施例では金属基板を用いた
が、アルミナ基板など熱伝導性の良好な基板であれば他
の材料を用いても良いことはいうまでもない。Further, although the metal substrate is used in the above-mentioned embodiment, it goes without saying that another material may be used as long as it is a substrate having a good thermal conductivity such as an alumina substrate.

【００３４】さらにまた、前記実施例では、支持基板を
絞り加工で形成したが、図３に変形例を示すように金属
基板４の凹部を、フライス加工によって形成したザグリ
で構成した金属基板１１を用いるようにしてもよい。こ
こでは半導体チップ３と金属基板との接続はシルバーペ
ーストと呼ばれる導電性接着剤１２で達成している。ま
た前記実施例では半導体チップの表面側はＴＡＢ基板上
と一体的に形成したポリイミド樹脂膜１３で被覆した
が、この例では、ポリイミド樹脂膜１３形成後にポッテ
ィング樹脂８で被覆するようにしている。Furthermore, in the above-mentioned embodiment, the supporting substrate is formed by drawing, but as shown in a modified example in FIG. 3, the concave portion of the metal substrate 4 is a metal substrate 11 formed by counterboring formed by milling. You may use it. Here, the connection between the semiconductor chip 3 and the metal substrate is achieved by a conductive adhesive 12 called silver paste. Further, in the above-described embodiment, the surface side of the semiconductor chip is covered with the polyimide resin film 13 formed integrally with the TAB substrate, but in this example, the polyimide resin film 13 is formed and then covered with the potting resin 8.

【００３５】また図４に示すように、金属基板２１とし
てプレス加工により半抜き状態にして凹部を形成したも
のを用いるようにしても良い。Further, as shown in FIG. 4, a metal substrate 21 may be used in which half-pressed state is formed by pressing to form a recess.

【００３６】次に本発明の第２の実施例としてダイレク
トボンディングの一例を説明する。この例では図１に示
した第１の実施例において、ワイヤボンディングに代え
てダイレクトボンディングを用いたことを特徴とするも
ので図５に示すように、導体パターン１が半導体チップ
３のボンディングパッド上まで伸長し、先端に形成され
たバンプ９を介して該ボンディングパッドに直接接合さ
れており、他の部分については前記第１の実施例と同様
に形成する。８はポリイミド樹脂などから構成されるポ
ッティング樹脂である。Next, an example of direct bonding will be described as a second embodiment of the present invention. This example is characterized by using direct bonding instead of wire bonding in the first embodiment shown in FIG. 1. As shown in FIG. 5, the conductor pattern 1 is on the bonding pad of the semiconductor chip 3. And is directly bonded to the bonding pad through the bump 9 formed at the tip, and other portions are formed in the same manner as in the first embodiment. Reference numeral 8 is a potting resin composed of a polyimide resin or the like.

【００３７】かかる構成によれば、極めて容易に実装が
可能である。According to this structure, mounting can be performed very easily.

【００３８】なおこの例では凹部の深さと半導体チップ
の厚さなどを調整し、表面が平坦となるようにする必要
があるが、かかる構成によれば、導体パターン１が可撓
性を有しているため、わずかの深さの差は吸収し、極め
て容易に実装が可能でありかつ、これにより極めて信頼
性が高く低コストの半導体装置を得ることが可能とな
る。また半導体チップと金属基板との間の接続を絶縁性
接着剤に代えて、シルバーペーストと指称される導電性
接着剤を介して固着することによりさらに放熱性が向上
する。In this example, it is necessary to adjust the depth of the recess and the thickness of the semiconductor chip so that the surface becomes flat. According to this structure, the conductor pattern 1 has flexibility. Therefore, it is possible to obtain a semiconductor device which absorbs a slight difference in depth and can be mounted extremely easily, and which is extremely reliable and low in cost. In addition, instead of the insulating adhesive, the connection between the semiconductor chip and the metal substrate is fixed via a conductive adhesive called silver paste, so that the heat dissipation is further improved.

【００３９】また、絶縁性テープの裏面側に形成される
樹脂膜は必ずしもポリイミド樹脂である必要はなく、エ
ポキシ樹脂あるいは感光性樹脂膜をもちいてもよい。ま
た、パターン印刷法により孔を形成しても良い。The resin film formed on the back surface side of the insulating tape does not necessarily have to be a polyimide resin, and an epoxy resin or a photosensitive resin film may be used. Alternatively, the holes may be formed by a pattern printing method.

【００４０】次に本発明の第３の実施例の半導体装置
は、図６に示すように、ＴＡＢ基板の導体パターン１形
成面側が半導体チップ３側となるようにし、該導体パタ
ーン１にダイレクトボンディングにより半導体チップを
接続し、さらにこのＴＡＢ基板の絶縁性テープに孔Ｈを
形成し、この孔Ｈ内に露呈する導体パターン１に半田ボ
ールを固着したことを特徴とするものである。ここで金
属基板４と半導体チップの裏面は導電性接着剤であるシ
ルバーペースト１２を介して固着されている。金属基板
４など他の部分については前記第１の実施例と同様に形
成されている。Next, in the semiconductor device of the third embodiment of the present invention, as shown in FIG. 6, the side of the TAB substrate on which the conductor pattern 1 is formed is the semiconductor chip 3 side, and the conductor pattern 1 is directly bonded. The semiconductor chip is connected by means of the above, holes H are further formed in the insulating tape of the TAB substrate, and solder balls are fixed to the conductor patterns 1 exposed in the holes H. Here, the metal substrate 4 and the back surface of the semiconductor chip are fixed to each other via a silver paste 12 which is a conductive adhesive. Other parts such as the metal substrate 4 are formed in the same manner as in the first embodiment.

【００４１】次にこの半導体装置の製造工程について説
明する。Next, the manufacturing process of this semiconductor device will be described.

【００４２】図７(a) に示すように、まず膜厚５０μm
のポリイミドテープに打ち抜きにより格子状をなすよう
に孔Ｈを形成し、この絶縁性テープ２を形成する。As shown in FIG. 7A, first, the film thickness is 50 μm.
The insulating tape 2 is formed by punching holes H in the polyimide tape to form a lattice pattern.

【００４３】次いで、図７(b) に示すように、フォトリ
ソグラフィによりパターニングしたＣｕ箔をこの絶縁性
テープの孔Ｈの開口を覆うように接着剤を介して貼着
し、この後無電解めっきを行うことによりこのＣｕパタ
ーン上にＮｉ層およびＡｕ層を形成して３層構造の導体
パターン１を形成するとともにボンディング領域に金バ
ンプ９を形成する。このとき導体パターン１は孔Ｈ内に
露呈しているためこの領域ではＣｕの両面にＮｉ層およ
びＡｕ層の形成された５層構造となっている。Next, as shown in FIG. 7 (b), a Cu foil patterned by photolithography is attached via an adhesive so as to cover the opening of the hole H of this insulating tape, and then electroless plating is performed. Then, a Ni layer and an Au layer are formed on the Cu pattern to form the conductor pattern 1 having a three-layer structure and the gold bumps 9 are formed in the bonding region. At this time, the conductor pattern 1 is exposed in the hole H, so that in this region, a five-layer structure in which a Ni layer and an Au layer are formed on both surfaces of Cu is formed.

【００４４】さらに図７(c) に示すように、このように
して形成されたＴＡＢ基板の絶縁性テープ２側に支持台
Ｑをあてて補強した状態で、この導体パターン上に半導
体チップ３のボンディングパッドが対応するように位置
決めを行いバンプ９を介してＴＡＢ基板上の導体パター
ン１と半導体チップ３とを接続する。Further, as shown in FIG. 7 (c), a support pedestal Q is applied to the insulating tape 2 side of the TAB substrate thus formed to reinforce it, and the semiconductor chip 3 is formed on this conductor pattern. Positioning is performed so that the bonding pads correspond to each other, and the conductor pattern 1 on the TAB substrate and the semiconductor chip 3 are connected via the bumps 9.

【００４５】一方図７(d) に示すように、両面にＮｉめ
っき層を形成してなるＣｕ板を金属基板４として使用
し、これに絞り加工を行うことにより半導体チップ搭載
領域に凹部を形成し、この金属基板４上の凹部に、シル
バーペースト１２を塗布するとともに、凹部周縁の平坦
領域にポリイミド樹脂からなる絶縁性接着剤６を塗布し
たものを用意する。On the other hand, as shown in FIG. 7 (d), a Cu plate having Ni plating layers formed on both surfaces is used as the metal substrate 4, and a recess is formed in the semiconductor chip mounting region by drawing the Cu plate. Then, a silver paste 12 is applied to the recesses on the metal substrate 4, and an insulating adhesive 6 made of a polyimide resin is applied to a flat area around the periphery of the recesses.

【００４６】そして図７(e) に示すように、この金属基
板４を、半導体チップ３を搭載したＴＡＢ基板上に位置
決めし、加圧しつつ加熱することにより、金属基板と半
導体チップ３およびＴＡＢ基板とを固着する。そしてさ
らに中央部の半導体チップ搭載領域はポリイミド樹脂８
などをポッティングなどにより充填する。Then, as shown in FIG. 7 (e), the metal substrate 4 is positioned on the TAB substrate on which the semiconductor chip 3 is mounted, and the metal substrate, the semiconductor chip 3 and the TAB substrate are heated by applying pressure. Stick and. Further, the semiconductor chip mounting area in the central portion is made of polyimide resin 8
Etc. are filled by potting etc.

【００４７】そして最後に、図７(f) に示すように、支
持台Ｑから外し、ＴＡＢ基板が上にくるようにして、絶
縁性テープに穿設された孔内に半田ボールを載置し加熱
することにより、半田ボールを導体パターン１に固着す
る。このとき孔内に露呈する導体パターン表面もＡｕ層
で覆われているため、パターンの裏面ではあるが、表面
側と同一の条件となっており、接着性が良好である。Finally, as shown in FIG. 7 (f), the solder balls are removed from the support base Q and the TAB substrate is placed on the solder balls in the holes formed in the insulating tape. The solder balls are fixed to the conductor pattern 1 by heating. At this time, since the surface of the conductor pattern exposed in the hole is also covered with the Au layer, the condition is the same as that of the front surface side even though it is the back surface of the pattern, and the adhesiveness is good.

【００４８】このようにして形成された半導体装置は、
製造が容易でかつ高精度の半田パターンが形成されてお
り、しかも低コストである。The semiconductor device thus formed is
The manufacturing process is easy and a highly accurate solder pattern is formed, and the cost is low.

【００４９】なお、前記第３の実施例ではダイレクトボ
ンディングによって形成したが、図８に第４の実施例を
示すようにワイヤボンディングによって半導体チップと
導体パターンとの接続を達成しても良い。この場合はＴ
ＡＢ基板を金属基板４の平坦部から凹部にやや張り出し
たかたちで接続し、この表面の導体パターン１をボンデ
ィングワイヤ７を介して半導体チップに接続している。
この場合は、半導体チップを搭載した金属基板上に、あ
らかじめ表面の導体パターン１にボンディングワイヤの
一端をボンディングしたＴＡＢ基板を固着し、この後こ
のボンディングワイヤの他端を半導体チップ側にボンデ
ィングする。Although the third embodiment is formed by direct bonding, the semiconductor chip and the conductor pattern may be connected by wire bonding as shown in FIG. 8 in the fourth embodiment. In this case T
The AB substrate is connected to the concave portion from the flat portion of the metal substrate 4 in a slightly protruding manner, and the conductor pattern 1 on the surface is connected to the semiconductor chip via the bonding wire 7.
In this case, the TAB substrate having one end of the bonding wire bonded to the conductor pattern 1 on the surface in advance is fixed to the metal substrate on which the semiconductor chip is mounted, and then the other end of the bonding wire is bonded to the semiconductor chip side.

【００５０】さらにまたこの変形例として図９に示すよ
うに、導体パターン１のみを張り出した形で形成しても
よい。この場合は、半導体チップを搭載した金属基板４
上にＴＡＢ基板を固着し、この後ボンディングを行うよ
うにすれば良い。Further, as a modification of this, as shown in FIG. 9, only the conductor pattern 1 may be formed so as to project. In this case, the metal substrate 4 on which the semiconductor chip is mounted
The TAB substrate may be fixed on top of this, and then bonding may be performed.

【００５１】さらに図６に示した第３の実施例の変形例
として図１０に示すように金属基板４の凹部を含む表面
をＴＡＢ基板で覆ってしまうようにしてもよい。この場
合は金属基板４に半導体チップ３を搭載した後、半導体
チップ３の周縁の凹部、およびボンディングパッドを除
く半導体チップ表面に、凹部を埋める程度の量の熱収縮
性樹脂８ｐを塗布しておき、ＴＡＢ基板を導体パターン
１形成面側を内側にして位置決めをおこない加圧しつつ
加熱硬化せしめる。そして同様にして半田ボールを形成
する。これにより極めて容易に信頼性の高い半導体装置
を得ることができる。Further, as a modification of the third embodiment shown in FIG. 6, the surface including the concave portion of the metal substrate 4 may be covered with the TAB substrate as shown in FIG. In this case, after the semiconductor chip 3 is mounted on the metal substrate 4, the heat-shrinkable resin 8p is applied to the recesses at the peripheral edge of the semiconductor chip 3 and the surface of the semiconductor chip excluding the bonding pads in an amount enough to fill the recesses. The TAB substrate is positioned with the side on which the conductor pattern 1 is formed facing inward, and is heat-cured while applying pressure. Then, solder balls are formed in the same manner. Thereby, a highly reliable semiconductor device can be obtained extremely easily.

【００５２】[0052]

【発明の効果】以上説明してきたように、本発明によれ
ば、低コスト化および信頼性の向上をはかることが可能
となる。As described above, according to the present invention, it is possible to reduce the cost and improve the reliability.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１の実施例の半導体装置を示す図FIG. 1 is a diagram showing a semiconductor device according to a first embodiment of the present invention.

【図２】本発明の第１の実施例の半導体装置の製造工程
を示す図FIG. 2 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

【図３】本発明の第１の実施例の半導体装置の変形例を
示す図FIG. 3 is a diagram showing a modification of the semiconductor device according to the first embodiment of the present invention.

【図４】本発明の第１の実施例の半導体装置の変形例を
示す図FIG. 4 is a diagram showing a modification of the semiconductor device according to the first embodiment of the present invention.

【図５】本発明の第２の実施例の半導体装置を示す図FIG. 5 is a diagram showing a semiconductor device according to a second embodiment of the present invention.

【図６】本発明の第３の実施例の半導体装置を示す図FIG. 6 is a diagram showing a semiconductor device according to a third embodiment of the present invention.

【図７】本発明の第３の実施例の半導体装置の製造工程
を示す図FIG. 7 is a diagram showing a manufacturing process of a semiconductor device according to a third embodiment of the present invention.

【図８】本発明の第４の実施例の半導体装置を示す図FIG. 8 is a diagram showing a semiconductor device according to a fourth embodiment of the present invention.

【図９】本発明の第４の実施例の半導体装置の変形例を
示す図FIG. 9 is a diagram showing a modification of the semiconductor device of the fourth embodiment of the present invention.

【図１０】本発明の第３の実施例の半導体装置の変形例
を示す図FIG. 10 is a diagram showing a modification of the semiconductor device according to the third embodiment of the present invention.

【図１１】従来例の半導体装置を示す図FIG. 11 is a diagram showing a conventional semiconductor device.

【図１２】従来例の半導体装置を示す図FIG. 12 is a diagram showing a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１ 導体パターン ２ 絶縁性テープ ３ 半導体チップ ４ 金属基板 ５ 半田ボール ６ 絶縁性接着剤 ７ ボンディングワイヤ ８ 封止樹脂（ポッティング樹脂） ８ｐ 熱収縮性樹脂 ９ バンプ １１ 金属基板 １２ 導電性接着剤 １３ 絶縁膜（ポリイミド樹脂膜） ２１ 金属基板 １０１ ＰＣＢ基板 １０２ 半導体チップ １０３ ワイヤ １０４ ソルダーボール（半田ボール） １０５ 封止樹脂 ２０１ ＴＡＢテープ ２０２ 半導体チップ ２０３ 支持体 ２０４ ソルダーボール（半田ボール） ２０５ 封止樹脂 DESCRIPTION OF SYMBOLS 1 Conductor pattern 2 Insulating tape 3 Semiconductor chip 4 Metal substrate 5 Solder ball 6 Insulating adhesive 7 Bonding wire 8 Sealing resin (potting resin) 8p Heat shrinkable resin 9 Bump 11 Metal substrate 12 Conductive adhesive 13 Insulating film (Polyimide resin film) 21 Metal substrate 101 PCB substrate 102 Semiconductor chip 103 Wire 104 Solder ball (solder ball) 105 Encapsulating resin 201 TAB tape 202 Semiconductor chip 203 Support 204 Solder ball (solder ball) 205 Encapsulating resin

Claims (10)

【特許請求の範囲】[Claims] 【請求項１】 チップ搭載領域に凹部を形成するととも
に熱伝導性材料で構成された支持基板と、 前記支持基板の前記凹部に接着剤を介して固着せしめら
れた半導体チップと、 前記半導体チップと電気的接続のなされた導体パターン
を表面側に担持した絶縁性テープからなり、この絶縁性
テープの裏面側を前記支持基板の前記凹部の周縁部に固
着せしめたＴＡＢ基板と、 前記絶縁性テープの前記導体パターン形成面側を被覆す
る絶縁膜と、 前記絶縁膜に形成されたスルーホールを介して前記導体
パターンに接続せしめられ、前記絶縁膜表面に突出せし
められた半田ボールとを具備したことを特徴とする半導
体装置。1. A support substrate, which is formed of a heat conductive material and has a recess formed in a chip mounting region, a semiconductor chip fixed to the recess of the support substrate via an adhesive, and the semiconductor chip. A TAB substrate which is made of an insulating tape having a conductive pattern electrically connected to the front surface thereof, the back surface of the insulating tape being fixed to the peripheral edge of the recess of the supporting substrate; An insulating film covering the conductor pattern forming surface side; and a solder ball connected to the conductor pattern through a through hole formed in the insulating film and protruding from the insulating film surface. Characteristic semiconductor device. 【請求項２】 前記導体パターンは、その先端が前記半
導体チップのボンディングパッドの直上まで延在せしめ
られ、前記ボンディングパッドに直接接続せしめられて
いることを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the conductor pattern has a tip extending to just above a bonding pad of the semiconductor chip and is directly connected to the bonding pad. 【請求項３】 前記導体パターンは、ボンディングワイ
ヤを介して前記半導体チップのボンディングパッドに接
続せしめられていることを特徴とする請求項１記載の半
導体装置。3. The semiconductor device according to claim 1, wherein the conductor pattern is connected to a bonding pad of the semiconductor chip via a bonding wire. 【請求項４】 チップ搭載領域に凹部を形成してなる熱
伝導性の支持基板を用意する基板形成工程と、 前記支持基板の前記凹部に接着剤を介して半導体チップ
を固着せしめる半導体チップ搭載工程と、 絶縁性テープ上に導体パターンを形成してなるＴＡＢ基
板を用意するＴＡＢ基板形成工程と、 前記ＴＡＢ基板を前記支持基板上に固着し、前記半導体
チップとの電気的接続を達成するＴＡＢ基板搭載工程
と、 さらにこの上層に、表面に複数の孔が穿設せしめられた
絶縁膜を形成する絶縁膜形成工程と、 前記絶縁膜上に半田ボールを載せ、加熱により前記孔内
の導体パターンと前記半田ボールとを固溶せしめ、前記
半田ボールを固着せしめるボール固着工程とを含むこと
を特徴とする半導体装置の製造方法。4. A substrate forming step of preparing a heat conductive support substrate having a concave portion formed in a chip mounting area, and a semiconductor chip mounting step of fixing a semiconductor chip to the concave portion of the supporting substrate with an adhesive agent. And a TAB substrate forming step of preparing a TAB substrate having a conductive pattern formed on an insulating tape, and a TAB substrate for fixing the TAB substrate on the supporting substrate to achieve electrical connection with the semiconductor chip. A mounting step, an insulating film forming step of further forming an insulating film having a plurality of holes formed on the surface on the upper layer, and a solder ball placed on the insulating film, and a conductor pattern in the holes by heating. A method of manufacturing a semiconductor device, comprising a step of solid-dissolving the solder balls and fixing the solder balls. 【請求項５】 前記基板形成工程は、金属基板に絞り加
工を行うことにより凹部を形成する工程を含むことを特
徴とする請求項４記載の半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 4, wherein the substrate forming step includes a step of forming a recess by drawing a metal substrate. 【請求項６】 前記絶縁膜形成工程は、 前記絶縁性テープ表面を感光性樹脂フィルムで被覆する
被覆工程と、 フォトリソグラフィにより前記感光性樹脂フィルムの所
定の領域に孔を形成する穿孔工程とを含むことを特徴と
する請求項４記載の半導体装置の製造方法。6. The insulating film forming step includes a covering step of covering the surface of the insulating tape with a photosensitive resin film, and a perforating step of forming a hole in a predetermined region of the photosensitive resin film by photolithography. The method of manufacturing a semiconductor device according to claim 4, further comprising: 【請求項７】 チップ搭載領域に凹部を形成するととも
に熱伝導性材料で構成された支持基板と、 前記支持基板の前記凹部に接着剤を介して固着せしめら
れた半導体チップと、 前記半導体チップと電気的接続のなされた導体パターン
を前記支持基板側に担持した絶縁性テープからなり、前
記支持基板の前記凹部の周縁部に固着せしめられたＴＡ
Ｂ基板と、 前記絶縁テープに形成されたスルーホールを介して前記
導体パターンに接続するとともに、前記絶縁性テープ表
面に突出した半田ボールとを具備したことを特徴とする
半導体装置。7. A support substrate having a recess formed in a chip mounting region and made of a heat conductive material, a semiconductor chip fixed to the recess of the support substrate with an adhesive, and the semiconductor chip. TA made of an insulating tape carrying a conductor pattern electrically connected to the supporting substrate side and fixed to the peripheral edge of the recess of the supporting substrate.
A semiconductor device comprising a B substrate and a solder ball connected to the conductor pattern through a through hole formed in the insulating tape and protruding from the surface of the insulating tape. 【請求項８】 前記導体パターンは、前記半導体チップ
のボンディングパッドの直上まで延在せしめられ、前記
ボンディングパッドに直接接続せしめられていることを
特徴とする請求項７記載の半導体装置。8. The semiconductor device according to claim 7, wherein the conductor pattern is extended to directly above a bonding pad of the semiconductor chip and is directly connected to the bonding pad. 【請求項９】 前記導体パターンは、ボンディングワイ
ヤを介して前記半導体チップのボンディングパッドに接
続せしめられていることを特徴とする請求項７記載の半
導体装置。9. The semiconductor device according to claim 7, wherein the conductor pattern is connected to a bonding pad of the semiconductor chip via a bonding wire. 【請求項１０】 チップ搭載領域に凹部を形成してなる
熱伝導性の支持基板を用意する基板形成工程と、 絶縁性テープ上に導体パターンを形成してなるＴＡＢ基
板を用意するＴＡＢ基板形成工程と、 前記ＴＡＢ基板の導体パターン上に、半導体チップをフ
ェ−スダウンで搭載し直接接続により電気的接続を達成
する半導体チップ搭載工程と、 前記支持基板の前記凹部に接着剤を介して半導体チップ
を固着せしめるとともに、前記支持基板と前記ＴＡＢ基
板とを絶縁性接着剤を介して固着する支持基板固着工程
と、 前記ＴＡＢ基板の絶縁性テープに複数の孔を穿設する穿
孔工程と、 前記絶縁性テープ上に半田ボールを載せ、加熱により前
記孔内の導体パターンと前記半田ボールとを固溶せし
め、前記半田ボールを固着せしめるボール固着工程とを
含むことを特徴とする半導体装置の製造方法。10. A substrate forming step of preparing a thermally conductive support substrate having a concave portion formed in a chip mounting region, and a TAB substrate forming step of preparing a TAB substrate having a conductive pattern formed on an insulating tape. And a semiconductor chip mounting step of mounting a semiconductor chip on a conductor pattern of the TAB substrate by face-down to achieve electrical connection by direct connection, and a semiconductor chip mounted on the concave portion of the support substrate via an adhesive. A supporting substrate fixing step of fixing and supporting the supporting substrate and the TAB substrate via an insulating adhesive; a perforating step of forming a plurality of holes in an insulating tape of the TAB substrate; A ball fixing step in which a solder ball is placed on a tape, the conductor pattern in the hole and the solder ball are solid-dissolved by heating, and the solder ball is fixed. The method of manufacturing a semiconductor device, which comprises a.
JP17265694A 1994-07-25 1994-07-25 Semiconductor device and method of manufacturing semiconductor device Pending JPH0837204A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP17265694A JPH0837204A (en) 1994-07-25 1994-07-25 Semiconductor device and method of manufacturing semiconductor device
US08/757,639 US5717252A (en) 1994-07-25 1996-12-02 Solder-ball connected semiconductor device with a recessed chip mounting area

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17265694A JPH0837204A (en) 1994-07-25 1994-07-25 Semiconductor device and method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JPH0837204A true JPH0837204A (en) 1996-02-06

Family

ID=15945948

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17265694A Pending JPH0837204A (en) 1994-07-25 1994-07-25 Semiconductor device and method of manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0837204A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6404070B1 (en) 1999-08-03 2002-06-11 Shinko Electric Industries Co., Ltd. Semiconductor device
DE19802575B4 (en) * 1997-01-25 2005-10-13 LG Semicon Co., Ltd., Cheongju A method of manufacturing a unit for a ball grid array semiconductor device and producing a ball grid array semiconductor device
WO2012165265A1 (en) * 2011-05-27 2012-12-06 日立化成工業株式会社 Substrate, method for producing same, heat-releasing substrate, and heat-releasing module

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19802575B4 (en) * 1997-01-25 2005-10-13 LG Semicon Co., Ltd., Cheongju A method of manufacturing a unit for a ball grid array semiconductor device and producing a ball grid array semiconductor device
US6404070B1 (en) 1999-08-03 2002-06-11 Shinko Electric Industries Co., Ltd. Semiconductor device
WO2012165265A1 (en) * 2011-05-27 2012-12-06 日立化成工業株式会社 Substrate, method for producing same, heat-releasing substrate, and heat-releasing module
CN103748672A (en) * 2011-05-27 2014-04-23 日立化成株式会社 Substrate, method for producing same, heat-releasing substrate, and heat-releasing module

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