JPH0864635A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0864635A
JPH0864635A JP6195564A JP19556494A JPH0864635A JP H0864635 A JPH0864635 A JP H0864635A JP 6195564 A JP6195564 A JP 6195564A JP 19556494 A JP19556494 A JP 19556494A JP H0864635 A JPH0864635 A JP H0864635A
Authority
JP
Japan
Prior art keywords
conductor pattern
semiconductor chip
insulating tape
surface side
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6195564A
Other languages
Japanese (ja)
Inventor
Atsushi Fukui
淳 福井
Takashi Nakajima
高士 中島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
Original Assignee
Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP6195564A priority Critical patent/JPH0864635A/en
Publication of JPH0864635A publication Critical patent/JPH0864635A/en
Priority to US08/757,639 priority patent/US5717252A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/79—Apparatus for Tape Automated Bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: To obtain a highly reliable semiconductor device which can be mounted easily even if the bonding pads are arranged at a fine pitch. CONSTITUTION: A semiconductor chip 3 and a metal board 4 are mounted on an insulating tape 2 having a conductor pattern formed on one side thereof, i.e., on the conductor pattern 1, forming side of a TAB board. Solder balls 5 are arranged on the rear side of the insulating tape 2 such that the solder balls are connected through holes H with a conductor pattern formed on the surface side.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体装置に係り、特
に、ＳＢＣ（ソルダボールコネクト）法を用いた半導体
装置の実装に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to mounting of a semiconductor device using an SBC (Solder Ball Connect) method.

【０００２】[0002]

【従来の技術】ＩＣ、ＬＳＩ等の半導体装置は、実装基
板上の回路パターンに半田等を用いて接続されている。
近年、素子の微細化および装置の小型化に対応して、Ｓ
ＢＣ法と指称される、半田ボールを用いて回路基板上に
半導体パッケージを接続する方法が提案されている。こ
の方法によれば、実装基板上の回路パターンに位置決め
を行い、載置して加熱し固着すればよく、実装が容易で
あることから、注目されている。2. Description of the Related Art Semiconductor devices such as ICs and LSIs are connected to a circuit pattern on a mounting board by using solder or the like.
In recent years, in response to miniaturization of elements and downsizing of devices, S
A method called a BC method for connecting a semiconductor package on a circuit board using solder balls has been proposed. According to this method, positioning is performed on the circuit pattern on the mounting substrate, and it is sufficient that the circuit pattern is mounted, heated and fixed, and the mounting is easy, and therefore, it is drawing attention.

【０００３】この一例として、図８に示すように、スル
ーホールを有し、両面に回路パターンの形成されたＰＣ
Ｂ基板１０１上に半導体チップ１０２を搭載し、ワイヤ
１０３によって電気的接続を行うとともに、該ＰＣＢ基
板１０１の裏面側にソルダーボール１０４を配設し、表
面側を封止樹脂１０５によって封止してなるいわゆるＰ
ＢＧＡ（Plastic Ball Grid Aray）方式がある。As an example of this, as shown in FIG. 8, a PC having through holes and circuit patterns formed on both sides
The semiconductor chip 102 is mounted on the B board 101, electrical connection is made by the wires 103, the solder balls 104 are arranged on the back surface side of the PCB board 101, and the front surface side is sealed by the sealing resin 105. Become so-called P
There is a BGA (Plastic Ball Grid Aray) system.

【０００４】また、他の例として、図９に示すように両
面に回路パターンの形成されたＴＡＢテープ２０１上に
フェイスダウンで半導体チップ２０２を接続し、この周
囲に金属板からなる支持体２０３を接着剤を介して固着
するとともに、このＴＡＢテープ２０１に形成されたス
ルーホールＨを介して裏面にソルダーボール２０４を配
設し、表面側を封止樹脂２０５によって封止してなるい
わゆるＴＢＧＡ（TapeBall Grid Aray ）方式がある。As another example, as shown in FIG. 9, a semiconductor chip 202 is connected face down on a TAB tape 201 having circuit patterns formed on both sides, and a support 203 made of a metal plate is provided around the semiconductor chip 202. A so-called TBGA (TapeBall) in which the solder ball 204 is fixed on the back surface through a through hole H formed in the TAB tape 201 and the front surface side is sealed by a sealing resin 205 while being fixed by an adhesive. Grid Aray) method is available.

【０００５】しかしながら、いずれも両面に回路パター
ンの形成されたＰＣＢ基板あるいはＴＡＢ（Tape Autom
ated Bonding）基板を用いているため、コストが高いと
いう問題があった。また、近年ではパッドピッチは７５
μm から６０μm 程度と微細化が進む一方であり、上述
した２つの方式では、ソルダーボールの形成ピッチの微
細化が困難であるため、微細パターンの接続に対応でき
ないという問題もあった。However, in both cases, a PCB substrate or a TAB (Tape Autom) with circuit patterns formed on both sides is used.
There is a problem that the cost is high because an ated bonding substrate is used. In recent years, the pad pitch is 75
As the miniaturization progresses from about μm to about 60 μm, there is a problem that the above-mentioned two methods cannot cope with the connection of fine patterns because it is difficult to reduce the solder ball formation pitch.

【０００６】[0006]

【発明が解決しようとする課題】上述したように、従来
の方法では、コストが高くまた、ボンディングパッドの
狭ピッチ化に対応するのは困難であるという問題があっ
た。As described above, the conventional method has a problem that the cost is high and it is difficult to cope with the narrowing of the pitch of the bonding pads.

【０００７】本発明は、前記実情に鑑みてなされたもの
で、ボンディングパッドの狭ピッチ化に際しても、実装
が容易で信頼性の高い半導体装置を提供することを目的
とする。The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device which is easy to mount and has high reliability even when the pitch of the bonding pads is narrowed.

【０００８】[0008]

【課題を解決するための手段】そこで本発明の第１の半
導体装置の特徴は、片面に導体パターンを形成した絶縁
性テープすなわちＴＡＢ基板の導体パターン形成面側に
半導体チップと金属基板とを搭載し、絶縁性テープの裏
面側に、孔を介して表面側の前記導体パターンに接続す
るように半田ボールを配設したことにある。すなわち本
発明の第１の半導体装置は、複数個の孔と、少なくとも
前記孔の開口を覆うように形成された導体パターンとを
表面側に具備した絶縁性テープと、前記絶縁性テープ表
面に固着せしめられ、前記導体パターンと電気的に接続
された半導体チップと、前記絶縁性テープ表面の前記半
導体チップを囲む領域に固着された金属基板と、前記絶
縁性テープの前記孔を介して前記導体パターンに接続せ
しめられ、前記絶縁性テープの裏面側に突出せしめられ
た半田ボールとを具備している。Therefore, the first semiconductor device of the present invention is characterized in that an insulating tape having a conductor pattern formed on one surface thereof, that is, a semiconductor chip and a metal substrate are mounted on the conductor pattern forming surface side of a TAB substrate. Then, the solder balls are arranged on the back surface side of the insulating tape so as to be connected to the conductor patterns on the front surface side through the holes. That is, the first semiconductor device of the present invention comprises an insulating tape having a plurality of holes and a conductor pattern formed so as to cover at least the openings of the holes on the front surface side, and fixed to the surface of the insulating tape. A semiconductor chip electrically connected to the conductor pattern, a metal substrate fixed to a region of the surface of the insulating tape surrounding the semiconductor chip, and the conductor pattern through the hole of the insulating tape. And a solder ball projected to the back side of the insulating tape.

【０００９】望ましくは、前記半導体チップと前記導体
パターンは、ボンディングワイヤを介して、接合せしめ
られ、前記半導体チップ表面および前記ボンディングワ
イヤは封止樹脂で被覆せしめられている。Desirably, the semiconductor chip and the conductor pattern are bonded via a bonding wire, and the surface of the semiconductor chip and the bonding wire are covered with a sealing resin.

【００１０】また望ましくは、前記半導体チップの表面
に形成されたボンディングパッドを介して前記半導体チ
ップは、前記導体パターンに直接接合せしめられてい
る。Preferably, the semiconductor chip is directly bonded to the conductor pattern via a bonding pad formed on the surface of the semiconductor chip.

【００１１】本発明の第２の半導体装置の特徴は、ＴＡ
Ｂ基板の絶縁性テープのチップ搭載領域に開口を形成
し、この開口内に導体パターンを伸長せしめ、絶縁性テ
ープ面側に金属基板を固着するとともに、この導体パタ
ーンの半導体チップを直接接合し、ＴＡＢ基板の導体パ
ターン形成面側を半導体チップとともに絶縁膜で被覆し
この絶縁膜に形成したスルーホールを介して半田ボール
を導体パターンに接続したことにある。すなわち、裏面
側に導体パターンを具備し、チップ搭載領域に開口を形
成してなる絶縁性テープと、前記絶縁性テープ上から、
前記開口内をボンディングパッドまで伸長せしめられた
導体パターンに、ボンディングパッドを直接接合した半
導体チップと、前記絶縁性テープのチップ搭載面側の前
記半導体チップの周縁部に貼着せしめられた金属基板
と、前記絶縁性テープの裏面側に、半導体チップおよび
前記絶縁性テープを一体的に被覆するように配設された
絶縁膜と、前記絶縁膜に形成されたスルーホールを介し
て前記導体パターンに接続せしめられ、前記絶縁膜表面
に突出せしめられた半田ボールとを具備している。The second semiconductor device of the present invention is characterized in that TA
An opening is formed in the chip mounting region of the insulating tape of the B substrate, a conductor pattern is extended in this opening, a metal substrate is fixed to the insulating tape surface side, and a semiconductor chip of this conductor pattern is directly joined, This is because the surface of the TAB substrate on which the conductor pattern is formed is covered with an insulating film together with the semiconductor chip, and the solder balls are connected to the conductor pattern through the through holes formed in the insulating film. That is, an insulating tape having a conductor pattern on the back surface side and having an opening formed in the chip mounting area, and from above the insulating tape,
A conductor pattern extended to the bonding pad in the opening, a semiconductor chip having a bonding pad directly joined, and a metal substrate attached to the peripheral edge of the semiconductor chip on the chip mounting surface side of the insulating tape. , An insulating film provided on the back surface side of the insulating tape so as to integrally cover the semiconductor chip and the insulating tape, and connected to the conductor pattern through a through hole formed in the insulating film And solder balls that are protruded from the surface of the insulating film.

【００１２】[0012]

【作用】本発明によれば、ＴＡＢ基板上の半導体チップ
を囲む領域に金属基板を固着しているため、支持強度が
高く、放熱性が極めて良好である。そして、片面に導体
パターンを形成した絶縁性テープすなわちＴＡＢ基板を
用いて実装しているため、表面と裏面のパターンのマス
ク合わせの必要もなくまた、スルーホールめっきも不要
であり、絶縁性テープあるいはこれを覆う絶縁膜に形成
した孔に半田ボールを充填し、加熱等により導体パター
ン表面に固着するのみでよく、製造が容易かつ高精度で
安価である。According to the present invention, since the metal substrate is fixed to the area surrounding the semiconductor chip on the TAB substrate, the supporting strength is high and the heat dissipation is extremely good. Since the mounting is performed using an insulating tape having a conductor pattern formed on one surface, that is, a TAB substrate, there is no need to align the masks of the patterns on the front surface and the back surface, and through-hole plating is not necessary. It suffices to fill the holes formed in the insulating film covering this with solder balls and fix them to the surface of the conductor pattern by heating or the like, which is easy, highly accurate, and inexpensive.

【００１３】望ましくは、ＴＡＢ基板を半導体チップ上
まで延ばし、ダイレクトボンディングによって半導体チ
ップとの電気的接続を達成するようにすれば、実装が極
めて容易となる。また、ＴＡＢ基板と半導体チップとの
接続はワイヤボンディングを用いるようにしてもよい。Desirably, if the TAB substrate is extended onto the semiconductor chip and the electrical connection with the semiconductor chip is achieved by direct bonding, mounting becomes extremely easy. Wire bonding may be used to connect the TAB substrate and the semiconductor chip.

【００１４】本発明の第２の半導体装置によれば、ＴＡ
Ｂ基板の絶縁性テープのチップ搭載領域に開口を設け、
この開口内に導体パターンを伸長させ、これを半導体チ
ップに直接接合し、さらにこのＴＡＢ基板の導体パター
ン形成面側を半導体チップとともに絶縁膜で被覆し、絶
縁膜に形成した孔を介して導体パターンに接続する半田
ボールを突出せしめているため、実装が極めて容易で、
信頼性の高いものとなる。According to the second semiconductor device of the present invention, TA
An opening is provided in the chip mounting area of the insulating tape on the B board,
A conductor pattern is extended in this opening and is directly bonded to the semiconductor chip, and the conductor pattern formation surface side of this TAB substrate is covered with an insulating film together with the semiconductor chip, and the conductor pattern is formed through the hole formed in the insulating film. Since the solder ball connected to is projected, it is extremely easy to mount,
It will be reliable.

【００１５】[0015]

【実施例】以下、本発明の実施例について、図面を参照
しつつ詳細に説明する。Embodiments of the present invention will now be described in detail with reference to the drawings.

【００１６】本発明の第１の実施例の半導体装置は図１
に示すように、片面に導体パターン１を形成したポリイ
ミド樹脂からなる絶縁性テープ２からなるＴＡＢ基板
の、導体パターン形成面側に半導体チップを搭載すると
ともに、この半導体チップを囲むように金属基板４を搭
載し、裏面側に半田ボール５を形成したことを特徴とす
るものである。そして、半導体チップ３は、金からなる
ボンディングワイヤ７を介して導体パターン１に接続さ
れ、このボンディングワイヤとともに、ポリイミド樹脂
からなるポッティング樹脂８で全体を被覆せしめられて
いる。そしてさらに、ＴＡＢ基板は孔Ｈを有し、この孔
を介して表面側の前記導体パターン１に接続するよう
に、裏面側に、半田ボール５が突出せしめてられてい
る。ここで半導体チップ３および金属基板４は、ポリイ
ミド樹脂からなる絶縁性接着剤６を介してＴＡＢ基板に
接続されている。また、この孔Ｈは、絶縁性テープの全
面に格子状をなすように形成されている。The semiconductor device of the first embodiment of the present invention is shown in FIG.
As shown in FIG. 3, a semiconductor chip is mounted on the conductor pattern forming surface side of a TAB substrate made of an insulating tape 2 made of a polyimide resin having a conductor pattern 1 formed on one surface, and a metal substrate 4 is provided so as to surround the semiconductor chip. Is mounted, and the solder balls 5 are formed on the back surface side. The semiconductor chip 3 is connected to the conductor pattern 1 through a bonding wire 7 made of gold, and the bonding wire 7 and the semiconductor chip 3 are entirely covered with a potting resin 8 made of a polyimide resin. Further, the TAB substrate has a hole H, and a solder ball 5 is projected on the back surface side so as to be connected to the conductor pattern 1 on the front surface side through this hole. Here, the semiconductor chip 3 and the metal substrate 4 are connected to the TAB substrate via an insulating adhesive 6 made of polyimide resin. The holes H are formed in a grid pattern on the entire surface of the insulating tape.

【００１７】図２(a) 乃至(c) はこの半導体装置の製造
工程図である。FIGS. 2A to 2C are manufacturing process diagrams of this semiconductor device.

【００１８】まず、図２(a) に示すように、膜厚５０μ
m のポリイミド樹脂からなる絶縁性テープ２に打ち抜き
により格子状をなすようにピッチ１．２７mm、孔径０．
６５mmの孔Ｈを形成し、この絶縁性テープ２を形成す
る。First, as shown in FIG. 2 (a), the film thickness is 50 μm.
An insulating tape 2 made of polyimide resin having a pitch of 1.27 mm and a hole diameter of 0.
A hole H of 65 mm is formed, and this insulating tape 2 is formed.

【００１９】次いで、図２(b) に示すように、この絶縁
性テープ表面に厚さ１８μm のＣｕ箔を貼着したのち、
フォトリソグラフィにより、この絶縁性テープの孔Ｈの
開口を覆うように、このＣｕ箔をパターニングし、この
後無電解めっきを行うことによりこのＣｕパターン上に
それぞれ膜厚０．５μm のＮｉ層およびＡｕ層を形成し
て３層構造の導体パターン１を形成する。このとき導体
パターン１は孔Ｈ内に露呈しているためこの領域ではＣ
ｕの両面にＮｉ層およびＡｕ層の形成された５層構造と
なっている。Then, as shown in FIG. 2 (b), a Cu foil having a thickness of 18 μm is attached to the surface of the insulating tape,
The Cu foil is patterned by photolithography so as to cover the opening of the hole H of the insulating tape, and then electroless plating is performed to form a Ni layer and an Au layer having a film thickness of 0.5 μm on the Cu pattern, respectively. Layers are formed to form a conductor pattern 1 having a three-layer structure. At this time, since the conductor pattern 1 is exposed in the hole H, C is present in this area.
It has a five-layer structure in which a Ni layer and an Au layer are formed on both sides of u.

【００２０】さらに図２(c) に示すように、このように
して形成されたＴＡＢ基板の絶縁性テープ２側に支持台
Ｑをあてて補強した状態で、この導体パターン上にポリ
イミドからなる絶縁性接着剤６を介して、ニッケルめっ
き層で被覆された銅板からなる枠状の金属基板４を加圧
しつつ加熱し固着する。一方この金属基板４の内側に絶
縁性接着剤６を介して同様に半導体チップ３を固着す
る。そしてワイヤボンディングにより半導体チップ３と
導体パターン１との間の電気的接続を達成したのち、ボ
ンディングワイヤ７および半導体チップ３を覆うように
ポリイミド樹脂（ポッティング樹脂８）をポッティング
し、固着保護する。Further, as shown in FIG. 2 (c), a support pedestal Q is applied to the insulating tape 2 side of the TAB substrate thus formed so as to be reinforced, and insulation made of polyimide is formed on the conductor pattern. The frame-shaped metal substrate 4 made of a copper plate coated with a nickel plating layer is heated and fixed via a conductive adhesive 6 while being pressed. On the other hand, the semiconductor chip 3 is similarly fixed to the inside of the metal substrate 4 via the insulating adhesive 6. Then, after electrical connection between the semiconductor chip 3 and the conductor pattern 1 is achieved by wire bonding, a polyimide resin (potting resin 8) is potted so as to cover the bonding wire 7 and the semiconductor chip 3, and fixation is secured.

【００２１】この後、絶縁性テープ２の孔Ｈ内にフラッ
クスを印刷し、Ｐｂ１０％、Ｓｎ９０％の半田からなる
直径０．７mmの半田ボール５を供給し、３２０℃１０秒
間（ピーク温度維持時間）の加熱工程を経て、表面を導
体パターン１に固着する。そして最後に必要に応じて、
イソプロピルアルコール（ＩＰＡ）に浸漬して超音波洗
浄を行い、余剰のフラックスを除去する。After that, a flux is printed in the holes H of the insulating tape 2 and a solder ball 5 of 0.7 mm in diameter made of Pb 10% and Sn 90% solder is supplied, and the temperature is 320 ° C. for 10 seconds (peak temperature maintenance time). ), The surface is fixed to the conductor pattern 1. And finally, if necessary,
It is immersed in isopropyl alcohol (IPA) and ultrasonically cleaned to remove excess flux.

【００２２】このようにして低コストでかつ高精度の半
田ボールが形成される。In this way, low-cost and high-precision solder balls are formed.

【００２３】なお、孔ピッチや孔径は前記実施例に限定
されることなく適宜変形可能であり、例えば格子ピッチ
が１mmであれば、孔径は０．５５mm、格子ピッチが１．
５mmであれば、孔径は０．７５mmというふうに適宜変更
可能である。The hole pitch and the hole diameter are not limited to those in the above embodiment, and can be appropriately changed. For example, if the grating pitch is 1 mm, the hole diameter is 0.55 mm and the grating pitch is 1.
If it is 5 mm, the hole diameter can be appropriately changed to 0.75 mm.

【００２４】さらに半田ボールの組成についても適宜選
択可能であり、例えばＰｂ３７％Ｓｎ６３％の共晶半田
を用いた場合には固着工程での加熱温度は２３０℃程度
でよい。Further, the composition of the solder balls can be appropriately selected. For example, when Pb37% Sn63% eutectic solder is used, the heating temperature in the fixing step may be about 230.degree.

【００２５】また、前記実施例では銅基板を用いたが、
アルミナ基板など熱伝導性の良好な基板であれば他の材
料を用いても良いことはいうまでもない。Although a copper substrate is used in the above embodiment,
It goes without saying that other materials may be used as long as they have good thermal conductivity, such as an alumina substrate.

【００２６】次に本発明の第２の実施例としてダイレク
トボンディングの一例を説明する。この例では図１に示
した第１の実施例において、ＴＡＢ基板としてチップ搭
載部に開口を形成したものを用い、ワイヤボンディング
に代えてダイレクトボンディングを用いたことを特徴と
するもので、図３に示すように、導体パターン１と半導
体チップ３のボンディングパッドがバンプ９を介して直
接接合されており、半導体チップ３の周りはポッティン
グ樹脂８Ｓにより固着されている。他の部分については
前記第１の実施例と同様に形成する。Next, an example of direct bonding will be described as a second embodiment of the present invention. This example is characterized in that in the first embodiment shown in FIG. 1, a TAB substrate having an opening formed in a chip mounting portion is used, and direct bonding is used instead of wire bonding. As shown in, the conductor pattern 1 and the bonding pads of the semiconductor chip 3 are directly bonded via the bumps 9, and the periphery of the semiconductor chip 3 is fixed by the potting resin 8S. Other parts are formed in the same manner as in the first embodiment.

【００２７】かかる構成によれば、極めて容易に実装が
可能である。According to this structure, mounting can be performed very easily.

【００２８】また必要箇所のみ導体パターンを絶縁被覆
しておくようにし、半導体チップと金属基板との間の接
続を、絶縁性接着剤に代えて、シルバーペーストと指称
される導電性接着剤を介して固着することにより、さら
に放熱性が向上する。In addition, the conductor pattern is insulated and coated only at necessary portions, and the connection between the semiconductor chip and the metal substrate is replaced with an electrically conductive adhesive called silver paste instead of the electrically insulating adhesive. By sticking together, the heat dissipation is further improved.

【００２９】また、ポッティング樹脂としては、必ずし
もポリイミド樹脂を用いる必要はなく、エポキシ樹脂等
他の樹脂膜を用いてもよい。As the potting resin, it is not always necessary to use a polyimide resin, but another resin film such as an epoxy resin may be used.

【００３０】次に本発明の第３の実施例の半導体装置
は、図４に示すように、ＴＡＢ基板の絶縁性テープ面側
に金属基板４および半導体チップ３を搭載するように
し、導体パターン１を半導体チップ３のボンディングパ
ッドの直上まで伸長し、導体パターン１にダイレクトボ
ンディングにより半導体チップ３を接続している。そし
てさらにこのＴＡＢ基板の導体パターン１形成面側に、
半導体チップ３をも覆うように絶縁膜１３を塗布しこの
絶縁膜に孔Ｈを形成し、この孔Ｈ内に露呈する導体パタ
ーン１に接続するように半田ボール５を形成している。
ここで金属基板４は導電性接着剤であるシルバーペース
ト１２を介して固着されている。バンプ９、金属基板４
など他の部分については前記第２の実施例と同様に形成
される。Next, in the semiconductor device of the third embodiment of the present invention, as shown in FIG. 4, the metal substrate 4 and the semiconductor chip 3 are mounted on the insulating tape surface side of the TAB substrate, and the conductor pattern 1 is formed. Is extended to just above the bonding pad of the semiconductor chip 3, and the semiconductor chip 3 is connected to the conductor pattern 1 by direct bonding. Further, on the side of the TAB substrate on which the conductor pattern 1 is formed,
An insulating film 13 is applied so as to also cover the semiconductor chip 3, holes H are formed in this insulating film, and solder balls 5 are formed so as to be connected to the conductor pattern 1 exposed in the holes H.
Here, the metal substrate 4 is fixed via a silver paste 12 which is a conductive adhesive. Bump 9, metal substrate 4
Other parts are formed in the same manner as in the second embodiment.

【００３１】次にこの半導体装置の製造工程について説
明する。Next, the manufacturing process of this semiconductor device will be described.

【００３２】図５(a) に示すように、まず膜厚５０μm
のポリイミドテープに、厚さ１８μm の銅箔を貼着し、
この銅箔をフォトリソグラフィによりパターニングした
後、膜厚０．５μm のニッケルめっき層および膜厚０．
５μm の金めっき層を形成し導体パターン１を有するＴ
ＡＢ基板を構成する。このとき導体パターンの先端にバ
ンプ９をめっきにより形成しておく。As shown in FIG. 5 (a), first, the film thickness is 50 μm.
Adhere 18 μm thick copper foil to the polyimide tape of
After patterning this copper foil by photolithography, a nickel plating layer having a thickness of 0.5 μm and a thickness of 0.
T with a 5 μm gold plated layer and conductor pattern 1
Configure the AB substrate. At this time, the bump 9 is formed on the tip of the conductor pattern by plating.

【００３３】次いで、図５(b) に示すように、このよう
にして形成されたＴＡＢ基板の導体パターン１形成面側
に支持台（図示せず）をあてて補強した状態で、この導
体パターン１のバンプ９上に半導体チップ３のボンディ
ングパッドが対応するように位置決めを行い、ＴＡＢ基
板上の導体パターン１と半導体チップ３とを接続する。
そしてさらに、金属基板４を、半導体チップ３を搭載し
たＴＡＢ基板上に位置決めし、加圧しつつ加熱すること
により固着する。Then, as shown in FIG. 5 (b), a support base (not shown) is applied to the surface of the TAB substrate thus formed on the side where the conductor pattern 1 is formed, and the conductor pattern is reinforced. Positioning is performed so that the bonding pad of the semiconductor chip 3 corresponds to the bump 9 of No. 1, and the conductor pattern 1 on the TAB substrate and the semiconductor chip 3 are connected.
Further, the metal substrate 4 is positioned on the TAB substrate on which the semiconductor chip 3 is mounted and fixed by heating while applying pressure.

【００３４】そして最後に、ポッティング樹脂８を充填
し、支持台Ｑから外し、ＴＡＢ基板が上にくるようにし
て、前記半導体チップ３を完全に覆うようにポリイミド
樹脂膜１３を塗布し、フォトリソグラフィにより面全体
に格子状をなすようにピッチ１．２７mm、孔径０．６５
mmの孔Ｈを形成する。この後この孔Ｈ内にフラックスを
印刷し、Ｐｂ１０％、Ｓｎ９０％の半田からなる直径
０．７mmの半田ボール５を供給し、２４０℃１０秒間
（ピーク温度維持時間）の加熱工程を経て、表面を導体
パターン１に固着する。Finally, the potting resin 8 is filled in, removed from the support Q, and the polyimide resin film 13 is applied so as to completely cover the semiconductor chip 3 so that the TAB substrate is on the top, and photolithography is performed. With a pitch of 1.27 mm and a hole diameter of 0.65
A hole H of mm is formed. After that, a flux is printed in the hole H, a solder ball 5 having a diameter of 0.7 mm made of Pb 10% and Sn 90% solder is supplied, and the surface is subjected to a heating process at 240 ° C. for 10 seconds (peak temperature maintaining time). Are fixed to the conductor pattern 1.

【００３５】そして最後に必要に応じて、イソプロピル
アルコール（ＩＰＡ）に浸漬して超音波洗浄を行い、余
剰のフラックスを除去する。Finally, if necessary, it is immersed in isopropyl alcohol (IPA) for ultrasonic cleaning to remove excess flux.

【００３６】このようにして形成された半導体装置は、
製造が容易でかつ高精度の半田パターンが形成されてお
り、しかも低コストである。The semiconductor device thus formed is
The manufacturing process is easy and a highly accurate solder pattern is formed, and the cost is low.

【００３７】なお、ここで絶縁膜としてポリイミド樹脂
膜１３を塗布したのち孔を形成したが、あらかじめ孔を
形成してなる樹脂膜を貼着するようにしてもよい。Although the holes are formed after the polyimide resin film 13 is applied as an insulating film here, a resin film formed with holes in advance may be attached.

【００３８】次に、本発明の第３の実施例について説明
する。この半導体装置は図６に示すように、ＴＡＢ基板
として、絶縁性テープの両面に導体パターン１を形成し
たものを用い、チップ搭載部ではこの導体パターンをス
ルーホールＨを介して裏面と電気的に接続するように
し、グランドプレートとして用いるようにしたことを特
徴とするものである。また半導体チップ３とＴＡＢ基板
とはボンディングワイヤ７を介して電気的に接続されて
おり、導体パターン１と半田ボール５とによって外部接
続が達成されるようになっている。また半導体チップは
銀ペースト（導電性接着剤１２）を介してＴＡＢ基板の
導体パターン１上に接続されている。８はポッティング
樹脂、１３は裏面の導体パターン１を被覆保護するため
の絶縁膜である。Next, a third embodiment of the present invention will be described. As shown in FIG. 6, this semiconductor device uses, as a TAB substrate, a conductive pattern 1 formed on both surfaces of an insulating tape, and the conductive pattern is electrically connected to the back surface through a through hole H in a chip mounting portion. It is characterized in that it is connected and used as a ground plate. Further, the semiconductor chip 3 and the TAB substrate are electrically connected to each other through the bonding wires 7, and the conductor pattern 1 and the solder balls 5 can achieve external connection. The semiconductor chip is connected to the conductor pattern 1 on the TAB substrate via a silver paste (conductive adhesive 12). Reference numeral 8 is a potting resin, and 13 is an insulating film for covering and protecting the conductor pattern 1 on the back surface.

【００３９】この構造では、前記実施例における効果に
加え、放熱性が良好で、別にグランドライン取り出しの
ための半田ボールを形成する必要がない。また、実装基
板への搭載に際しても、グランドプレートを構成する領
域を導電性ペーストを介して実装基板上に直接固着する
ようにしてもよく、実装作業性が良好である。With this structure, in addition to the effects of the above-described embodiment, the heat dissipation is good, and it is not necessary to separately form a solder ball for taking out the ground line. Also, when mounting on the mounting board, the region forming the ground plate may be directly fixed on the mounting board via the conductive paste, and the mounting workability is good.

【００４０】さらにまた本発明の第４の実施例として、
図７に示すように、金属基板として、ハーフエッチング
によってチップ搭載部に凹部を形成したキャップ状のＣ
ｕ板１４を用い、この凹部に導電性接着剤１２を介して
半導体チップ３を固着するようにしてもよい。なお、Ｔ
ＡＢ基板の導体パターン１と半導体チップ３との接続は
ボンディングワイヤ７を介して達成されており、ＴＡＢ
基板は導体パターン１形成面が外側にくるように金属基
板１４上に絶縁性接着剤６を介して貼着されている。ま
た、導体パターン１は絶縁膜１３によって被覆保護され
ている。かかる構造によれば、上記効果に加え製造が容
易でかつ放熱性が向上する。Furthermore, as a fourth embodiment of the present invention,
As shown in FIG. 7, as a metal substrate, a C-shaped cap having a recess formed in the chip mounting portion by half etching.
It is also possible to use the u plate 14 and fix the semiconductor chip 3 to this recess via the conductive adhesive 12. In addition, T
The connection between the conductor pattern 1 on the AB substrate and the semiconductor chip 3 is achieved via the bonding wire 7.
The substrate is adhered on the metal substrate 14 with an insulating adhesive 6 so that the surface on which the conductor pattern 1 is formed is on the outside. The conductor pattern 1 is covered and protected by the insulating film 13. According to this structure, in addition to the above effects, the manufacturing is easy and the heat dissipation is improved.

【００４１】[0041]

【発明の効果】以上説明してきたように、本発明によれ
ば、低コスト化および信頼性の向上をはかることが可能
となる。As described above, according to the present invention, it is possible to reduce the cost and improve the reliability.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１の実施例の半導体装置を示す図FIG. 1 is a diagram showing a semiconductor device according to a first embodiment of the present invention.

【図２】本発明の第１の実施例の半導体装置の製造工程
を示す図FIG. 2 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

【図３】本発明の第２の実施例の半導体装置を示す図FIG. 3 is a diagram showing a semiconductor device according to a second embodiment of the present invention.

【図４】本発明の第３の実施例の半導体装置を示す図FIG. 4 is a diagram showing a semiconductor device according to a third embodiment of the present invention.

【図５】本発明の第３の実施例の半導体装置の製造工程
を示す図FIG. 5 is a diagram showing a manufacturing process of a semiconductor device according to a third embodiment of the present invention.

【図６】本発明の第４の実施例の半導体装置を示す図FIG. 6 is a diagram showing a semiconductor device according to a fourth embodiment of the present invention.

【図７】本発明の第５の実施例の半導体装置を示す図FIG. 7 is a diagram showing a semiconductor device according to a fifth embodiment of the present invention.

【図８】従来例の半導体装置を示す図FIG. 8 is a diagram showing a conventional semiconductor device.

【図９】従来例の半導体装置を示す図FIG. 9 is a diagram showing a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１ 導体パターン ２ 絶縁性チップ ３ 半導体チップ ４ 金属基板 ５ 半田ボール ６ 絶縁性接着剤 ７ ボンディングワイヤ ８ 封止樹脂（ポッティング樹脂） ９ バンプ １２ 導電性接着剤 １３ ポリイミド樹脂膜 １０１ ＰＣＢ基板 １０２ 半導体チップ １０３ ワイヤ １０４ ソルダーボール（半田ボール） １０５ 封止樹脂 ２０１ ＴＡＢテープ ２０２ 半導体チップ ２０３ 支持体 ２０４ ソルダーボール（半田ボール） ２０５ 封止樹脂 1 Conductor Pattern 2 Insulating Chip 3 Semiconductor Chip 4 Metal Substrate 5 Solder Ball 6 Insulating Adhesive 7 Bonding Wire 8 Sealing Resin (Potting Resin) 9 Bump 12 Conductive Adhesive 13 Polyimide Resin Film 101 PCB Substrate 102 Semiconductor Chip 103 Wire 104 Solder Ball (Solder Ball) 105 Encapsulation Resin 201 TAB Tape 202 Semiconductor Chip 203 Support 204 Solder Ball (Solder Ball) 205 Encapsulation Resin

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 複数個の孔と、少なくとも前記孔の開口
を覆うように形成された導体パターンとを表面側に具備
した絶縁性テープと、 前記絶縁性テープ表面に固着せしめられ、前記導体パタ
ーンと電気的に接続された半導体チップと、 前記絶縁性テープ表面の前記半導体チップを囲む領域に
固着された金属基板と、 前記絶縁性テープの前記孔を
介して前記導体パターンに接続せしめられ、前記絶縁性
テープの裏面側に突出せしめられた半田ボールとを具備
したことを特徴とする半導体装置。1. An insulating tape having a plurality of holes and a conductor pattern formed so as to cover at least the openings of the holes on the surface side, and the conductor pattern fixed to the surface of the insulating tape. A semiconductor chip electrically connected to the insulating tape, a metal substrate fixed to a region surrounding the semiconductor chip on the surface of the insulating tape, and connected to the conductor pattern through the hole of the insulating tape, A semiconductor device, comprising: a solder ball projected on the back surface side of the insulating tape. 【請求項２】 前記半導体チップと前記導体パターンと
は、ボンディングワイヤを介して接合せしめられ、前記
半導体チップ表面および前記ボンディングワイヤは封止
樹脂で被覆せしめられていることを特徴とする請求項１
記載の半導体装置。2. The semiconductor chip and the conductor pattern are bonded to each other via a bonding wire, and the surface of the semiconductor chip and the bonding wire are covered with a sealing resin.
13. The semiconductor device according to claim 1. 【請求項３】 前記半導体チップは、前記導体パターン
に直接接合せしめられていることを特徴とする請求項１
記載の半導体装置。3. The semiconductor chip is directly bonded to the conductor pattern.
13. The semiconductor device according to claim 1. 【請求項４】 裏面側に導体パターンを具備し、チップ
搭載領域に開口を形成してなる絶縁性テープと、 前記導体パターンの一部は前記絶縁性テープ上から、前
記開口内をボンディングパッドまで伸長せしめられ、前
記ボンディングパッドと直接接合せしめられた半導体チ
ップと、 前記絶縁性テープのチップ搭載面側の前記半導体チップ
の周縁部に貼着せしめられた金属基板と、 前記絶縁性テープの裏面側に、半導体チップおよび前記
絶縁性テープを被覆するように配設された絶縁膜と、 前記絶縁膜に形成されたスルーホールを介して前記導体
パターンに接続せしめられ、前記絶縁膜表面に突出せし
められた半田ボールとを具備したことを特徴とする半導
体装置。4. An insulating tape having a conductor pattern on a back surface side and having an opening formed in a chip mounting region, and a part of the conductor pattern from above the insulating tape to a bonding pad within the opening. A semiconductor chip extended and directly bonded to the bonding pad, a metal substrate attached to the peripheral edge of the semiconductor chip on the chip mounting surface side of the insulating tape, and a back surface side of the insulating tape And an insulating film arranged to cover the semiconductor chip and the insulating tape, and a conductive pattern through a through hole formed in the insulating film, and projected on the surface of the insulating film. And a solder ball.
JP6195564A 1994-07-25 1994-08-19 Semiconductor device Pending JPH0864635A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP6195564A JPH0864635A (en) 1994-08-19 1994-08-19 Semiconductor device
US08/757,639 US5717252A (en) 1994-07-25 1996-12-02 Solder-ball connected semiconductor device with a recessed chip mounting area

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6195564A JPH0864635A (en) 1994-08-19 1994-08-19 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0864635A true JPH0864635A (en) 1996-03-08

Family

ID=16343224

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6195564A Pending JPH0864635A (en) 1994-07-25 1994-08-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0864635A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08203958A (en) * 1995-01-11 1996-08-09 Advanced Semiconductor Assembly Technol Inc Package for semiconductor die and its preparation
JPH08222594A (en) * 1995-02-14 1996-08-30 Nec Corp Semiconductor device
WO1997005653A1 (en) * 1995-08-01 1997-02-13 Minnesota Mining And Manufacturing Company Wire bond tape ball grid array package
JPH1035164A (en) * 1996-04-25 1998-02-10 Samsung Aerospace Ind Ltd Ic card and manufacture thereof
US5801449A (en) * 1994-12-16 1998-09-01 Bull S.A. Process and substrate for connecting an integrated circuit to another substrate by means of balls
KR20010046361A (en) * 1999-11-12 2001-06-15 박종섭 A tape for adhesive solder ball and a semiconductor package which use a tape for adhesive solder ball
KR100475337B1 (en) * 1997-09-13 2005-07-01 삼성전자주식회사 High Power Chip Scale Package and Manufacturing Method
KR100459820B1 (en) * 1997-09-13 2005-07-07 삼성전자주식회사 Chip scale package and its manufacturing method
DE19802575B4 (en) * 1997-01-25 2005-10-13 LG Semicon Co., Ltd., Cheongju A method of manufacturing a unit for a ball grid array semiconductor device and producing a ball grid array semiconductor device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5801449A (en) * 1994-12-16 1998-09-01 Bull S.A. Process and substrate for connecting an integrated circuit to another substrate by means of balls
JPH08203958A (en) * 1995-01-11 1996-08-09 Advanced Semiconductor Assembly Technol Inc Package for semiconductor die and its preparation
JPH08222594A (en) * 1995-02-14 1996-08-30 Nec Corp Semiconductor device
WO1997005653A1 (en) * 1995-08-01 1997-02-13 Minnesota Mining And Manufacturing Company Wire bond tape ball grid array package
JPH1035164A (en) * 1996-04-25 1998-02-10 Samsung Aerospace Ind Ltd Ic card and manufacture thereof
DE19802575B4 (en) * 1997-01-25 2005-10-13 LG Semicon Co., Ltd., Cheongju A method of manufacturing a unit for a ball grid array semiconductor device and producing a ball grid array semiconductor device
KR100475337B1 (en) * 1997-09-13 2005-07-01 삼성전자주식회사 High Power Chip Scale Package and Manufacturing Method
KR100459820B1 (en) * 1997-09-13 2005-07-07 삼성전자주식회사 Chip scale package and its manufacturing method
KR20010046361A (en) * 1999-11-12 2001-06-15 박종섭 A tape for adhesive solder ball and a semiconductor package which use a tape for adhesive solder ball

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