JPH0544199B2 - - Google Patents
Info
- Publication number
- JPH0544199B2 JPH0544199B2 JP57002203A JP220382A JPH0544199B2 JP H0544199 B2 JPH0544199 B2 JP H0544199B2 JP 57002203 A JP57002203 A JP 57002203A JP 220382 A JP220382 A JP 220382A JP H0544199 B2 JPH0544199 B2 JP H0544199B2
- Authority
- JP
- Japan
- Prior art keywords
- plating
- etching
- conductor
- resist film
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000007747 plating Methods 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 239000010949 copper Substances 0.000 claims description 14
- 239000006082 mold release agent Substances 0.000 claims description 14
- 239000011521 glass Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 10
- 239000011347 resin Substances 0.000 claims description 9
- 229920005989 resin Polymers 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims 1
- 239000010408 film Substances 0.000 description 11
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- PIBWKRNGBLPSSY-UHFFFAOYSA-L palladium(II) chloride Chemical compound Cl[Pd]Cl PIBWKRNGBLPSSY-UHFFFAOYSA-L 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Description
【発明の詳細な説明】 本発明は多層配線基板に関する。[Detailed description of the invention] The present invention relates to a multilayer wiring board.
多層配線基板には銅張り積層板を用いるいわゆ
るプリント多層配線板と、セラミツク基板及びガ
ラス基板等を用いる厚膜及び薄膜多層配線板があ
る。これらは絶縁材としての樹脂及びセラミツク
あるいはガラスの各層に導電性パターンを形成
し、これらのパターン及び絶縁層を貫通するスル
ーホールによつて各層の導電性パターンを接続し
ている。即ち従来技術では、予じめ成形された基
板上に導電性パターンを形成した後、これらのパ
ターンをつなぐためのスルーホールを微小ドリル
或いはパンチング等で設け、その後にこのスルー
ホール内に導電膜を形成して層間の電気接続を行
つている。ところがこの方法及びこの方法による
多層配線板では微小径のスルーホールの形成が困
難となり配線密度に限界が生じ、この為基板の縮
小化、回路の高集積化は不可能であつた。 Multilayer wiring boards include so-called printed multilayer wiring boards using copper-clad laminates, and thick film and thin film multilayer wiring boards using ceramic substrates, glass substrates, and the like. In these devices, conductive patterns are formed on each layer of resin, ceramic, or glass as insulating materials, and the conductive patterns in each layer are connected by through holes penetrating these patterns and the insulating layers. That is, in the conventional technology, after forming conductive patterns on a pre-formed substrate, through-holes for connecting these patterns are formed using a micro-drill or punching, and then a conductive film is formed in the through-holes. forming electrical connections between layers. However, with this method and the multilayer wiring board using this method, it is difficult to form through-holes with minute diameters, which limits the wiring density, making it impossible to downsize the board and increase the degree of circuit integration.
本発明は上記従来技術の欠点をなくし、配線基
板の配線密度を向上し得た高性能の多層配線基板
を提供することを目的とする。 SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art described above and provide a high-performance multilayer wiring board that can improve the wiring density of the wiring board.
上記目的を達成するため、本発明は、片面に離
型剤が塗布され、該離型剤に被着されためつき処
理用の導通層上に下部パターンとなる銅層を形成
したガラス製保持板等よりなる基材に、前記銅層
をエツチングレジスト膜をレジストにしてエツチ
ングして形成された下部パターンと、該下部パタ
ーンの所要位置に対してめつきレジスト膜のホト
エツチングプロセスにより形成された微小径の穴
にめつき処理にて形成された導通体と、該導通体
の形成に伴い前記めつきレジスト膜が除去された
位置と同位置に形成された絶縁性樹脂層と、該絶
縁性樹脂層および導通体の同一面上に前記導通体
を介して下部パターンに接続するように形成され
た上部パターンとを設け、該上部パターン形成後
に、前記ガラス製保持板，離型剤およびめつき処
理用の導通層を除去して形成された積層接合可能
な両面パターン基板からなる多層配線基板に構成
し、
また、片面に離型剤が塗布され、該離型剤に被
着されためつき処理用の導通層上に下部パターン
となる銅層を形成したガラス製保持板等よりなる
基材に、前記銅層をエツチングレジスト膜をレジ
ストにしてエツチングして形成された下部パター
ンと、該下部パターンの所要位置に対してめつき
レジスト膜のホトエツチングプロセスにより形成
された微小径の穴にめつき処理にて形成された導
通体と、該導通体の形成に伴い前記めつきレジス
ト膜が除去された位置と同位置に形成された絶縁
性樹脂層と、該絶縁性樹脂層および導通体の同一
面上に前記導通体を介して下部パターンに接続す
るように形成された上部パターンと、該上部パタ
ーン上にめつき処理にて上端面を露出するように
形成された接続端子とを設け、該接続端子形成後
に、前記ガラス製保持板，離型剤およびめつき処
理用の導通層を除去して形成された積層接合可能
な接続端子付の両面パターン基板からなる多層配
線基板に構成したものである。 In order to achieve the above object, the present invention provides a glass holding plate having a mold release agent coated on one side and a copper layer forming a lower pattern on a conductive layer for glazing treatment adhered to the mold release agent. A lower pattern is formed by etching the copper layer using an etching resist film as a resist, and a micro-pattern is formed by photo-etching a plated resist film at desired positions on the lower pattern. A conductor formed in a small-diameter hole by plating, an insulating resin layer formed at the same position where the plating resist film was removed when forming the conductor, and the insulating resin. An upper pattern formed to be connected to the lower pattern via the conductor is provided on the same surface of the layer and the conductor, and after the upper pattern is formed, the glass holding plate, the mold release agent and the plating treatment are applied. The multilayer wiring board consists of a double-sided patterned board that can be laminated and bonded by removing the conductive layer for the purpose, and one side is coated with a mold release agent, and the mold release agent is coated with a layer for heat treatment. A lower pattern formed by etching the copper layer using an etching resist film as a resist on a base material such as a glass holding plate on which a copper layer serving as a lower pattern is formed on the conductive layer, and a lower pattern of the lower pattern. A conductive body is formed by plating into a micro-diameter hole formed by a photoetching process of a plating resist film at a desired position, and the plating resist film is removed along with the formation of the conductive body. an insulating resin layer formed at the same position as the insulating resin layer, an upper pattern formed on the same surface of the insulating resin layer and the conductor so as to be connected to the lower pattern via the conductor, and the upper pattern. A connecting terminal is formed on the top by plating to expose the upper end surface, and after forming the connecting terminal, the glass holding plate, the mold release agent, and the conductive layer for plating are removed. This is a multilayer wiring board consisting of a double-sided patterned board with connection terminals that can be laminated and bonded.
以下に本発明を第１図及び第２図に示す実施例
に基づいて説明する。第１図ａ〜ｋは本発明の多
層配線基板を構成する配線板の製造工程を順次説
明する断面図、第２図は本発明の多層配線基板の
実施例を示す断面図である。 The present invention will be explained below based on the embodiments shown in FIGS. 1 and 2. FIGS. 1A to 1K are cross-sectional views sequentially illustrating the manufacturing process of a wiring board constituting a multilayer wiring board of the present invention, and FIG. 2 is a cross-sectional view showing an embodiment of the multilayer wiring board of the present invention.
第１図ａにおいて、表面を平坦化したガラス製
の保持板１の上面に、ガラスとの接着力が小さい
ワツクス等の離型剤２を回転塗布機で厚さが均一
になるよう塗布する。この後、離型剤２上面を塩
化パラジウムを含む活性化液で活性化し、無電解
めつき処理によつて錫層で形成されるめつき用導
通層３を全面に被着させる。この場合、離型剤２
以外の保持板１の裏面及び側面に被着した導通層
は、離型剤２上に被着しためつき用導通層３上に
エツチングレジスト処理を施こした後エツチング
にて除去しておく。また、このめつき用導通層
は、以降の工程で行なわれる電解めつき処理用の
導電層とするためのもので、次工程で説明する下
部パターンのエツチング処理時に同時にエツチン
グ除去されない材質のものであれば、錫以外の金
属を用いてもよい。さらに無電解めつき性の点か
ら下地の銅層を施こし、その上に錫層を施こす方
法も有効である。次にｂ図に示す如く、ガラス製
保持板１と離型剤２とめつき用導通層３とより成
る基材中のめつき用導通層３上に導電性の下部パ
ターンとなるべく銅層４をめつき処理にて被着さ
せる。尚基材は上記で例示したものに限らず、又
本発明に於ける配線基板とはこれらを含めたもの
も含めないものも両者を指称する。前記下部パタ
ーンは、回路の低抵抗化の要求から極力厚くする
ことが必要であり、処理速度の速い電解めつき法
を用いた。なお、めつき用導通体３及び銅層４の
形成に蒸着法及びスパツタリング法を用いて、そ
れぞれの金属を被着することも有効である。次
に、銅層４の上面にエツチングレジスト液を塗布
し、乾燥、露光、現像処理を行なつて、ｃ図に示
す如くエツチングレジスト膜５を形成する。次
に、当該エツチングレジスト膜５をレジストにし
て銅層４をエツチングし、エツチングレジスト膜
５を除去することにより、ｄ図に示す如く所望パ
ターンを有する下部パターン６，６′，６″，６ In FIG. 1a, a release agent 2 such as wax, which has a low adhesion to glass, is applied to the upper surface of a flattened glass holding plate 1 using a rotary coating machine so as to have a uniform thickness. Thereafter, the upper surface of the mold release agent 2 is activated with an activating solution containing palladium chloride, and a plating conductive layer 3 formed of a tin layer is deposited on the entire surface by electroless plating. In this case, the mold release agent 2
The other conductive layers deposited on the back and side surfaces of the holding plate 1 are removed by etching after performing an etching resist treatment on the taming conductive layer 3 deposited on the mold release agent 2. In addition, this conductive layer for plating is intended to be a conductive layer for the electrolytic plating process that will be performed in the subsequent process, and is made of a material that will not be etched away at the same time as the etching process of the lower pattern, which will be explained in the next process. If available, metals other than tin may be used. Furthermore, from the viewpoint of electroless plating properties, it is also effective to form a copper layer as a base layer and then form a tin layer thereon. Next, as shown in Figure b, a copper layer 4 is formed to form a conductive lower pattern on the conductive layer 3 for plating in the base material consisting of the glass holding plate 1, the mold release agent 2, and the conductive layer 3 for plating. It is applied by plating process. Note that the base material is not limited to those exemplified above, and the term "wiring board" in the present invention refers to both those that include and those that do not. The lower pattern needed to be as thick as possible due to the demand for low resistance of the circuit, so electrolytic plating, which has a high processing speed, was used. Note that it is also effective to use a vapor deposition method and a sputtering method to form the plating conductor 3 and the copper layer 4 to deposit the respective metals. Next, an etching resist solution is applied to the upper surface of the copper layer 4, followed by drying, exposure, and development to form an etching resist film 5 as shown in FIG. Next, the copper layer 4 is etched using the etching resist film 5 as a resist, and by removing the etching resist film 5, the lower patterns 6, 6', 6'', 6 have a desired pattern as shown in FIG.
Claims (1)
るとともに、該離型剤上にめつき用導通層が被着
されてなる、下記の上部パターン形成後に除去さ
れる基材に、 (1) 該基材中のめつき用導通層上に形成した銅層
を、エツチングレジスト膜をレジストにしてエ
ツチングして形成された下部パターンと、 (2) 該下部パターンの所要位置に対してめつきレ
ジスト膜のホトエツチングプロセスにより形成
された導通体と、 (3) 該導通体の形成に伴い前記めつきレジスト膜
が除去された位置と同位置に形成された絶縁性
樹脂層と、 (4) 該絶縁性樹脂層および導通体の同一面上に形
成された銅層を、エツチングレジスト膜をレジ
ストにしてエツチングすることにより、前記導
通体を介して下部パターンに接続するように形
成された上部パターンと、 を設けた積層接合可能な両面パターン基板からな
る多層配線基板。 ２ ガラス製保持板の片面に、離型剤が塗布され
るとともに、該離型剤上にめつき用導通層が被着
されてなる、下記の上部パターン形成後に除去さ
れる基材に、 (1) 該基材中のめつき用導通層上に形成した銅層
を、エツチングレジスト膜をレジストにしてエ
ツチングして形成された下部パターンと、 (2) 該下部パターンの所要位置に対してめつきレ
ジスト膜のホトエツチングプロセスにより形成
された導通体と、 (3) 該導通体の形成に伴い前記めつきレジスト膜
が除去された位置と同位置に形成された絶縁性
樹脂層と、 (4) 該絶縁性樹脂層および導通体の同一面上に形
成された銅層を、エツチングレジスト膜をレジ
ストにしてエツチングすることにより、前記導
通体を介して下部パターンに接続するように形
成された上部パターンと、 (5) 該上部パターン上にめつき処理にて上端面を
露出するように形成された接続端子と、 を設けた積層接合可能な接続端子付の両面パター
ン基板からなる多層配線基板。[Scope of Claims] 1. A mold release agent is applied to one side of a glass holding plate, and a conductive layer for plating is applied on the mold release agent, which is removed after the following upper pattern is formed. (1) a lower pattern formed by etching the copper layer formed on the conductive layer for plating in the base material using an etching resist film as a resist; and (2) a lower pattern formed on the lower pattern. (3) A conductor formed at a desired position by a photo-etching process of a plating resist film, and (3) an insulator formed at the same position where the plating resist film was removed when the conductor was formed. and (4) connecting the copper layer formed on the same surface of the insulating resin layer and the conductor to the lower pattern via the conductor by etching the copper layer using an etching resist film as a resist. A multilayer wiring board consisting of an upper pattern formed as shown in FIG. 2 A mold release agent is coated on one side of a glass holding plate, and a conductive layer for plating is adhered on the mold release agent, and the base material to be removed after the formation of the upper pattern described below is coated with ( 1) a lower pattern formed by etching the copper layer formed on the conductive layer for plating in the base material using an etching resist film as a resist; (3) an insulating resin layer formed at the same position where the plated resist film was removed when forming the conductor; (4) ) The copper layer formed on the same surface of the insulating resin layer and the conductor is etched using an etching resist film as a resist, thereby forming an upper part connected to the lower pattern via the conductor. A multilayer wiring board comprising a double-sided pattern board with connection terminals that can be laminated and bonded, and (5) connection terminals formed on the upper pattern by plating so as to expose the upper end surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP220382A JPS58121698A (en) | 1982-01-12 | 1982-01-12 | Multilayer printed board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP220382A JPS58121698A (en) | 1982-01-12 | 1982-01-12 | Multilayer printed board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58121698A JPS58121698A (en) | 1983-07-20 |
| JPH0544199B2 true JPH0544199B2 (en) | 1993-07-05 |
Family
ID=11522793
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP220382A Granted JPS58121698A (en) | 1982-01-12 | 1982-01-12 | Multilayer printed board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58121698A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6062193A (en) * | 1983-09-14 | 1985-04-10 | 松下電工株式会社 | Method of producing multilayer printed circuit board |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS497758A (en) * | 1972-05-15 | 1974-01-23 | ||
| JPS4922552A (en) * | 1972-06-26 | 1974-02-28 | ||
| JPS5064767A (en) * | 1973-10-12 | 1975-06-02 | ||
| JPS5662398A (en) * | 1979-10-26 | 1981-05-28 | Nippon Electric Co | Method of manufacturing high density multilayer board |
| JPS56116697A (en) * | 1980-02-19 | 1981-09-12 | Nippon Electric Co | Method of forming conductor layer on multilayer circuit board |
-
1982
- 1982-01-12 JP JP220382A patent/JPS58121698A/en active Granted
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS497758A (en) * | 1972-05-15 | 1974-01-23 | ||
| JPS4922552A (en) * | 1972-06-26 | 1974-02-28 | ||
| JPS5064767A (en) * | 1973-10-12 | 1975-06-02 | ||
| JPS5662398A (en) * | 1979-10-26 | 1981-05-28 | Nippon Electric Co | Method of manufacturing high density multilayer board |
| JPS56116697A (en) * | 1980-02-19 | 1981-09-12 | Nippon Electric Co | Method of forming conductor layer on multilayer circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58121698A (en) | 1983-07-20 |
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