JPH0555750A - Multilayer printed circuit board and manufacture of the same - Google Patents
Multilayer printed circuit board and manufacture of the sameInfo
- Publication number
- JPH0555750A JPH0555750A JP21202591A JP21202591A JPH0555750A JP H0555750 A JPH0555750 A JP H0555750A JP 21202591 A JP21202591 A JP 21202591A JP 21202591 A JP21202591 A JP 21202591A JP H0555750 A JPH0555750 A JP H0555750A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- circuit conductor
- conductor layer
- metal
- palladium
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manufacturing Of Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は広範な電子機器に用いら
れる多層プリント配線板とその製造方法に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board used in a wide variety of electronic devices and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】近年、電子機器の小型軽量化や高性能
化，高機能化のニーズが増大し、それに伴って高度な多
層プリント配線板の需要が著しく増加している。2. Description of the Related Art In recent years, there has been an increasing need for electronic devices to be smaller and lighter, to have higher performance, and to have higher functions, and accordingly, the demand for sophisticated multilayer printed wiring boards has significantly increased.
【０００３】このような中にあって、昨今いろいろな多
層プリント配線板が使用されているが、その代表的なも
のとして図４に示すものがある。図４において、１は絶
縁基板、２は金属銅からなる内層の配線回路導体層、３
は絶縁樹脂層、４は最外層の配線回路導体層、５は貫通
穴である。Under such circumstances, various multilayer printed wiring boards have been used these days, and a typical one is shown in FIG. In FIG. 4, 1 is an insulating substrate, 2 is an inner wiring circuit conductor layer made of metallic copper, 3
Is an insulating resin layer, 4 is an outermost wiring circuit conductor layer, and 5 is a through hole.
【０００４】このような従来例による多層プリント配線
板は、ガラスエポキシ積層板等の合成樹脂系の絶縁基板
１の表裏両面全体に予め金属銅箔を接着したいわゆる銅
張り積層板を出発材料として、フォトエッチング法等の
公知の方法によって先ず絶縁基板１の表裏両面層に金属
銅箔からなる所望とする配線図形状の内層の配線回路導
体層２を構成し、その表面に薄いガラス繊維シートにエ
ポキシ樹脂を含漬して半硬化状態とした絶縁樹脂層３を
構成してさらにその表面に金属銅からなる最外層の配線
回路導体層４を構成し、層間の配線回路導体層を貫通す
る穴５を導通化することによって電気的に相互接続した
ものである。The multilayer printed wiring board according to the conventional example described above uses a so-called copper-clad laminate in which metallic copper foils are preliminarily adhered to both front and back surfaces of a synthetic resin-based insulating substrate 1 such as a glass epoxy laminate, as a starting material. First, by a known method such as a photo-etching method, an inner wiring circuit conductor layer 2 of a desired wiring diagram shape made of a metal copper foil is formed on both front and back surface layers of the insulating substrate 1, and a thin glass fiber sheet is coated with epoxy on the surface thereof. A semi-cured insulating resin layer 3 is formed by impregnating a resin, and an outermost wiring circuit conductor layer 4 made of metallic copper is formed on the surface of the insulating resin layer 3. A hole 5 penetrating the wiring circuit conductor layers between layers is formed. Are electrically connected to each other by making them conductive.
【０００５】[0005]
【発明が解決しようとする課題】上記の従来例では内層
の回路導体層２と絶縁樹脂層３との密着性を良好に保つ
ために、通常は内層の回路導体層２を構成する銅箔表面
に酸化層を形成してその表面を粗面化することによって
絶縁樹脂層３との密着性を高める方法がとられている。
しかしながらこのような内層の回路導体層２に酸化膜を
形成したものではその導体層を貫通する穴を導通化した
場合、貫通穴５の壁面に露出した酸化銅膜がスルーホー
ルめっき工程における各種薬品処理で溶出し、絶縁樹脂
層１３との間に空隙が生じいわゆるハローイング現象が
生じることや、絶縁樹脂層３への銅のマイグレーション
によって多層プリント配線板の層間絶縁の信頼性が著し
く損なわれることや、酸化銅処理を行うには高温，強ア
ルカリ中での処理を必要とし、大変危険な作業を伴うば
かりでなくアルカリ溶液に基板を浸漬することによって
絶縁基板材料の電気絶縁特性が著しく劣化すること等の
問題点を有していた。In the above-mentioned conventional example, in order to maintain good adhesion between the inner circuit conductor layer 2 and the insulating resin layer 3, the surface of the copper foil forming the inner circuit conductor layer 2 is usually formed. A method of increasing the adhesiveness with the insulating resin layer 3 is formed by forming an oxide layer on the surface and roughening the surface.
However, in the case where an oxide film is formed on the inner circuit conductor layer 2 as described above, when the hole penetrating the conductor layer is made conductive, the copper oxide film exposed on the wall surface of the through hole 5 causes various chemicals in the through hole plating step. It is eluted during the treatment, a void is formed between the insulating resin layer 13 and the so-called haloing phenomenon, and the migration of copper to the insulating resin layer 3 significantly impairs the reliability of interlayer insulation of the multilayer printed wiring board. In addition, copper oxide treatment requires high temperature and strong alkali treatment, which not only involves extremely dangerous work, but also dips the substrate in an alkaline solution, which significantly deteriorates the electrical insulation characteristics of the insulating substrate material. There was a problem such as that.
【０００６】また一方、従来例による多層プリント配線
板はその最外層の配線回路導体層４は通常、金属銅によ
って構成されたものであるが、金属銅は一般に酸化され
易い金属であるため、最終仕上げ工程でその表面に耐熱
性を有するプリフラックスやはんだレベラー等の防錆処
理を施し、はんだ付けを良好に保つ方策がとられてい
る。しかしながら、このようなフラックスやはんだレベ
ラーによる銅箔の防錆法でははんだ付け性は必ずしも満
足のいくものではなく、はんだ付作業を繰り返し行う熱
履歴によってはんだ付け性が著しく劣化し、良好なはん
だ付け性が得られないという問題点があった。On the other hand, in the multilayer printed wiring board according to the conventional example, the outermost wiring circuit conductor layer 4 is usually made of metallic copper. In the finishing process, the surface is subjected to rust-preventive treatment such as heat-resistant preflux or solder leveler, and measures are taken to maintain good soldering. However, the rust prevention method of copper foil by such flux and solder leveler is not always satisfactory in solderability, and the heat history of repeating the soldering work significantly deteriorates the solderability, resulting in good soldering. There was a problem that the sex was not obtained.
【０００７】本発明は上記従来の欠点を解決して、層間
絶縁の信頼性と、はんだ付け性に優れた多層プリント配
線板とその製造方法を提供することを目的としたもので
ある。An object of the present invention is to solve the above-mentioned conventional drawbacks and to provide a multilayer printed wiring board excellent in reliability of interlayer insulation and solderability and a manufacturing method thereof.
【０００８】[0008]
【課題を解決するための手段】この目的を達成するため
に本発明は、絶縁基板の少なくとも一方の主面上に絶縁
樹脂層と金属銅からなる配線回路導体層とを交互に形成
して構成し、前記回路導体面に金属パラジウムの薄膜層
を形成したものである。In order to achieve this object, the present invention is constructed by alternately forming an insulating resin layer and a wiring circuit conductor layer made of metallic copper on at least one main surface of an insulating substrate. Then, a thin film layer of metallic palladium is formed on the circuit conductor surface.
【０００９】[0009]
【作用】本発明によれば金属パラジウムの薄膜層を内層
の配線回路導体層の表面上に被覆することによって、層
間絶縁樹脂層への銅金属のマイグレーションが皆無とな
り、回路導体層と層間絶縁樹脂層の密着性が向上して層
間絶縁の信頼性が改善されると共に、最外層の配線回路
導体層に金属パラジウムの薄膜層を被覆することによっ
てはんだ付け性が改善され信頼性に優れた多層プリント
配線板が実現されることとなる。According to the present invention, by coating a thin film layer of metallic palladium on the surface of the inner wiring circuit conductor layer, the migration of copper metal to the interlayer insulating resin layer is eliminated, and the circuit conductor layer and the interlayer insulating resin layer are eliminated. The adhesion of layers is improved and the reliability of interlayer insulation is improved, and the outermost wiring circuit conductor layer is covered with a thin film layer of metallic palladium to improve solderability and multilayer printing with excellent reliability. A wiring board will be realized.
【００１０】[0010]
【実施例】（実施例１）以下、本発明の一実施例の多層
プリント配線板とその製造方法について図面を参照しな
がら説明する。図１は本発明の第１の実施例における多
層プリント配線板を示すものである。図１において、６
は絶縁基板、７は内層の配線回路導体層、８は金属パラ
ジウム層、９は絶縁樹脂層、１０は最外層の配線回路導
体層、１１は貫通穴である。(Embodiment 1) Hereinafter, a multilayer printed wiring board according to an embodiment of the present invention and a method for manufacturing the same will be described with reference to the drawings. FIG. 1 shows a multilayer printed wiring board according to the first embodiment of the present invention. In FIG. 1, 6
Is an insulating substrate, 7 is an inner wiring circuit conductor layer, 8 is a metal palladium layer, 9 is an insulating resin layer, 10 is an outermost wiring circuit conductor layer, and 11 is a through hole.
【００１１】以上の構成からなる多層プリント配線板は
ガラスエポキシ積層板やガラスポリイミド積層板等の樹
脂系の絶縁基板６の表裏両面にフォトエッチング法等の
公知の方法によって金属銅箔から内層の配線回路導体層
７を設け、この内層の配線回路導体層７の表面層に厚さ
０．０５〜１μｍ程度の金属パラジウムの薄膜層８を被
覆した後で、その表面に例えばガラス繊維シートにエポ
キシ樹脂を含漬した絶縁樹脂層９を設けて、さらにこの
絶縁樹脂層９の表面に金属銅箔からなる最外層の配線回
路導体層１０を構成し、貫通穴１１を導通化することに
よって内層の配線回路導体層７と電気的に相互接続した
ものである。The multilayer printed wiring board having the above-mentioned structure is formed by wiring a metal copper foil to an inner layer by a known method such as photoetching on both front and back surfaces of a resin-based insulating substrate 6 such as a glass epoxy laminated board or a glass polyimide laminated board. A circuit conductor layer 7 is provided, and a surface layer of the wiring circuit conductor layer 7 as an inner layer is covered with a thin film layer 8 of metallic palladium having a thickness of about 0.05 to 1 μm. An insulating resin layer 9 in which is impregnated is provided, and further, an outermost wiring circuit conductor layer 10 made of a metal copper foil is formed on the surface of the insulating resin layer 9, and the through hole 11 is made conductive, thereby wiring the inner layer. It is electrically connected to the circuit conductor layer 7.
【００１２】この場合、内層の金属銅箔からなる配線回
路導体層７の表面に被覆する金属パラジウムの薄膜層８
は無電解めっき法によって析出させた。In this case, the metal palladium thin film layer 8 covering the surface of the wiring circuit conductor layer 7 made of the inner metal copper foil.
Was deposited by electroless plating.
【００１３】そしてこの無電解パラジウムめっき条件の
実施例の１例を下記に示した。 〈無電解パラジウムめっき浴〉 塩化パラジウム ０．０１〜０．０２モル／ｌ エチレンジアミン ０．０８〜０．１０モル／ｌ 次亜リン酸ソーダ ０．０６〜０．０８モル／ｌ 浴ＰＨ ８〜９ 浴温度 ５０℃ また、この無電解パラジウムめっきを行う前処理として
金属銅層の表面には予め無電解めっき法によってニッケ
ル金属を約１μ程度の厚さに析出させておくことにより
銅とパラジウムの安定した密着性が得られた。An example of an example of the electroless palladium plating condition is shown below. <Electroless Palladium Plating Bath> Palladium chloride 0.01 to 0.02 mol / l Ethylenediamine 0.08 to 0.10 mol / l Sodium hypophosphite 0.06 to 0.08 mol / l Bath PH 8 to 9 Bath temperature 50 ° C As a pretreatment for this electroless palladium plating, nickel metal is deposited in advance to a thickness of about 1 μm on the surface of the metal copper layer by electroless plating to stabilize copper and palladium. Adhesion was obtained.
【００１４】このような金属パラジウム層８を介してそ
の表面に絶縁樹脂層を構成することにより、絶縁樹脂層
９と内層の配線回路導体層７の密着性が著しく改善され
る理由としては、無電解めっき法によって析出した金属
パラジウム層８の表面が極めて微細に粗面化された表面
状態を呈し、且つパラジウム金属は耐腐食性に優れた金
属であるため、層間の絶縁樹脂中に含まれるナトリウム
やカリウム等のアルカリ金属類等により内層の回路を構
成する銅金属の腐食を防止する効果によって良好な密着
性が得られるものである。The reason why the adhesion between the insulating resin layer 9 and the inner wiring circuit conductor layer 7 is remarkably improved by forming the insulating resin layer on the surface of the metallic palladium layer 8 is as follows. Since the surface of the metal palladium layer 8 deposited by the electrolytic plating method has a very finely roughened surface state and the palladium metal is a metal having excellent corrosion resistance, sodium contained in the interlayer insulating resin is used. Good adhesion can be obtained by the effect of preventing the corrosion of the copper metal forming the inner layer circuit by the alkali metals such as potassium and potassium.
【００１５】そして、内層の配線回路導体層７を貫通し
た穴の内壁面を導通化する工程において、貫通穴１１に
露出した内層の配線回路導体層の表面層がパラジウム金
属層で覆われているため、酸化銅層の溶出によるハロー
イング現象や銅金属の絶縁樹脂層９へのマイグレーショ
ンが防止され、信頼性に極めて優れた多層プリント配線
板が構成できるものである。In the step of making the inner wall surface of the hole penetrating the inner wiring circuit conductor layer 7 conductive, the surface layer of the inner wiring circuit conductor layer exposed in the through hole 11 is covered with the palladium metal layer. Therefore, the haloing phenomenon due to the elution of the copper oxide layer and the migration of copper metal to the insulating resin layer 9 are prevented, and a multilayer printed wiring board having extremely excellent reliability can be configured.
【００１６】（実施例２）次に本発明の他の実施例につ
いて説明する。(Embodiment 2) Next, another embodiment of the present invention will be described.
【００１７】図２は本発明の第２の実施例を説明するた
めの多層プリント配線板の断面図である。FIG. 2 is a sectional view of a multilayer printed wiring board for explaining the second embodiment of the present invention.
【００１８】図２において、図１と同一箇所については
同一符号を用いている。図１と異なる点は、金属パラジ
ウムの薄膜層８を最外層の配線回路導体層１０の表面に
も被覆したことである。In FIG. 2, the same parts as those in FIG. 1 are designated by the same reference numerals. The difference from FIG. 1 is that the metal palladium thin film layer 8 is also coated on the surface of the outermost wiring circuit conductor layer 10.
【００１９】これによって、最外層の配線回路導体層１
０の防錆効果がより一層向上し、プリフラックス塗布や
はんだレベラー処理を行わなくても良好なはんだ付け性
が得られ、特に繰り返しの熱履歴による回路導体層の酸
化による変色が防止でき、はんだ付け性が著しく改善さ
れる効果が得られることが明らかとなった。As a result, the outermost wiring circuit conductor layer 1
The rust prevention effect of No. 0 is further improved, good solderability can be obtained without applying pre-flux coating or solder leveler treatment, and discoloration due to oxidation of the circuit conductor layer due to repeated thermal history can be prevented. It was clarified that the effect of remarkably improving the attachability was obtained.
【００２０】なお、この場合も最外層の配線回路導体層
１０に金属パラジウム薄膜層８を被覆する前に無電解ニ
ッケル層を金属銅層の表面に薄く被覆しておくことによ
りパラジウムめっきの均一性が得られ良好なはんだ付け
性が得られた。In this case as well, even before the outermost wiring circuit conductor layer 10 is covered with the metallic palladium thin film layer 8, the electroless nickel layer is thinly coated on the surface of the metallic copper layer, so that the uniformity of palladium plating is improved. And good solderability was obtained.
【００２１】なお、上記実施例１，２では多層配線基板
を構成する絶縁基板６としてガラスエポキシ基材等の樹
脂系基板材料を使用したが、この絶縁基板材料は樹脂系
に限定されるものではなく、例えばアルミナ等のセラミ
ック基板を使用し、その表面に金属銅と絶縁樹脂層９を
交互に形成して構成の多層プリント配線板にも適用され
るものである。In Examples 1 and 2 described above, a resin-based substrate material such as a glass epoxy base material was used as the insulating substrate 6 constituting the multilayer wiring board, but the insulating substrate material is not limited to the resin-based material. Instead, it is also applicable to a multilayer printed wiring board in which a ceramic substrate such as alumina is used and metallic copper and insulating resin layers 9 are alternately formed on the surface thereof.
【００２２】また、このような最外層の配線回路導体層
１０に金属パラジウム層を構成することによってコネク
ターや各種スイッチの接点回路を備えた高機能多層プリ
ント配線板として使用することも可能になり、付加価値
が著しく向上するものである。Further, by forming a metal palladium layer on the outermost wiring circuit conductor layer 10 as described above, it becomes possible to use it as a high-performance multilayer printed wiring board having contact circuits for connectors and various switches. The added value is remarkably improved.
【００２３】（実施例３）さらに、本発明の他の実施例
について説明する。(Embodiment 3) Another embodiment of the present invention will be described.
【００２４】図３（Ａ）〜（Ｃ）は本発明の第３の実施
例を説明するための多層プリント配線板の製造工程を説
明するための主要製造工程の断面図である。3 (A) to 3 (C) are sectional views of the main manufacturing steps for explaining the manufacturing steps of the multilayer printed wiring board for explaining the third embodiment of the present invention.
【００２５】図３において、１２は絶縁基板、１３は内
層の配線回路導体層、１４は層間絶縁樹脂層、１５は金
属銅箔、１６は貫通穴、１７は導電金属層、１８はレジ
スト層、１９は金属パラジウム層である。In FIG. 3, 12 is an insulating substrate, 13 is an inner wiring circuit conductor layer, 14 is an interlayer insulating resin layer, 15 is a metal copper foil, 16 is a through hole, 17 is a conductive metal layer, 18 is a resist layer, Reference numeral 19 is a metal palladium layer.
【００２６】本実施例では、先ず図３（Ａ）に示すよう
にガラスエポキシ積層板やガラスポリイミド積層板等の
合成樹脂系の絶縁基板１２の表面両面に金属銅箔を接着
したいわゆる銅張り積層板を出発材料としてまずフォト
エッチング法等の公知の方法によって絶縁基板１２の表
面両面層に所望とする内層の配線回路導体層１３を形成
する。次いでこの内層の配線回路導体層１３の表面に酸
化銅層を形成するか、または前述の無電解パラジウムめ
っき法によって金属パラジウムの薄膜層を形成した後
で、その表面にガラス繊維シートにエポキシ樹脂を含漬
して半硬化状態としたプリプレグ絶縁樹脂層１４と金属
銅箔１５を積層して真空熱プルスによって一体成型し、
必要な箇所に貫通穴１６を開けてその内壁面を含む基板
全体に無電解銅めっきと電解銅めっきを併用して金属銅
からなる導電金属層１７を析出した。In this embodiment, first, as shown in FIG. 3A, a so-called copper-clad laminate in which metallic copper foil is adhered to both surfaces of a synthetic resin type insulating substrate 12 such as a glass epoxy laminate plate or a glass polyimide laminate plate. Using the plate as a starting material, first, a desired inner wiring circuit conductor layer 13 is formed on both surface layers of the insulating substrate 12 by a known method such as a photoetching method. Then, a copper oxide layer is formed on the surface of the inner wiring circuit conductor layer 13 or a thin film layer of metallic palladium is formed by the above-mentioned electroless palladium plating method, and then a glass fiber sheet is coated with an epoxy resin on the surface. The prepreg insulating resin layer 14 and the metal copper foil 15 which are soaked in a semi-cured state are laminated and integrally molded by vacuum heat pulling,
A through-hole 16 was formed at a required position, and electroless copper plating and electrolytic copper plating were used together to deposit a conductive metal layer 17 made of metallic copper on the entire substrate including the inner wall surface thereof.
【００２７】そしてこの導電金属層１７の表面にスクリ
ーン印刷法や、フォト法によって逆配線図形状に耐めっ
き性のレジスト層１８を形成し、しかる後に上述した浴
組成の無電解パラジウムめっき液に浸漬して図３Ｂに示
すようレジスト層１８が被覆していない配線図形状の導
電金属層１７の表面に金属パラジウム層１９を薄く均一
に析出させた。この場合、無電解パラジウムめっきを行
う前には金属銅層の表面には無電解ニッケルめっきを施
し、このニッケル金属層の表面に無電解パラジウムめっ
きを行った。この金属パラジウム層１９はエッチング液
によって配線回路導体層が侵されないようにピンホール
のない均一な厚さにする必要があるが、本実施例ではこ
の厚さを最低１μｍ以上行った。Then, a resist layer 18 having a resistance to plating is formed in a reverse wiring diagram shape on the surface of the conductive metal layer 17 by a screen printing method or a photo method, and then immersed in the electroless palladium plating solution having the above-mentioned bath composition. Then, as shown in FIG. 3B, a metal palladium layer 19 was thinly and uniformly deposited on the surface of the conductive metal layer 17 having a wiring diagram shape not covered with the resist layer 18. In this case, the electroless nickel plating was performed on the surface of the metal copper layer before the electroless palladium plating, and the electroless palladium plating was performed on the surface of the nickel metal layer. The metal palladium layer 19 needs to have a uniform thickness without pinholes so that the wiring circuit conductor layer is not attacked by the etching solution, but in this embodiment, this thickness is at least 1 μm or more.
【００２８】それから、図３（Ｃ）に示すように無電解
パラジウムめっき液は耐めっき性のレジスト層１８を溶
剤等で除去し、露出した導電金属銅層１７と金属銅箔層
１５を金属ハラジウム層１９を溶解しないエッチング液
として例えば塩化第２鉄溶液や塩化第１銅溶液またはア
ンモニア系のアルカリ性エッチング液中に浸漬して溶解
除去することによって最外層の配線回路導体層を形成し
た。Then, as shown in FIG. 3C, the electroless palladium plating solution is used to remove the plating resistant resist layer 18 with a solvent or the like, and the exposed conductive metal copper layer 17 and metal copper foil layer 15 are removed from the metal haladium. The outermost wiring circuit conductor layer was formed by immersing and removing the layer 19 as an etching solution that does not dissolve, for example, a ferric chloride solution, a cuprous chloride solution, or an ammonia-based alkaline etching solution.
【００２９】このような多層プリント配線板は、従来の
はんだめっきレジスト法によるパターンめっき方法と比
べ、パラジウム金属をレジスト金属とするため材料コス
トは高くつくが、無電解めっき法によってパラジウム金
属を析出させるために設備費用が安価になることはもと
より、極めて小径の穴内や微細な回線回路導体面にも極
めて短時間に均一な厚さの金属パラジウム層を析出させ
ることができるので、より高密度ではんだ付け特性に優
れた多層プリント配線板を作ることができるものであ
る。In such a multilayer printed wiring board, palladium metal is used as a resist metal in comparison with the conventional pattern plating method using a solder plating resist method, but the material cost is high, but palladium metal is deposited by electroless plating. As a result, not only is the equipment cost low, but it is also possible to deposit a metal palladium layer of a uniform thickness in an extremely small diameter hole or on a fine circuit circuit conductor surface in an extremely short time, so soldering with higher density is possible. It is possible to make a multilayer printed wiring board having excellent attachment characteristics.
【００３０】また一方この多層プリント配線板の製造方
法ではパラジウムめっき浴がほぼ中性で行うことができ
るため、使用する耐めっき性レジストの耐薬品性が大幅
に緩和されレジスト樹脂材料の選択幅が広がる利点が得
られるものである。On the other hand, in this method for manufacturing a multilayer printed wiring board, since the palladium plating bath can be performed almost neutrally, the chemical resistance of the plating resistant resist to be used is greatly relaxed and the selection range of the resist resin material is increased. The advantage is that it spreads.
【００３１】[0031]
【発明の効果】以上の説明から明らかなように本発明に
よる多層プリント配線板は、絶縁樹脂層と金属銅からな
る内層または最外層の配線回路導体層の表面に金属パラ
ジウムの薄膜層を被覆したものであり、内層の配線回路
導体面にパラジウム層を構成することによって層間絶縁
層との密着性が著しく改善され、かつ層間絶縁層への銅
金属のマイグレーション，ハローイング現象の防止等従
来例にない特別の効果が得られるものである。As is apparent from the above description, in the multilayer printed wiring board according to the present invention, the surface of the inner or outermost wiring circuit conductor layer made of the insulating resin layer and metallic copper is coated with the thin film layer of metallic palladium. By forming the palladium layer on the inner surface of the wiring circuit conductor surface, the adhesion with the interlayer insulating layer is significantly improved, and the migration of copper metal to the interlayer insulating layer and the prevention of haloing phenomenon are achieved. There is no special effect.
【００３２】また一方、本発明による最外層の配線回路
導体層の形成において無電解めっきによる金属パラジウ
ムを貫通穴を含む配線回路状に露出した金属銅からなる
導電金属層上に被覆してエッチングレジストとする方法
では、従来のはんだ金属を電気めっき法によって形成す
る方法に比べ、無電解めっき法によってレジスト金属層
を構成するため、製造設備が簡素化され、経済性に優れ
ると共に、レジスト金属層の膜厚が均一に構成されるの
で小径穴や微細な配線回路導体層の形成が可能である。
また最外層の配線回路導体層の表面層はエッチングレジ
ストに用いたパラジウム金属層が残留するため、はんだ
付け性が大幅に改善される効果が得られるものである。On the other hand, in the formation of the outermost wiring / circuit conductor layer according to the present invention, a metal palladium formed by electroless plating is coated on a conductive metal layer made of metal copper exposed in a wiring circuit shape including a through hole to form an etching resist. In the method, the resist metal layer is formed by the electroless plating method as compared with the conventional method of forming the solder metal by the electroplating method, which simplifies the manufacturing equipment and is excellent in economic efficiency. Since the film thickness is uniform, it is possible to form small diameter holes and fine wiring circuit conductor layers.
Further, since the palladium metal layer used as the etching resist remains on the surface layer of the outermost wiring circuit conductor layer, the solderability is greatly improved.
【図１】本発明の第１の実施例における多層プリント配
線板の要部断面図FIG. 1 is a sectional view of an essential part of a multilayer printed wiring board according to a first embodiment of the present invention.
【図２】本発明の第２実施例における多層プリント配線
板の要部断面図FIG. 2 is a sectional view of an essential part of a multilayer printed wiring board according to a second embodiment of the present invention.
【図３】（Ａ），（Ｂ），（Ｃ）はそれぞれ本発明の多
層プリント配線板の製造方法を説明する工程断面図3 (A), (B), and (C) are process cross-sectional views illustrating a method for manufacturing a multilayer printed wiring board according to the present invention.
【図４】従来の多層プリント配線板の要部断面図FIG. 4 is a sectional view of a main part of a conventional multilayer printed wiring board.
６，１２ 絶縁基板 ７，１３ 内層の配線回路導体層 ８，１９ 金属パラジウム層 ９，１４ 絶縁樹脂層 １０ 最外層の配線回路導体層 １１，１６ 貫通穴 １５ 金属銅箔 １７ 導電金属層 １８ レジスト層 6,12 Insulating substrate 7,13 Inner wiring circuit conductor layer 8,19 Metal palladium layer 9,14 Insulating resin layer 10 Outermost wiring circuit conductor layer 11,16 Through hole 15 Metal copper foil 17 Conductive metal layer 18 Resist layer
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０５Ｋ 3/42 Ａ 6736−4Ｅ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H05K 3/42 A 6736-4E
Claims (5)
樹脂層と金属銅からなる回路導体層とを交互に形成して
構成し、前記回路導体層の表面に金属パラジウムの薄膜
層を形成したことを特徴とする多層プリント配線板。1. An insulating resin layer and a circuit conductor layer made of metal copper are alternately formed on at least one main surface of an insulating substrate, and a metal palladium thin film layer is formed on the surface of the circuit conductor layer. A multilayer printed wiring board characterized by the above.
薄層を被覆した請求項１記載の多層プリント配線板。2. The multilayer printed wiring board according to claim 1, wherein the inner surface of the wiring circuit conductor surface is covered with a thin layer of metallic palladium.
の薄層を被覆した請求項１記載の多層プリント配線板。3. The multilayer printed wiring board according to claim 1, wherein the outermost wiring circuit conductor surface is covered with a thin layer of metallic palladium.
よって形成したことを特徴とする多層プリント配線板の
製造方法。4. A method for manufacturing a multilayer printed wiring board, wherein the thin layer of metallic palladium is formed by an electroless plating method.
した貫通穴の内壁面に金属銅からなる導体層を形成し、
この導体層上に無電解めっき法によって金属パラジウム
薄層を所望とする回路導体の形状に形成し、その後パラ
ジウム薄層で覆われていない露出した導体層を溶解除去
することを特徴とした多層プリント配線板の製造方法。5. A conductor layer made of metallic copper is formed on the entire surface of the insulating resin layer and on the inner wall surface of the through hole formed in the insulating resin layer,
A multilayer print characterized in that a thin metal palladium layer is formed on this conductor layer by electroless plating in the shape of a desired circuit conductor, and then the exposed conductor layer not covered with the thin palladium layer is dissolved and removed. Wiring board manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21202591A JPH0555750A (en) | 1991-08-23 | 1991-08-23 | Multilayer printed circuit board and manufacture of the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21202591A JPH0555750A (en) | 1991-08-23 | 1991-08-23 | Multilayer printed circuit board and manufacture of the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0555750A true JPH0555750A (en) | 1993-03-05 |
Family
ID=16615626
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21202591A Pending JPH0555750A (en) | 1991-08-23 | 1991-08-23 | Multilayer printed circuit board and manufacture of the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0555750A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09102677A (en) * | 1995-08-25 | 1997-04-15 | Macdermid Inc | Manufacture of printed circuit board |
| US5878487A (en) * | 1996-09-19 | 1999-03-09 | Ford Motor Company | Method of supporting an electrical circuit on an electrically insulative base substrate |
| WO2021111590A1 (en) * | 2019-12-05 | 2021-06-10 | ベジ 佐々木 | Laminate, method for producing patterned substrate, electronic device and package device |
-
1991
- 1991-08-23 JP JP21202591A patent/JPH0555750A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09102677A (en) * | 1995-08-25 | 1997-04-15 | Macdermid Inc | Manufacture of printed circuit board |
| US5878487A (en) * | 1996-09-19 | 1999-03-09 | Ford Motor Company | Method of supporting an electrical circuit on an electrically insulative base substrate |
| WO2021111590A1 (en) * | 2019-12-05 | 2021-06-10 | ベジ 佐々木 | Laminate, method for producing patterned substrate, electronic device and package device |
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