JPH04144190A - Circuit board and manufacture thereof - Google Patents
Circuit board and manufacture thereofInfo
- Publication number
- JPH04144190A JPH04144190A JP26648890A JP26648890A JPH04144190A JP H04144190 A JPH04144190 A JP H04144190A JP 26648890 A JP26648890 A JP 26648890A JP 26648890 A JP26648890 A JP 26648890A JP H04144190 A JPH04144190 A JP H04144190A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- face
- solder
- nickel
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000007772 electroless plating Methods 0.000 claims abstract description 8
- 239000003054 catalyst Substances 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 37
- 239000012790 adhesive layer Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 6
- 238000009713 electroplating Methods 0.000 claims description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 25
- 239000010949 copper Substances 0.000 abstract description 16
- 229910000679 solder Inorganic materials 0.000 abstract description 16
- 239000010931 gold Substances 0.000 abstract description 13
- 229910052759 nickel Inorganic materials 0.000 abstract description 10
- 238000007747 plating Methods 0.000 abstract description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052802 copper Inorganic materials 0.000 abstract description 8
- 229910052737 gold Inorganic materials 0.000 abstract description 7
- 239000004020 conductor Substances 0.000 abstract description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 3
- 239000007864 aqueous solution Substances 0.000 abstract description 2
- RJTANRZEWTUVMA-UHFFFAOYSA-N boron;n-methylmethanamine Chemical compound [B].CNC RJTANRZEWTUVMA-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052763 palladium Inorganic materials 0.000 abstract description 2
- PIBWKRNGBLPSSY-UHFFFAOYSA-L palladium(II) chloride Chemical compound Cl[Pd]Cl PIBWKRNGBLPSSY-UHFFFAOYSA-L 0.000 abstract description 2
- 239000003638 chemical reducing agent Substances 0.000 abstract 1
- 239000007788 liquid Substances 0.000 abstract 1
- 230000007797 corrosion Effects 0.000 description 9
- 238000005260 corrosion Methods 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008642 heat stress Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Abstract
Description
配線基板およびその製造方法に関し、
接続パッドの半田溶食を防止することを目的とし、
密着層上にＣｕ−Ｎｉ −Ａｕの多層構造を有する接続
パッドを形成してなる配線基板において、前記Ｎｉ層を
無電解Ｎｉ−Ｂにて形成するように構成する。
また、その配線基板の製造方法を、
密着層上にＣｕ Ｎｉ−Ａｕの多層構造を有する接続
パッドを形成する配線基板の製造方法において、
前記Ｃｕ層を電解メッキにて形成した後、適宜の触媒を
該Ｃｕ層の露出部に吸着させ、次いでＮｉ−Ｂ、および
Ａｕ層を無電解メッキにて積層して構成する。Regarding a wiring board and its manufacturing method, in a wiring board in which a connection pad having a multilayer structure of Cu-Ni-Au is formed on an adhesive layer for the purpose of preventing solder corrosion of the connection pad, the Ni layer is is formed of electroless Ni-B. In addition, the method for manufacturing the wiring board includes forming a connection pad having a multilayer structure of Cu Ni-Au on the adhesive layer, and after forming the Cu layer by electrolytic plating, a suitable catalyst is applied. is adsorbed onto the exposed portion of the Cu layer, and then Ni--B and Au layers are laminated by electroless plating.
本発明は、配線基板、およびその製造方法に関するもの
である。The present invention relates to a wiring board and a method for manufacturing the same.
一般にプリント基板、セラミンク基板等の配線基板の回
路には、半田付用の接続パッドが設けられており、この
接続パッド２の膜構成は、従来、第２図に示すように、
電気抵抗の低さから導電層として使用される銅層４と、
Ｐｂ−３ｎ、Ｉｎ−３ｎ、Ｉｎ−Ｐｂ、Ａｕ−３ｎ等の
半田と銅層４の拡散防止のためのニッケル層３と、半田
濡れの長３ｔＪｌ確保を目的とする金層５とからなる多
層構造が取られていた。
なお、第２図において６は基材、１は密着層である。Generally, circuits on wiring boards such as printed circuit boards and ceramic boards are provided with connection pads for soldering, and the film structure of the connection pads 2 has conventionally been as shown in FIG.
a copper layer 4 used as a conductive layer due to its low electrical resistance;
Multilayer consisting of a nickel layer 3 for preventing diffusion of solder such as Pb-3n, In-3n, In-Pb, Au-3n, etc. and a copper layer 4, and a gold layer 5 for ensuring a solder wetting length of 3tJl. structure was taken. In addition, in FIG. 2, 6 is a base material, and 1 is an adhesive layer.
しかし、上述した接続パッド２は、スピンコ−ドにレジ
ストを塗布した後、電気メッキで銅メンキ、ニッケルメ
ンキ、金メッキをし、金をマスクとしてパネルエツチン
グをすることにより形成されるので、該接続パッド２の
端面には銅が露出したり、あるいはニッケルメッキ層３
の厚さにばらつきが生じ、半田付けの際に加えられる熱
ストレスにより半田溶食が進行し、断線、パッド脱落が
生じるという欠点を有するものであった。
本発明は、以上の欠点を解消すべくなされたものであっ
て、接続バッドの半田溶食を防止することができる配ｖ
Ａ基板およびその製造方法を提供することを目的とする
。However, the connection pad 2 described above is formed by applying resist to the spin cord, then electroplating with copper, nickel, and gold, and then performing panel etching using the gold as a mask. Copper is exposed on the end face, or nickel plating layer 3
This has disadvantages in that the thickness of the pads varies, and the heat stress applied during soldering progresses solder corrosion, leading to wire breakage and pad falling off. The present invention has been made in order to eliminate the above-mentioned drawbacks, and provides an arrangement that can prevent solder corrosion of connection pads.
The purpose of the present invention is to provide a substrate A and a method for manufacturing the same.
本発明によれば上記目的は、実施例に対応する第１図（
ｈ）に示すように、
密着層１上にＣｕ−Ｎｉ −Ａｕの多層構造を有する接
続バッド２を形成してなる配線基板において、
前記Ｎｉ層３を無電解Ｎｉ−Ｂにて形成したことを特徴
とする配線基板を提供することにより達成される。
さらに、上記配線基板は、第１図にその工程を示すよう
に、
密着１１上にＣｕ−Ｎｉ−Ａｕの多層構造を有する接続
パッド２を形成する配線基板の製造方法において、
前記Ｃｕ層４を電解メッキにて形成した後、適宜の触媒
を該Ｃｕ ｔｉ ４の露出部に吸着させ、次いでＮｉ−
Ｂ、およびＡｕ層５を無電解メッキにて積層して製造さ
れる。According to the present invention, the above object is achieved as shown in FIG.
As shown in h), in the wiring board in which the connection pad 2 having a multilayer structure of Cu-Ni-Au is formed on the adhesive layer 1, the Ni layer 3 is formed of electroless Ni-B. This is achieved by providing a wiring board with these characteristics. Furthermore, the above-mentioned wiring board is manufactured using a method for manufacturing a wiring board in which a connection pad 2 having a multilayer structure of Cu-Ni-Au is formed on the adhesive 11, as shown in the process shown in FIG. After forming by electrolytic plating, a suitable catalyst is adsorbed on the exposed part of the Cu Ti 4, and then Ni-
It is manufactured by laminating B and Au layer 5 by electroless plating.
上記構成に基づき、本発明におけるニッケル層３は、無
電解メッキにより形成される。
電解ニッケルメンキにおいては、メッキ厚のばらつきが
太き（，２ミクロンの膜厚を目標にメッキすると、略４
０パーセントの領域のメッキ厚は、１ミクロン程度とな
ることが知られており、この程度の膜厚においては、容
易に半田溶食が生じることとなる。これに対し、無電解
メッキの膜厚のばらつきは、電解メッキのそれに比較し
て３分の１あるいは４分の１程度と小さ（、半田拡散防
止層としてａ能するメッキ層が薄いために生じる半田溶
食は確実に防止される。
さらに、無電解メッキにより、銅層４の端面に対しても
容易にメッキ層が形成され、端面からの半田溶食が防止
される。
（実施例］
以下、本発明の望ましい実施例を添付図面に基づいて詳
細に説明する。
第１図は本発明の実施例を示すもので、先ずセラミック
基板等の配線基板の基材６上には、ポリイミドがスピン
コードされ、このポリイミド絶縁層７上にＣｒ、あるい
はＴｉがスパッタリングされて密着層１が形成される（
第１図（ａ）参照）。
次いで、第１図（ｂ）に示すように、密着層１上にレジ
スト８を塗布した後、第１図（Ｃ）に示すように、銅を
電気メッキし、さらにレジスト８を剥離してＣｕ層４が
密着層Ｉ上に積層される（第１図（ｄ）参照）。
この後、Ｃｕ層層上上は、レジスト８が塗布され、パネ
ルエンチングにより不要部分の密着層１を除去した後、
レジスト８を剥離し、導体パターンが形成される（第１
図（ｅ）ないしくｇ）参照）本発明は、銅による導体パ
ターンの端面が外部に露出し、半田溶食を受けないよう
に、上記導体パターンの表面部に加え、端面にもニッケ
ル層３を形成するもので、端面を含めてＣｕ層４をＮｉ
層３で覆うために、先ず配線基板を塩化パラジウム水溶
液中に浸漬して、Ｃｕ層４０表面部、および端面にパラ
ジウム触媒を吸着させた後、無電解ニッケルメッキが施
される。この場合、半田濡れ性の信頼性を向上させるた
め、ジメチルアミンボランを還元側としたＮｉ−Ｂのニ
ッケルメッキ液を使用するのが望ましく、かかるＮｉ−
８層３上に金層５が無電解メッキにより形成され、接続
バッド２が形成される。Based on the above configuration, the nickel layer 3 in the present invention is formed by electroless plating. With electrolytic nickel coating, there is a large variation in plating thickness (if plating is aimed at a film thickness of 2 microns, it will be approximately 4.5 microns thick).
It is known that the plating thickness in the 0% region is about 1 micron, and at this film thickness, solder corrosion easily occurs. On the other hand, the variation in film thickness for electroless plating is about one-third or one-fourth smaller than that for electrolytic plating (this occurs because the plating layer that functions as a solder diffusion prevention layer is thin). Solder corrosion is reliably prevented.Furthermore, by electroless plating, a plating layer is easily formed on the end face of the copper layer 4, and solder corrosion from the end face is prevented.(Example) Below , a preferred embodiment of the present invention will be described in detail based on the accompanying drawings. Fig. 1 shows an embodiment of the present invention, in which polyimide is first spun on a base material 6 of a wiring board such as a ceramic substrate. The adhesive layer 1 is formed by sputtering Cr or Ti on the polyimide insulating layer 7 (
(See Figure 1(a)). Next, as shown in FIG. 1(b), after applying a resist 8 on the adhesive layer 1, as shown in FIG. 1(C), copper is electroplated, and the resist 8 is peeled off to form a Cu Layer 4 is laminated on adhesive layer I (see FIG. 1(d)). After that, a resist 8 is applied on the Cu layer, and after removing unnecessary parts of the adhesive layer 1 by panel etching,
The resist 8 is peeled off and a conductor pattern is formed (first
(See Figures (e) to g)) In order to prevent the end faces of the copper conductor pattern from being exposed to the outside and being subject to solder corrosion, the present invention provides a nickel layer on the end face in addition to the surface of the conductor pattern. The Cu layer 4 including the end faces is covered with Ni.
To cover with the layer 3, the wiring board is first immersed in a palladium chloride aqueous solution to adsorb a palladium catalyst on the surface and end surfaces of the Cu layer 40, and then electroless nickel plating is applied. In this case, in order to improve the reliability of solder wettability, it is desirable to use a Ni-B nickel plating solution with dimethylamine borane on the reducing side;
A gold layer 5 is formed on the 8 layer 3 by electroless plating, and a connection pad 2 is formed.
以上の説明から明らかなように、本発明による配！９！
基板によれば、半田溶食に対する拡散防止層となるＮｉ
−Ｂ層の膜厚のばらつきを抑えることができ、さらにＣ
ｕ層の端面をも該Ｎｉ−Ｂ層で覆うことができるので、
半田溶食を完全に防止することができる。As is clear from the above description, the arrangement according to the present invention! 9!
According to the substrate, Ni acts as a diffusion prevention layer against solder corrosion.
- It is possible to suppress variations in the film thickness of the B layer, and also
Since the end face of the u layer can also be covered with the Ni-B layer,
Solder corrosion can be completely prevented.
第１図は本発明の実施例を示す図、 第２図は従来例を示す図である。 図において、 ｌ・・・密着層、 ２・・・接続パッド、 ３・・・Ｎｉ−Ｂ層、 ４・・・Ｃｕ層、 ５・・・Ａｕ層、 FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a conventional example. In the figure, l...Adhesion layer, 2... Connection pad, 3...Ni-B layer, 4...Cu layer, 5...Au layer,
Claims (1)
を有する接続パッド（２）を形成してなる配線基板にお
いて、 前記Ｎｉ層（３）を無電解Ｎｉ−Ｂにて形成したことを
特徴とする配線基板。 〔２〕 密着層（１）上にＣｕ−Ｎｉ−Ａｕの多層構造
を有する接続パッド（２）を形成する配線基板の製造方
法において、 前記Ｃｕ層（４）を電解メッキにて形成した後、適宜の
触媒を該Ｃｕ層（４）の露出部に吸着させ、次いでＮｉ
−Ｂ、およびＡｕ層（５）を無電解メッキにて積層して
なる配線基板の製造方法。[Scope of Claims] [1] In a wiring board in which a connection pad (2) having a multilayer structure of Cu-Ni-Au is formed on an adhesive layer (1), the Ni layer (3) is made of electroless Ni. - A wiring board characterized in that it is formed of B. [2] In a method for manufacturing a wiring board in which a connection pad (2) having a multilayer structure of Cu-Ni-Au is formed on an adhesive layer (1), after forming the Cu layer (4) by electrolytic plating, A suitable catalyst is adsorbed onto the exposed portion of the Cu layer (4), and then Ni
-B and an Au layer (5) are laminated by electroless plating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26648890A JP2886317B2 (en) | 1990-10-05 | 1990-10-05 | Wiring board and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26648890A JP2886317B2 (en) | 1990-10-05 | 1990-10-05 | Wiring board and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04144190A true JPH04144190A (en) | 1992-05-18 |
| JP2886317B2 JP2886317B2 (en) | 1999-04-26 |
Family
ID=17431630
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26648890A Expired - Fee Related JP2886317B2 (en) | 1990-10-05 | 1990-10-05 | Wiring board and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2886317B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09191164A (en) * | 1996-01-10 | 1997-07-22 | Asahi Chem Ind Co Ltd | Fine thick film connection substrate and its manufacturing method |
| WO2004059305A2 (en) * | 2002-12-23 | 2004-07-15 | Friz Biochem Gesellschaft Für Bioanalytik Mbh | Printed board for the electrochemical detection of biomolecules |
| KR100516171B1 (en) * | 1997-12-30 | 2005-11-28 | 삼성전자주식회사 | Video output selection device and method of optical disc player |
| KR100756261B1 (en) * | 2005-12-14 | 2007-09-07 | 후지쯔 가부시끼가이샤 | Wiring board manufacturing method |
| CN102190277A (en) * | 2010-03-15 | 2011-09-21 | 欧姆龙株式会社 | Electrode structure and microdevice package provided therewith |
| JP2013038407A (en) * | 2011-08-05 | 2013-02-21 | Samsung Electro-Mechanics Co Ltd | Thin film electrode ceramic substrate and method for producing the same |
| WO2020004271A1 (en) * | 2018-06-26 | 2020-01-02 | 京セラ株式会社 | Wiring board |
-
1990
- 1990-10-05 JP JP26648890A patent/JP2886317B2/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09191164A (en) * | 1996-01-10 | 1997-07-22 | Asahi Chem Ind Co Ltd | Fine thick film connection substrate and its manufacturing method |
| KR100516171B1 (en) * | 1997-12-30 | 2005-11-28 | 삼성전자주식회사 | Video output selection device and method of optical disc player |
| WO2004059305A2 (en) * | 2002-12-23 | 2004-07-15 | Friz Biochem Gesellschaft Für Bioanalytik Mbh | Printed board for the electrochemical detection of biomolecules |
| WO2004059305A3 (en) * | 2002-12-23 | 2004-10-14 | Friz Biochem Gmbh | Printed board for the electrochemical detection of biomolecules |
| KR100756261B1 (en) * | 2005-12-14 | 2007-09-07 | 후지쯔 가부시끼가이샤 | Wiring board manufacturing method |
| CN102190277A (en) * | 2010-03-15 | 2011-09-21 | 欧姆龙株式会社 | Electrode structure and microdevice package provided therewith |
| JP2011192847A (en) * | 2010-03-15 | 2011-09-29 | Omron Corp | Electrode structure and package for microdevice having electrode structure |
| JP2013038407A (en) * | 2011-08-05 | 2013-02-21 | Samsung Electro-Mechanics Co Ltd | Thin film electrode ceramic substrate and method for producing the same |
| WO2020004271A1 (en) * | 2018-06-26 | 2020-01-02 | 京セラ株式会社 | Wiring board |
| JPWO2020004271A1 (en) * | 2018-06-26 | 2021-06-24 | 京セラ株式会社 | Wiring board |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2886317B2 (en) | 1999-04-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |