JPH05211192A - 半導体装置のワイヤボンディング方法 - Google Patents

半導体装置のワイヤボンディング方法

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Publication number
JPH05211192A
JPH05211192A JP3161696A JP16169691A JPH05211192A JP H05211192 A JPH05211192 A JP H05211192A JP 3161696 A JP3161696 A JP 3161696A JP 16169691 A JP16169691 A JP 16169691A JP H05211192 A JPH05211192 A JP H05211192A
Authority
JP
Japan
Prior art keywords
wire
pad
gold
semiconductor device
wire bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3161696A
Other languages
English (en)
Inventor
Akihisa Iguchi
明久 井口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
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Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP3161696A priority Critical patent/JPH05211192A/ja
Publication of JPH05211192A publication Critical patent/JPH05211192A/ja
Withdrawn legal-status Critical Current

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    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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Abstract

(57)【要約】 【目的】 半導体装置のワイヤボンディング方法におい
て、パッド間隔の縮小化を図り、しかもワイヤループの
垂みや、カールの発生を防止する。 【構成】 半導体装置のワイヤボンディングにあたり、
予め半導体素子１２のパッド１２ａ上に金球１４ａを形
成し、リードフレームの外部端子１３に金線１４を接合
し、その金線１４を張り、半導体素子１２のパッド１２
ａ上の金球１４ａにウェッジボンドするようにしたもの
である。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は、半導体集積回路におけ
る内部配線であるワイヤボンディング方法に関するもの
である。
【０００２】
【従来の技術】従来、このような分野の技術としては、
例えば、以下に示すようなものがあった。図３はかかる
従来の半導体装置のワイヤボンディング工程図である。
まず、図３（ａ）に示すように、ダイパッド１上の半導
体素子２をパッケージの外部端子３に接続する場合、金
属細線４の先端を熱で溶解し、球状５としたものを、半
導体素子２上のパッドに接続した後、その金属細線４を
パッケージの外部端子３側へ導いて接合する。
【０００３】次に、図３（ｂ）に示すように、外部端子
３上の金属細線４を切断する。最後に、図３（ｃ）に示
すように、金属細線４の先端を球状５となし、次の箇所
のワイヤボンドに備える。なお、６はキャピラリ、７は
クランパである。
【０００４】
【発明が解決しようとする課題】しかしながら、従来の
ワイヤボンディング方法では、半導体素子のパッド側の
金属細線４が１５０μｍから４００μｍ程度立ち上がっ
ているために、半導体素子２上のパッド配列間隔を狭め
るためには、キャピラリ６の先端が隣の既に存在する金
属細線に干渉しないように細くするか、もしくは干渉し
ない程度のパッド配列間隔にとめる等の対策を必要とし
ていた。しかし、キャピラリ６の先端を細くする方法に
も限界があり、おのずとパッド配列間隔は制約されてし
まうという問題点があった。
【０００５】本発明は、上記問題点を除去し、パッド間
隔の縮小化が可能で、しかもワイヤループの垂みや、カ
ールが発生することがない半導体装置のワイヤボンディ
ング方法を提供することを目的とする。
【０００６】
【課題を解決するための手段】本発明は、上記目的を達
成するために、半導体装置のワイヤボンディング方法に
おいて、予め半導体素子のパッド上に金属球を形成し、
リードフレームの外部端子に金属細線を接合し、該金属
細線を張り、前記半導体素子のパッド上の金属球にウェ
ッジボンドするようにしたものである。
【０００７】また、前記半導体素子のパッド上にはバン
プが形成されたものを用いることもできる。
【０００８】
【作用】本発明によれば、ワイヤボンディング方法にお
いて、予め、半導体素子のパッド上に金球を接合し、金
球のみを残して金線を一旦カットし、金球の生成を行な
う。次に、２つ目に形成した金球をリードフレームの外
部端子に接合し、そこから導いた金線を先程パッド上に
接合した金球へ接合することにより、電気的導通を得
る。
【０００９】従って、パッド間隔の縮小化が可能であ
り、しかも、ワイヤループの垂みや、カールが発生する
ことがない。
【００１０】
【実施例】以下、本発明の実施例について図面を参照し
ながら詳細に説明する。図１は本発明の実施例を示す前
半の半導体装置のワイヤボンディング工程断面図であ
り、図２は本発明の実施例を示す後半の半導体装置のワ
イヤボンディング工程断面図である。
【００１１】まず、図１（ａ）に示すように、キャピラ
リ１６の下方の金線１４の先端に形成された金球１４ａ
を、ダイパッド１１上に搭載された半導体素子１２のパ
ッド１２ａ上に位置合わせする。次に、図１（ｂ）に示
すように、金線１４の先端に形成された金球１４ａをキ
ャピラリ１６により半導体素子１２のパッド１２ａ上に
押し付け接合する。
【００１２】次いで、図１（ｃ）に示すように、金球形
成に必要な金球長さｌをキャピラリ１６から繰り出した
ところで、クランパ１７を閉じる。次に、図１（ｄ）に
示すように、キャピラリ１６を上昇させて、金球１４ａ
から金線１４を切断する。次に、図１（ｅ）に示すよう
に、トーチ１８により、金球１４ｂを形成する。
【００１３】次いで、図２（ｆ）に示すように、リード
フレームの外部端子１３にその金球１４ｂを位置合わせ
する。次いで、図２（ｇ）に示すように、リードフレー
ムの外部端子１３にその金球１４ｂを接合する。次に、
図２（ｈ）に示すように、既存の方式により、ワイヤル
ープを形成しながら、金線１４を導いていく。
【００１４】次に、図２（ｉ）に示すように、金線１４
を半導体素子１２のパッド１２ａ上に既に形成された金
球１４ａ上にウェッジボンドする。次に、図２（ｊ）に
示すように、ワイヤボンドに必要な金球形成のためテー
ル１４ｔを繰り出す。次に、図２（ｋ）に示すように、
金球１４ｃをトーチ１８により作る。
【００１５】このように、上記のサイクルを続けること
で、ワイヤボンドを行なうことができる。なお、上記実
施例においては、図１（ｄ）に示すように、半導体素子
１２のパッド１２ａ上にキャピラリ１６により金球１４
ａを形成するようにしているが、これに代えて、図４に
示すように、ダイパッド２１上に予めバンプ２３が形成
された半導体素子２２を搭載し、そのバンプ２３上に、
図２（ｉ）と同様に、金線２５をウェッジボンドするよ
うにしてもよい。２４は外部端子である。
【００１６】上記したように、予め、金球を形成する方
式は、金球形成の位置精度が要求され、次のワイヤボン
ド時に、もう一度金球位置を画像認識補正を個々の金球
について行なうことが必要とされる時に有利である。ま
た、バンプ付き半導体素子を用いる場合は、金球形成
に要するワイヤボンドの時間を短縮することができる。
パッドがダメージを受け易い構造の場合に、全くダメ
ージを与えずに形成できるバンプをつけて、ワイヤボン
ドの衝撃を和らげることができる。
【００１７】なお、本発明は上記実施例に限定されるも
のではなく、本発明の趣旨に基づいて種々の変形が可能
であり、これらを本発明の範囲から排除するものではな
い。
【００１８】
【発明の効果】以上、詳細に説明したように、本発明に
よれば、半導体素子のパッド間隔の縮小化を図ることが
できる。例えば、従来１８０μｍピッチであったパッド
間隔を１００μｍ以下とすることができる。その場合、
現在のワイヤボンド装置を流用して、簡単に実施するこ
とができる。
【００１９】更に、以下に述べる効果を奏することがで
きる。 （１）キャピラリ先端の形状は現状のままで良い。 （２）リードフレームの外部端子のボンディング強度が
リード形状に影響されることがない。 （３）リードフレームの外部端子のボンディング時に、
従来発生していたワイヤループの垂みや、カールが発生
することがない。
【図面の簡単な説明】
【図１】本発明の実施例を示す前半の半導体装置のワイ
ヤボンディング工程断面図（その１）である。
【図２】本発明の実施例を示す後半の半導体装置のワイ
ヤボンディング工程断面図（その２）である。
【図３】従来の半導体装置のワイヤボンディング工程図
である。
【図４】本発明の他の実施例を示す半導体装置のワイヤ
ボンディング状態を示す断面図である。
【符号の説明】
１１，２１ ダイパッド １２，２２ 半導体素子 １２ａ パッド １３，２４ 外部端子 １４，２４ 金線 １４ａ，１４ｂ，１４ｃ 金球 １４ｔ テール １６ キャピラリ １７ クランパ １８ トーチ ２３ バンプ

Claims (2)

    【特許請求の範囲】
  1. 【請求項１】（ａ）予め半導体素子のパッド上に金属球
    を形成し、 （ｂ）次に、リードフレームの外部端子に金属細線を接
    合し、 （ｃ）該金属細線を張り、前記半導体素子のパッド上の
    金属球にウェッジボンドすることを特徴とする半導体装
    置のワイヤボンディング方法。
  2. 【請求項２】 前記パッド上にはバンプが形成された半
    導体素子を用いることを特徴とする請求項１記載の半導
    体装置のワイヤボンディング方法。
JP3161696A 1991-07-02 1991-07-02 半導体装置のワイヤボンディング方法 Withdrawn JPH05211192A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3161696A JPH05211192A (ja) 1991-07-02 1991-07-02 半導体装置のワイヤボンディング方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3161696A JPH05211192A (ja) 1991-07-02 1991-07-02 半導体装置のワイヤボンディング方法

Publications (1)

Publication Number Publication Date
JPH05211192A true JPH05211192A (ja) 1993-08-20

Family

ID=15740127

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JPH05211192A (ja)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0753891A2 (en) * 1995-06-28 1997-01-15 Texas Instruments Incorporated Low loop wire bonding
US6079610A (en) * 1996-10-07 2000-06-27 Denso Corporation Wire bonding method
JP2002237499A (ja) * 2001-02-09 2002-08-23 Mitsubishi Electric Corp 半導体装置の製造方法、半導体装置の製造装置
WO2002082527A1 (en) * 2001-04-05 2002-10-17 Stmicroelectronics Pte Ltd Method of forming electrical connections
US6601752B2 (en) 2000-03-13 2003-08-05 Denso Corporation Electronic part mounting method
EP1374298A1 (en) * 2001-03-23 2004-01-02 Koninklijke Philips Electronics N.V. Chip module with bond-wire connections with small loop height
KR100734269B1 (ko) * 2005-07-29 2007-07-02 삼성전자주식회사 와이어 본딩 장치

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0753891A2 (en) * 1995-06-28 1997-01-15 Texas Instruments Incorporated Low loop wire bonding
EP0753891A3 (en) * 1995-06-28 1999-03-31 Texas Instruments Incorporated Low loop wire bonding
US6079610A (en) * 1996-10-07 2000-06-27 Denso Corporation Wire bonding method
US6601752B2 (en) 2000-03-13 2003-08-05 Denso Corporation Electronic part mounting method
JP2002237499A (ja) * 2001-02-09 2002-08-23 Mitsubishi Electric Corp 半導体装置の製造方法、半導体装置の製造装置
EP1374298A1 (en) * 2001-03-23 2004-01-02 Koninklijke Philips Electronics N.V. Chip module with bond-wire connections with small loop height
WO2002082527A1 (en) * 2001-04-05 2002-10-17 Stmicroelectronics Pte Ltd Method of forming electrical connections
KR100734269B1 (ko) * 2005-07-29 2007-07-02 삼성전자주식회사 와이어 본딩 장치

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