JPH05129465A - Electrode section structure of electronic device and manufacture thereof - Google Patents
Electrode section structure of electronic device and manufacture thereofInfo
- Publication number
- JPH05129465A JPH05129465A JP3288119A JP28811991A JPH05129465A JP H05129465 A JPH05129465 A JP H05129465A JP 3288119 A JP3288119 A JP 3288119A JP 28811991 A JP28811991 A JP 28811991A JP H05129465 A JPH05129465 A JP H05129465A
- Authority
- JP
- Japan
- Prior art keywords
- film pattern
- thin film
- electrode
- electronic device
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電子デバイス全般の電
極部構造に関し、特に半導体製造及び、その製造方法を
利用して製造される電子デバイスのフォトリソグラフィ
−によるパタ−ン配線形成時に利用される。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode structure of an electronic device in general, and is particularly used for manufacturing a semiconductor and forming a pattern wiring by photolithography of an electronic device manufactured by the manufacturing method. It
【０００２】[0002]
【従来の技術】従来の電子デバイスの電極部は、図５
（ａ）のように電極配線基板（１）上に、単に下地膜パ
タ−ン（３）を設け、さらにその上に電極となる上層薄
膜パタ−ン（４）を形成していた。しかし、図５（ｂ）
のようにフォトリソグラフィ−技法によって、下地の膜
パタ−ン（３）の段差部分上に、新たに薄膜パタ−ン
（４）を形成しようとした場合、エッチャントの染み込
みにより、段差部分にそってくさび形状の断線が発生し
ていた。2. Description of the Related Art The electrode portion of a conventional electronic device is shown in FIG.
As in (a), the underlying film pattern (3) is simply provided on the electrode wiring substrate (1), and the upper layer thin film pattern (4) serving as an electrode is further formed thereon. However, FIG. 5 (b)
When a new thin film pattern (4) is to be formed on the step portion of the underlying film pattern (3) by the photolithography technique as described above, the step portion is formed along the step portion due to the soaking of the etchant. There was a wedge-shaped disconnection.
【０００３】この原因は、上層に成膜した膜の段差部分
のステップカバレッジが悪く、空孔部分（１５）がで
き、この部分にフォトレジスト（１４）が入り込まない
ためといわれており、これを解決するために、半導体プ
ロセスでは、下地膜パタ−ンとなるシリコン酸化物のエ
ッチング時にその段差部分が傾斜するようにエッチャン
トを含むプロセスを制御していた。It is said that this is because the step coverage of the step portion of the film formed on the upper layer is poor and the hole portion (15) is formed, and the photoresist (14) does not enter this portion. In order to solve the problem, in a semiconductor process, a process including an etchant is controlled so that a step portion of the silicon oxide, which is a pattern of a base film, is inclined when the silicon oxide is etched.
【０００４】[0004]
【発明が解決しようとする課題】従来の電子デバイスの
電極部においては、前述したように下地となるシリコン
酸化物のエッチング時に段差が傾斜するようにエッチャ
ントを制御しなければならず、このため下地機能膜を変
更するたびに、その膜の材料に合わせた段差部分の傾斜
を達成するエッチャント組成の開発が必要であり、安定
に傾斜を達成するためのエッチャントの開発が容易では
なく、さらに材料によっては、それが不可能となってい
た。In the electrode portion of the conventional electronic device, the etchant must be controlled so that the step is inclined during the etching of the underlying silicon oxide, as described above. Each time the functional film is changed, it is necessary to develop an etchant composition that achieves the slope of the step portion according to the material of the film, and it is not easy to develop an etchant that achieves a stable slope. Had made it impossible.
【０００５】本発明は、電子デバイスのフォトリソグラ
フィ−を利用した電極配線形成において、エッチング時
に電極断線を防止し、良好な接続を可能にすることを目
的としている。It is an object of the present invention to prevent electrode breakage during etching in electrode wiring formation utilizing photolithography of an electronic device and to enable good connection.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するため
に、本発明は図１，２のように、電極部の下地膜パタ−
ン（３）の側面部に、該電極部の上層薄膜パタ−ン
（４）にそって、前記上層薄膜パタ−ン（４）の幅より
も幅の狭い突起部（２）を形成している。In order to achieve the above object, the present invention provides a base film pattern of an electrode portion as shown in FIGS.
A protrusion (2) having a width narrower than that of the upper thin film pattern (4) is formed on a side surface of the electrode (3) along the upper thin film pattern (4) of the electrode portion. There is.
【０００７】そして、本発明の製造方法においては、フ
ォトリソグラフィ−によって、下地膜パタ−ン（３）を
形成する際に、この下地膜パタ−ン（３）と同時に、突
起部（２）を形成し、さらに該突起部（２）を含めた下
地薄膜パタ−ン（３）上に、前記上層薄膜パタ−ン
（４）を設けている。In the manufacturing method of the present invention, when the underlying film pattern (3) is formed by photolithography, the protrusions (2) are formed simultaneously with the underlying film pattern (3). The upper layer thin film pattern (4) is formed on the underlying thin film pattern (3) including the projections (2).
【０００８】これにより本発明は、フォトリソグラフィ
−によるパタ−ン配線形成時に生じる不具合を解消して
いる。As a result, the present invention solves the problem that occurs when pattern wiring is formed by photolithography.
【０００９】[0009]
【実施例】図１は本発明の電子デバイスの電極部の構成
図、図２は本発明の突起物を形成した下地膜パタ−ン
図、そして図３、４は、本発明の電極配線を用いたサ−
マルヘッドの実施例を示す図面である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of an electrode portion of an electronic device of the present invention, FIG. 2 is a pattern diagram of a base film on which a protrusion of the present invention is formed, and FIGS. The server used
It is drawing which shows the Example of a round head.
【００１０】図１、２に示されているように、本発明
は、基板（１）上に下地膜パタ−ン（３）を設け、その
上に更に上層薄膜パタ−ン（４）を形成しようとした場
合に、単に薄膜パタ−ンを重ね合わせるのではなくて、
上層薄膜パタ−ン（４）の形成される位置にそって、下
地膜パタ−ン（３）の側面部に前述した上層薄膜パタ−
ン（４）の幅よりも幅の狭い突起部（２）を同時に形成
し、この突起部（２）を含めた下地膜パタ−ン（３）上
に上層薄膜パタ−ン（４）を設けている。なお、突起部
（２）の幅Ｗ２は、上層薄膜パタ−ン（４）の幅Ｗ１よ
り狭ければよいが、マスク合わせ時のズレを考慮する
と、Ｗ２はＷ１の１／３程度が好ましい。As shown in FIGS. 1 and 2, according to the present invention, a base film pattern (3) is provided on a substrate (1), and an upper layer thin film pattern (4) is further formed thereon. If you try, instead of simply stacking thin film patterns,
The above-mentioned upper layer thin film pattern is formed on the side surface of the underlayer film pattern (3) along the position where the upper layer thin film pattern (4) is formed.
A projection (2) narrower than the width of the projection (4) is formed at the same time, and the upper layer thin film pattern (4) is provided on the underlying film pattern (3) including the projection (2). ing. The width W2 of the protrusion (2) may be smaller than the width W1 of the upper layer thin film pattern (4), but considering the misalignment during mask alignment, W2 is preferably about 1/3 of W1.
【００１１】その際、突起部（２）の長さｌは、下地膜
パタ−ン（３）の膜厚の１０倍以上が好ましく、本実施
例では、膜厚１μm に対して１０μm 程度としたが、ス
ペ−スの制限がなければ、さらに長くすることもでき
る。At this time, the length l of the protrusion (2) is preferably 10 times or more the film thickness of the underlying film pattern (3), and in this embodiment, it is about 10 μm with respect to the film thickness of 1 μm. However, it can be made longer if there is no space limitation.
【００１２】ここで、これらの膜パタ−ンは、フォトリ
ソグラフィ−により形成がなされ、具体的には、まず下
地となる膜の表面にフォトレジストを塗布し、そして突
起配線パタ−ン（２）の描かれたフォトマスクを、この
上に載せて紫外線を照射する。これによって、フォトレ
ジストが選択的に除去され、下地膜パタ−ン（３）の側
面部に突起物を設けたパタ−ンを残している。それから
エッチング液でエッチングすることによって、図２に示
すように、突起部を備えた下地膜パタ−ン（３）を形成
している。次にこの突起物を含めた下地膜パタ−ン
（３）上に、新たに薄膜を付着させ、薄膜の表面に再び
フォトレジストを塗布して、今度は上層薄膜パタ−ンの
描かれたフォトマスクを載せる。そして前述と同じ操作
を繰り返し、電子デバイスの電極部を形成している。Here, these film patterns are formed by photolithography. Specifically, first, a photoresist is applied to the surface of the film to be the base, and then the projection wiring pattern (2) is formed. Place the photomask on which the above is drawn and irradiate it with ultraviolet rays. As a result, the photoresist is selectively removed, leaving a pattern in which protrusions are provided on the side surface of the underlying film pattern (3). Then, by etching with an etching solution, as shown in FIG. 2, a base film pattern (3) having protrusions is formed. Next, a new thin film is deposited on the underlayer film pattern (3) including the protrusions, and a photoresist is applied again to the surface of the thin film, and this time, a photo with the upper layer thin film pattern is drawn. Place a mask. Then, the same operation as described above is repeated to form the electrode portion of the electronic device.
【００１３】次に図３、４は、この発明をサ−マルヘッ
ドの電極配線部に応用した実施例であるが、その図３に
おいては、サ−マルヘッドの概略図が示され、ヒ−トシ
ンク（５）上にアルミナ基板（６）とＰＣＢ基板（７）
を載せ、前者のアルミナ基板（６）上には、発熱抵抗体
（８）とリ−ド線（９）を設け、後者のＰＣＢ基板
（７）上には、駆動用ＩＣ（１０）が具備されている。
そしてこのリ−ド線（９）と駆動用ＩＣ（１０）、そし
て駆動用ＩＣ（１０）とＰＣＢ基板（７）の電気的接続
は、ワイヤボンディング（１１）によって接続され、保
護樹脂（１２）で覆われている。Next, FIGS. 3 and 4 show an embodiment in which the present invention is applied to an electrode wiring portion of a thermal head. In FIG. 3, a schematic diagram of the thermal head is shown and a heat sink ( 5) Alumina substrate (6) and PCB substrate (7) on top
The heating resistor (8) and the lead wire (9) are provided on the former alumina substrate (6), and the driving IC (10) is provided on the latter PCB substrate (7). Has been done.
The lead wire (9) and the driving IC (10), and the driving IC (10) and the PCB substrate (7) are electrically connected to each other by wire bonding (11) and a protective resin (12). Is covered with.
【００１４】ここで本発明の電極配線を用いた実施例と
して、このワイヤボンディング（１１）をリ−ド線
（９）に接続する際に必要なパッド部（１３）について
以下説明する。As an embodiment using the electrode wiring of the present invention, the pad portion (13) required for connecting the wire bonding (11) to the lead wire (9) will be described below.
【００１５】図４（ａ）、図４（ｂ）は、図３のパッド
部（１３）の拡大図であるが、パッド部（１３）の下地
膜パタ−ン（３）の側面部に、発熱抵抗体（８）につな
がるリ−ド線（９）の幅よりも幅の狭い突起部（２）を
下地膜パタ−ン（３）形成と同時に設け、その上に、そ
のリ−ド線（９）となる上層薄膜パタ−ンを形成してい
る。4 (a) and 4 (b) are enlarged views of the pad portion (13) of FIG. 3, in which the side surface portion of the base film pattern (3) of the pad portion (13) is A protrusion (2) having a width narrower than that of the lead wire (9) connected to the heating resistor (8) is provided at the same time as the formation of the underlying film pattern (3), and the lead wire is formed on the protrusion (2). The upper layer thin film pattern to be (9) is formed.
【００１６】この場合もそれぞれの膜パタ−ンは、フォ
トリソグラフィ−によって形成されるが、図４（ａ）は
下地膜パタ−ン（３）上に、上層薄膜パタ−ン（４）の
フォトマスクを合わせた状態を示し、図４（ｂ）はエッ
チングした後の状態を示しており、上層薄膜パタ−ン
（４）であるリ−ド線（９）と下地膜パタ−ン（３）と
が、同じアルミニウム等の金属からなっているため、エ
ッチングを行うと下地膜パターン（３）もリ−ド線
（９）のある部分以外は、除去されてしまっている。In this case as well, each film pattern is formed by photolithography. In FIG. 4 (a), the photo film of the upper layer thin film pattern (4) is formed on the base film pattern (3). FIG. 4 (b) shows a state after the mask is fitted, and shows the state after etching, that is, the lead wire (9) which is the upper layer thin film pattern (4) and the underlying film pattern (3). Since they are made of the same metal such as aluminum, the underlying film pattern (3) is also removed by etching except for the portion having the lead line (9).
【００１７】これにより、リ−ド部（９）よりも膜厚が
厚いパッド部が形成される。As a result, a pad portion having a film thickness larger than that of the lead portion (9) is formed.
【００１８】[0018]
【発明の効果】以上に述べた如く本発明によれば、下地
膜に上層薄膜パタ−ン（４）の幅よりも狭い幅の突起部
（２）を下地膜パタ−ン（３）形成と同時に設けている
ため、フォトリソグラフィ−によって電極配線を形成す
る際に生じていた、エッチング時の下地段差部分のエッ
チャント染み込みによる電極断線を防止することを可能
としている。As described above, according to the present invention, the base film pattern (3) is formed on the base film with the protrusions (2) having a width narrower than the width of the upper thin film pattern (4). Since they are provided at the same time, it is possible to prevent the electrode disconnection caused by the etchant soaking in the step portion of the underlying layer during etching, which occurs when the electrode wiring is formed by photolithography.
【００１９】また、各種下地材料の段差部分に傾斜を設
けるエッチング方法をとる必要がなく、しかも、下地材
料の変更に対して新たなプロセス開発をする手間がかか
らないので、従来までの電極断線を防止するのに考えら
れていた製造プロセスよりも簡略化でき、さらに電極断
線による不良品も削減できるので、歩留りの向上にもつ
ながる。Further, since it is not necessary to use an etching method for providing an inclination at the stepped portion of various base materials, and since it does not take time and effort to develop a new process for changing the base material, it is possible to prevent the electrode from being broken. The manufacturing process can be simplified compared to the conventional manufacturing process, and defective products due to electrode disconnection can be reduced, leading to improved yield.
【図１】本発明の電子デバイスの電極部の構成図であ
る。FIG. 1 is a configuration diagram of an electrode portion of an electronic device of the present invention.
【図２】本発明の突起部を形成した下地膜パタ−ン図で
ある。FIG. 2 is a pattern diagram of a base film on which a protrusion of the present invention is formed.
【図３】本発明の電極構造を用いたサ−マルヘッドの概
略図である。FIG. 3 is a schematic view of a thermal head using the electrode structure of the present invention.
【図４】本発明の電極構造を用いたサ−マルヘッドのパ
ッド部の拡大図である。 （ａ）フォトマスクを合わせた状態 （ｂ）エッチングした後の状態FIG. 4 is an enlarged view of a pad portion of a thermal head using the electrode structure of the present invention. (A) Photomask aligned state (b) State after etching
【図５】従来までの電子デバイスの電極部である。 （ａ）構成図 （ｂ）側面図FIG. 5 is an electrode part of a conventional electronic device. (A) Configuration diagram (b) Side view
１、基板 ２、下地膜パタ−ンの突起部 ３、下地膜パタ−ン ４、上層薄膜パタ−ン ５、ヒ−トシンク ６、アルミナ基板 ７、ＰＣＢ基板 ８、発熱抵抗体 ９、リ−ド線 １０、駆動用ＩＣ １１、ワイヤボンディング １２、保護樹脂 １３、パッド部 １４、フォトレジスト １５、フォトレジストの空孔部 1, substrate 2, base film pattern protrusion 3, base film pattern 4, upper layer thin film pattern 5, heat sink 6, alumina substrate 7, PCB substrate 8, heating resistor 9, lead Wire 10, drive IC 11, wire bonding 12, protective resin 13, pad portion 14, photoresist 15, hole portion of photoresist
Claims (2)
成した電子デバイスの電極部構造において、前記下地膜
パタ−ンの側面部に、該上層薄膜パタ−ンにそって、前
記上層薄膜パタ−ンの幅よりも幅の狭い突起部を形成し
たことを特徴とする電子デバイスの電極部構造。1. An electrode structure of an electronic device in which an upper layer thin film pattern is formed on an underlayer film pattern, the side surface portion of the underlayer film pattern being provided along the upper layer thin film pattern. An electrode structure of an electronic device, characterized in that a protrusion having a width narrower than that of the upper thin film pattern is formed.
タ−ンの側面部に、突起部を同時に形成し、次いで該突
起部を含めた下地膜パタ−ン上に、上層薄膜パタ−ンを
設けたことを特徴とする請求項１記載の電子デバイスの
電極部構造の製造方法。2. A projection is simultaneously formed on the side surface of the base film pattern by photolithography, and then an upper layer thin film pattern is provided on the base film pattern including the projection. The method for manufacturing an electrode part structure of an electronic device according to claim 1, wherein.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3288119A JPH05129465A (en) | 1991-11-01 | 1991-11-01 | Electrode section structure of electronic device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3288119A JPH05129465A (en) | 1991-11-01 | 1991-11-01 | Electrode section structure of electronic device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05129465A true JPH05129465A (en) | 1993-05-25 |
Family
ID=17726058
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3288119A Withdrawn JPH05129465A (en) | 1991-11-01 | 1991-11-01 | Electrode section structure of electronic device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05129465A (en) |
-
1991
- 1991-11-01 JP JP3288119A patent/JPH05129465A/en not_active Withdrawn
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| JPS58202555A (en) | Manufacture of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990204 |