JP2985426B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2985426B2 JP2985426B2 JP3261938A JP26193891A JP2985426B2 JP 2985426 B2 JP2985426 B2 JP 2985426B2 JP 3261938 A JP3261938 A JP 3261938A JP 26193891 A JP26193891 A JP 26193891A JP 2985426 B2 JP2985426 B2 JP 2985426B2
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- electrode
- base metal
- width
- resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
- H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
- H01L2224/11472—Profile of the lift-off mask
Landscapes
- Wire Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体装置のＴＡＢ
（Tape Automated Bonding）アセンブリ時にテープと接
合される半導体装置の突起電極（バンプ）部の構造、お
よびその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TAB for a semiconductor device.
(Tape Automated Bonding) The present invention relates to a structure of a protruding electrode (bump) portion of a semiconductor device to be bonded to a tape at the time of assembly and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】図８（Ａ）〜（Ｃ）は半導体装置のＴＡ
Ｂアセンブリプロセスを説明する図である。図８（Ａ）
のウエハ上のチップに図８（Ｂ）にて突起電極（バン
プ）を形成し、図８（Ｃ）に示すようにこの突起電極と
リードがボンディングされる。図７は図８（Ｂ）のバン
ブ部を拡大した従来例を示す断面図であり、例えばアル
ミ合金等からなる電極１上に突起電極６を形成してい
る。なお２は絶縁膜、３は下地金属層である。この種の
突起電極６の形成方法を図９によって説明する。2. Description of the Related Art FIGS. 8A to 8C show a TA of a semiconductor device.
It is a figure explaining a B assembly process. FIG. 8 (A)
8B, a protruding electrode (bump) is formed on the chip on the wafer, and the protruding electrode and the lead are bonded as shown in FIG. 8C. FIG. 7 is a sectional view showing a conventional example in which the bump portion of FIG. 8B is enlarged, in which a protruding electrode 6 is formed on an electrode 1 made of, for example, an aluminum alloy or the like. Reference numeral 2 denotes an insulating film, and reference numeral 3 denotes a base metal layer. A method for forming this type of bump electrode 6 will be described with reference to FIG.
【０００３】図９（Ａ）は電極１と図示しない半導体部
分を保護する絶縁膜２を示す。図９（Ｂ）において、上
記電極１と絶縁膜２の表面上に突起電極６と電極１との
機械的密着力および電気的な導電性を上げるために全面
に下地金属層３を例えばスパッタリングで形成する。こ
の下地金属層３は例えば銅，クロム，金等の多層金属膜
が用いられている。FIG. 9A shows an electrode 1 and an insulating film 2 for protecting a semiconductor portion (not shown). In FIG. 9B, a base metal layer 3 is formed on the entire surface of the electrode 1 and the insulating film 2 by, for example, sputtering on the entire surface in order to increase the mechanical adhesion between the protruding electrode 6 and the electrode 1 and the electrical conductivity. Form. As the base metal layer 3, a multilayer metal film of, for example, copper, chromium, gold or the like is used.
【０００４】次に図９（Ｃ）において突起電極を形成す
るためのマスクとしてネガレジスト４をパターン形成す
る。このマスク厚さは例えば３０μｍ程度あり、これは
突起電極６が後工程のＴＡＢ時にハンダ層の拡散防止や
機械的耐性を確保するため厚いものが要求されているか
らであり、マスク４の厚さは当然のことながら突起電極
６より厚い。Next, in FIG. 9C, a negative resist 4 is patterned as a mask for forming the protruding electrodes. The thickness of this mask is, for example, about 30 μm, because the projection electrode 6 is required to be thick in order to prevent the diffusion of the solder layer and secure the mechanical resistance during the subsequent process of TAB. Is naturally thicker than the protruding electrode 6.
【０００５】次に図９（Ｄ）において例えば金等をメッ
キすることにより突起電極６を形成する。Next, in FIG. 9D, a protruding electrode 6 is formed by plating gold, for example.
【０００６】次に図９（Ｅ）においてレジスト４を除去
後、図９（Ｂ）で全面スパッタリング形成した下地金属
層３を突起電極６をマスクとしてウエットエッチング除
去し、突起電極６形成の部分工程は完了する。[0009] Next, after removing the resist 4 in FIG. 9 (E), the underlying metal layer 3 entirely formed by sputtering in FIG. 9 (B) is wet-etched and removed using the bump electrodes 6 as a mask. Is completed.
【０００７】[0007]
【発明が解決しようとする課題】（１）従来の突起電極
６の形成方法では、厚膜レジスト４のパターンを形成し
たとき、現像時の残留液の影響によって形成されると考
えられる裾引きが生じ、その後工程におけるメッキ時に
裾引き個所にメッキ金属が充填されない。その形状を図
７の５に示す。このため下地金属層３と突起電極６との
接触面積が少なくなり機械的耐力が劣るとともに電気的
接触性能が低下するという問題があった。さらにまた、
半導体装置の微細化に伴って相隣り合う突起電極間ピッ
チが狭くなってきており、上記裾引きがあると微細化が
困難であるという問題点もあった。（２）さらにまた図
９（Ｅ）に示したように、下地金属層をウエットエッチ
ングしたとき、図７に示すように下地金属層３がサイド
エッチングされる。結局のところ所定より幅のせまい下
地金属層３Sとなり、このようなものでは突起電極６と
の接続の機械的、電気的性能が劣るものであるという問
題点もあった。(1) In the conventional method of forming the bump electrode 6, when the pattern of the thick-film resist 4 is formed, a footing which is considered to be formed by the influence of the residual liquid at the time of development is made. Then, the plating metal is not filled in the tailing portion at the time of plating in the subsequent process. The shape is shown in FIG. For this reason, there is a problem that the contact area between the base metal layer 3 and the protruding electrode 6 is reduced, mechanical strength is deteriorated, and electrical contact performance is reduced. Furthermore,
With the miniaturization of semiconductor devices, the pitch between adjacent protruding electrodes has become narrower, and there has been a problem that miniaturization is difficult if there is the footing. (2) As shown in FIG. 9E, when the base metal layer is wet-etched, the base metal layer 3 is side-etched as shown in FIG. Narrower than ultimately predetermined width underlying metal layer 3 S becomes, than such things mechanical connection between the bump electrodes 6, there is a problem that in which electrical performance is poor.
【０００８】この発明は上記の問題点を解決するために
なされたもので、 （１）裾引きを除去する製造方法。 （２）裾引きを発生させない装置構造であってかつ、下
地金属層のサイドエッチングを防止する構造の提供を目
的とする。The present invention has been made to solve the above-mentioned problems, and (1) a manufacturing method for removing tailing. (2) It is an object of the present invention to provide a device structure that does not cause footing and that prevents side etching of a base metal layer.
【０００９】[0009]
【課題を解決するための手段】第１の発明に係る半導体
装置の製造方法では、電極上の保護膜表面に下地金属層
を形成する工程と、この下地金属層上にフォトレジスト
を設けパターン形成する工程と、このパターン形成され
た上記レジストをプラズマアッシングする工程と、上記
パターンに突起電極を形成する工程と、この突起電極を
マスクとして上記下地金属層をエッチングする工程とを
備えたものである。According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a base metal layer on a surface of a protective film on an electrode; forming a photoresist on the base metal layer to form a pattern; Performing a plasma ashing process on the patterned resist; forming a protruding electrode on the pattern; and etching the base metal layer using the protruding electrode as a mask. .
【００１０】第２の発明に係る半導体装置は、チップ上
に設けられた電極と、この電極上に選択的に形成された
絶縁膜と、この絶縁膜上に設けられ上記電極と接続され
た下地金属層と、この下地金属層上に形成される突起電
極とを備えた半導体装置であって、上記下地金属層には
上記突起電極の幅部分に相対して段差が設けられ、この
段差間の幅が上記突起電極の幅より小さいものである。A semiconductor device according to a second aspect of the present invention is an electrode provided on a chip, an insulating film selectively formed on the electrode, and a base provided on the insulating film and connected to the electrode. A semiconductor device comprising a metal layer and a protruding electrode formed on the underlying metal layer, wherein the underlying metal layer is provided with a step relative to a width portion of the protruding electrode. The width is smaller than the width of the protruding electrode.
【００１１】[0011]
【実施例】実施例１．以下この発明の一実施例を図につ
いて説明する。図１は第１の発明に係る突起電極の製造
方法を示すもので、プロセス途中の断面図である。詳し
くは従来例で説明した図９（Ｃ）の後に来るものであ
り、この本発明の図１の後に図９（Ｄ）の工程が来る。
つまり図１におけるネガレジストの厚膜レジスト４aを
パターン形成するまでは従来例と同じ製造方法であり、
この第１の発明ではレジスト４aをパターニング後、図
示しない半導体基板（図８のＡに相当する）の裏面から
約１００℃程度加熱し、表面を酸素プラズマによるアッ
シング（灰化）によりレジスト４aの表面層４bのみを除
去する。このようにして表面層４bのみが除去されたレ
ジスト４aは裾引き５aが小さなものとなり、その後の工
程でメッキされる突起電極６と下地金属層３との接触面
積は小さくならない。[Embodiment 1] An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view showing a method of manufacturing a bump electrode according to the first invention, which is in the middle of a process. The details come after FIG. 9C described in the conventional example, and the step of FIG. 9D comes after FIG. 1 of the present invention.
That is, the thick resist 4 a of the negative resist in Figure 1 until the patterning is the same manufacturing method as the conventional example,
After patterning the resist 4 a in the first invention, by heating the back surface from about 100 ° C. of the semiconductor substrate (not shown) (corresponding to A in FIG. 8), the resist 4 a by ashing the surface by oxygen plasma Only the surface layer 4b is removed. Thus the resist 4 only the surface layer 4 b is removed by a becomes footing 5 a is small, the contact area between the protrusion electrodes 6 and the underlying metal layer 3 to be plated in a subsequent step is not reduced.
【００１２】なお、この酸素プラズマによるアッシング
条件を図２に示す。この一実施例による条件では基板の
裏面から加熱されているのでレジスト４aの底部ほどア
ッシングされやすい。このようにアッシング処理時の基
板温度、処理時間等を制御することにより、レジスト４
aのパターン形状補正が可能となり、より垂直性のある
パターンが得られる。その実験の一例を図３、図４に示
す。なお、図３に示したポジ型レジストはレジスト４の
側壁傾きは小さいが後工程のメッキ性が悪いため採用さ
れ難い。FIG. 2 shows the ashing condition by the oxygen plasma. Likely to be ashed as the bottom of the resist 4 a because it is heated from the back surface of the substrate under the conditions according to this embodiment. By controlling the substrate temperature and the processing time during the ashing process in this manner, the resist 4
It enables a pattern shape correction, pattern is obtained more verticality of some. An example of the experiment is shown in FIGS. Although the positive type resist shown in FIG. 3 has a small inclination of the side wall of the resist 4, it is difficult to adopt the positive type resist because of poor plating property in a later step.
【００１３】実施例２．次に図５（Ａ）に第２の発明に
係るレジストパターンの構造を示す。図５（Ｂ）は図５
（Ａ）の裾引き部５c部分の拡大図を示す。図５（Ａ）
において、絶縁膜２に段差２cを設けている。この絶縁
膜２の上に従来技術と同様にして下地金属層３を全面に
スパッタリング形成する。この下地金属層３には絶縁膜
の段差２cに倣い、段差３b、３bが形成される。この段
差３b、３b間の距離つまり幅Ｗ2は、レジスト４のパタ
ーニング幅Ｗ1より小さい。つまり段差３b間の幅Ｗ2を
レジストパターニング幅Ｗ1より小さくするには、予め
絶縁膜２の段差２cの幅Ｗ3を下地金属層３の厚さ等を考
慮してエッチング形成する。図５（Ｂ）にはレジストパ
ターニング幅Ｗ1と下地金属層３の段差幅Ｗ2の差の1/2
であるΔＷを拡大化して示している。この隙間ΔＷはレ
ジスト４のエッチング液特性との関係から0.1〜0.5μｍ
程度が望しい。レジスト４のエッチングはパターン幅Ｗ
1でレジストを除去しつつ進行し、下地金属層３の上面
に達するが、上記隙間ΔＷが設けられているためエッチ
ング液の表面張力作用によって、裾引き５cは極めて小
さなものとなる。なお、下地金属層３の段差３bは、絶
縁膜の段差２cに下地金属層３のスパッタリングで倣う
ようにしているが、必要とあればスパッタリング後にエ
ッチングによって幅Ｗ2を精度よく形成してもよい。以
上のようにレジスト４のパターニングがなされるとエッ
チング液の表面張力と隙間ΔＷとの相関からレジスト４
の裾引き５cが小さくなり、この後工程で形成される突
起電極６の下地金属層３との接触長は少なくともＷ2と
なり、従来例の図７に示した如く接触面積の少ないもの
よりは格別の性能向上がはかれる。Embodiment 2 FIG. Next, FIG. 5A shows a structure of a resist pattern according to the second invention. FIG. 5 (B) is FIG.
Shows an enlarged view of the skirt portion 5 c portion of (A). FIG. 5 (A)
, A step 2 c is provided in the insulating film 2. An underlying metal layer 3 is formed on the entire surface of the insulating film 2 by sputtering in the same manner as in the prior art. Steps 3 b and 3 b are formed in the base metal layer 3 following the step 2 c of the insulating film. The step 3 b, 3 b distance clogging width W 2 of the smaller patterning width W 1 of the resist 4. That is, in order to make the width W 2 between the steps 3 b smaller than the resist patterning width W 1 , the width W 3 of the steps 2 c of the insulating film 2 is etched in advance in consideration of the thickness of the base metal layer 3 and the like. FIG. 5B shows a half of the difference between the resist patterning width W 1 and the step width W 2 of the underlying metal layer 3.
Is enlarged and shown. This gap ΔW is 0.1 to 0.5 μm from the relationship with the etching solution characteristics of the resist 4.
Desirable degree. The resist 4 is etched with a pattern width W
While proceeding while removing the resist at 1 , it reaches the upper surface of the underlying metal layer 3, but since the gap ΔW is provided, the footing 5 c becomes extremely small due to the surface tension effect of the etching solution. Incidentally, the step 3 b of the underlying metal layer 3 is so that follow in sputtering of the underlying metal layer 3 in the step 2 c of the insulating film, the width W 2 after sputtering by etching if necessary to precisely formed Is also good. When the resist 4 is patterned as described above, the pattern of the resist 4 is determined from the correlation between the surface tension of the etching solution and the gap ΔW.
The footing 5 c is reduced, the contact length between the underlying metal layer 3 projecting electrodes 6 formed in the following step for at least W 2 becomes, than with less as a contact area shown in FIG. 7 of the prior art Extraordinary performance improvement is achieved.
【００１４】次に図６で第２の発明により得られる他の
効果について説明する。図５（Ａ）でレジスト４をパタ
ーニング後従来例で説明した図９の（Ｄ）のメッキによ
り突起電極６が形成され、その後図９の（Ｅ）の如く下
地金属層３がエッチングされる。通常下地金属層３の厚
さは１μｍ程度であるので図６に示す第２の発明の構造
では、絶縁膜２の段差間２cの幅Ｗ3は、レジストパター
ン幅Ｗ1より２μｍ程度狭くなる。そして上記下地金属
層３のウエットエッチング時にこの絶縁膜の段差２Cが
エッチングストッパとして作用することにより、従来例
の第７図で示したような幅のせまい下地金属層３Sとな
らず、ほぼ絶縁膜の段差Ｗ3とならず、ほぼ絶縁膜の段
差幅Ｗ3に等しい幅ＷLの下地金属層３Lを得ることがで
きる。Next, another effect obtained by the second invention will be described with reference to FIG. After patterning the resist 4 in FIG. 5A, the protruding electrode 6 is formed by plating shown in FIG. 9D described in the conventional example, and then the underlying metal layer 3 is etched as shown in FIG. Normally, the thickness of the underlying metal layer 3 is about 1 μm, so in the structure of the second invention shown in FIG. 6, the width W 3 between the steps 2 c of the insulating film 2 is smaller than the resist pattern width W 1 by about 2 μm. . And it said underlying metal layer 3 at the time of wet etching by step 2 C of the insulating film acts as an etching stopper, narrow not the underlying metal layer 3 S width as shown in FIG. 7 of the prior art, approximately not the step W 3 of the insulating film, it is possible to obtain the underlying metal layer 3 L of equal width W L in step width W 3 of the substantially insulating film.
【００１５】[0015]
【発明の効果】以上のように第１の発明によれば、電極
上の保護膜表面に下地金属層を形成する工程と、この下
地金属層上にフォトレジストを設けパターン形成する工
程と、このパターン形成された上記レジストをプラズマ
アッシングする工程と、上記パターンに突起電極を形成
する工程と、この突起電極をマスクとして上記下地金属
層をエッチングする工程とによって半導体装置を製造し
ているので （１）突起電極と下地金属層との接触面積が従来のもの
に比べ増加し （２）その結果、下地金属層と突起電極との機械的、電
気的性能が向上する。 （３）また突起電極と下地金属層との接触が所望通りと
なるので狭ピッチの突起電極が得られることになり （４）半導体デバイスの微細化が可能となる。 次に第２の発明によれば、チップ上に設けられた電極
と、この電極上に選択的に形成された絶縁膜と、この絶
縁膜上に設けられ上記電極と接続された下地金属層と、
この下地金属上に形成される突起電極とを備えた半導体
装置であって、上記下地金属層には上記突起電極の幅部
分に相対して段差が設けられ、この段差間の幅が上記突
起電極の幅より小さくした構成であるので、上記した第
１の発明の（１）〜（４）に加え、 （５）下地金属層の幅を形成する為の絶縁膜の段差がエ
ッチングストッパとして作用して幅広の下地金属層が得
られ、これもまた突起電極と下地金属層と機械的、電気
的性能を高める。という効果が得られる。As described above, according to the first aspect, a step of forming a base metal layer on the surface of the protective film on the electrode, a step of forming a pattern by providing a photoresist on the base metal layer, Since a semiconductor device is manufactured by a step of plasma-ashing the patterned resist, a step of forming a projecting electrode in the pattern, and a step of etching the base metal layer using the projecting electrode as a mask, (1) ) The contact area between the bump electrode and the underlying metal layer is increased as compared with the conventional one. (2) As a result, the mechanical and electrical performance of the underlying metal layer and the bump electrode is improved. (3) Also, since the contact between the projecting electrode and the underlying metal layer is as desired, a projecting electrode having a narrow pitch can be obtained, and (4) miniaturization of a semiconductor device becomes possible. Next, according to the second invention, an electrode provided on the chip, an insulating film selectively formed on the electrode, and a base metal layer provided on the insulating film and connected to the electrode are provided. ,
A semiconductor device provided with a protruding electrode formed on the underlying metal, wherein the underlying metal layer is provided with a step relative to a width portion of the protruding electrode, and the width between the steps is equal to the width of the protruding electrode. (5) In addition to (1) to (4) of the first invention, (5) the step of the insulating film for forming the width of the base metal layer acts as an etching stopper. A wide underlying metal layer is obtained, which also enhances the mechanical and electrical performance of the bump electrode and the underlying metal layer. The effect is obtained.
【図１】第１の発明に係る一実施例の突起電極部の断面
図。FIG. 1 is a sectional view of a protruding electrode portion according to an embodiment of the first invention.
【図２】第１の発明に係る一実施例のプラズマアッシン
グ条件。FIG. 2 shows plasma ashing conditions of one embodiment according to the first invention.
【図３】第１の発明に係るプラズマアッシングによる実
験データ例。FIG. 3 is an example of experimental data by plasma ashing according to the first invention.
【図４】第１の発明に係るプラズマアッシングによる実
験データ例。FIG. 4 is an example of experimental data by plasma ashing according to the first invention.
【図５】図５（Ａ）は第２の発明に係る一実施例のレジ
ストパターンの構造断面図、同図（Ｂ）は第２の発明に
係る一実施例のレジストパターンの裾引き部の拡大図。FIG. 5A is a structural cross-sectional view of a resist pattern according to an embodiment of the second invention, and FIG. 5B is a sectional view of a footing portion of the resist pattern according to the embodiment of the second invention; Enlarged view.
【図６】第２の発明に係る突起電極部の断面図。FIG. 6 is a sectional view of a protruding electrode portion according to the second invention.
【図７】従来の突起電極（バンプ）部の断面図。FIG. 7 is a sectional view of a conventional protruding electrode (bump) portion.
【図８】ＴＡＢアセンブリプロセス説明図。FIG. 8 is an explanatory view of a TAB assembly process.
【図９】従来の突起電極形成プロセス図。FIG. 9 is a process chart for forming a conventional bump electrode.
1 電極 2 絶縁膜 2ｃ 段差 3、3L 下地金属層 3ｂ 段差 4、4ａ レジスト 4ｂ レジスト表面層 5、5ａ5ｃ 裾引き部 Ｗ1 レジストパターン幅 Ｗ2 下地金属層段差幅 Ｗ3 絶縁膜段差幅 ΔＷ 隙間 ＷL 下地金属幅1 Electrode 2 Insulating film 2c Step 3, 3L Base metal layer 3b Step 4, 4a Resist 4b Resist surface layer 5, 5a5c Footing part W 1 Resist pattern width W 2 Base metal layer step width W 3 Insulating film step width ΔW Gap WL Base metal width
Claims (2)
の製造方法において、電極上の保護膜表面に下地金属層
を形成する工程と、この下地金属層上にフォトレジスト
を設けパターン形成する工程と、このパターン形成され
た上記レジストをプラズマアッシングする工程と、上記
パターンに突起電極を形成する工程と、この突起電極を
マスクとして上記下地金属層をエッチングする工程とを
備えた半導体装置の製造方法。In a method of manufacturing a semiconductor device in which a bump electrode is provided on a chip, a step of forming a base metal layer on a surface of a protective film on the electrode, and a step of forming a pattern by providing a photoresist on the base metal layer A method of manufacturing a semiconductor device, comprising: plasma ashing the patterned resist; forming a projecting electrode on the pattern; and etching the base metal layer using the projecting electrode as a mask.
上に選択的に形成された絶縁膜と、この絶縁膜上に設け
られ上記電極と接続された下地金属層と、この下地金属
層上に形成される突起電極とを備えた半導体装置であっ
て、上記下地金属層には上記突起電極の幅部分に相対し
て段差が設けられ、この段差間の幅が上記突起電極の幅
より小さいことを特徴とする半導体装置。2. An electrode provided on a chip, an insulating film selectively formed on the electrode, a base metal layer provided on the insulating film and connected to the electrode, and a base metal layer provided on the chip. A projection electrode formed on the semiconductor device, wherein the base metal layer is provided with a step relative to a width portion of the projection electrode, and the width between the steps is larger than the width of the projection electrode. A semiconductor device which is small.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3261938A JP2985426B2 (en) | 1991-10-09 | 1991-10-09 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3261938A JP2985426B2 (en) | 1991-10-09 | 1991-10-09 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05102160A JPH05102160A (en) | 1993-04-23 |
| JP2985426B2 true JP2985426B2 (en) | 1999-11-29 |
Family
ID=17368772
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3261938A Expired - Lifetime JP2985426B2 (en) | 1991-10-09 | 1991-10-09 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2985426B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7064436B2 (en) | 2003-12-10 | 2006-06-20 | Fujitsu Limited | Semiconductor device and method of fabricating the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR3050865B1 (en) * | 2016-05-02 | 2018-10-12 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | METHOD FOR PRODUCING CONDUCTIVE INTERCONNECTIONS ON A SUBSTRATE AND INTERCONNECTIONS THUS OBTAINED |
-
1991
- 1991-10-09 JP JP3261938A patent/JP2985426B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7064436B2 (en) | 2003-12-10 | 2006-06-20 | Fujitsu Limited | Semiconductor device and method of fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05102160A (en) | 1993-04-23 |
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