JPS6313346B2 - - Google Patents
Info
- Publication number
- JPS6313346B2 JPS6313346B2 JP13193481A JP13193481A JPS6313346B2 JP S6313346 B2 JPS6313346 B2 JP S6313346B2 JP 13193481 A JP13193481 A JP 13193481A JP 13193481 A JP13193481 A JP 13193481A JP S6313346 B2 JPS6313346 B2 JP S6313346B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- convex portion
- forming
- wiring body
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010410 layer Substances 0.000 claims description 70
- 239000004020 conductor Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 239000011229 interlayer Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 238000000059 patterning Methods 0.000 description 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 125000005375 organosiloxane group Chemical group 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に係り、特に平
坦性のすぐれた多層配線構造の形成方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a multilayer wiring structure with excellent flatness.
半導体素子表面に多層配線を形成するに際し、
表面の凹凸に起因する配線体の断線や絶縁層の膜
切れの発生を防止するため、各層を極力平坦化す
ることが重要である。そのためかねてより平坦性
のすぐれた多層配線構造及びその製造方法が種々
提唱されている。 When forming multilayer wiring on the surface of a semiconductor element,
It is important to flatten each layer as much as possible in order to prevent disconnection of the wiring body and breakage of the insulating layer due to surface irregularities. Therefore, various multilayer wiring structures with excellent flatness and methods of manufacturing the same have been proposed for some time.
しかしそのいずれも実施するに際して、下層及
び上層配線体の接続構造を形成するためのパター
ニング工程において、位置ずれを生じる恐れがあ
る。そのため素子の設計に際しては当該工程にお
いて位置合せ余裕を設けねばならなかつた。 However, when carrying out either of these methods, there is a possibility that positional deviation may occur in the patterning process for forming the connection structure between the lower layer and the upper layer wiring body. Therefore, when designing the element, it is necessary to provide an alignment margin in the process.
本発明の目的は平坦性の良好な多層配線構造の
上層及び下層配線体の接続構造を自己整合法によ
り形成し得る半導体装置の製造方法を提供するこ
とにある。 An object of the present invention is to provide a method for manufacturing a semiconductor device in which a connection structure between upper and lower wiring bodies of a multilayer wiring structure with good flatness can be formed by a self-alignment method.
本発明の特徴は、半導体基板上に島状の第１の
導電体層を形成する工程と、該島状の第１の導電
体層上より半導体基板上に所定のパターンに従つ
て導出された第２の導電体層を選択的に形成する
と共に、該第２の導電体層の直下部を除く残りの
第１の導電体層を除去して凸部を有する下層配線
体を形成する工程と、半導体基板上に前記凸部上
面を露出し該凸部上面と略同一高さを有する層間
絶縁層を形成する工程と、該層間絶縁層上に前記
露出せる凸部表面と接続する上層配線体を形成す
る工程とを含むことにある。 The present invention is characterized by a step of forming an island-shaped first conductor layer on a semiconductor substrate, and a step of forming an island-shaped first conductor layer on the semiconductor substrate according to a predetermined pattern. selectively forming a second conductor layer and removing the remaining first conductor layer except for the area immediately below the second conductor layer to form a lower wiring body having a convex portion; , a step of exposing the upper surface of the convex portion on a semiconductor substrate and forming an interlayer insulating layer having substantially the same height as the upper surface of the convex portion; and an upper layer wiring body connecting the surface of the exposed convex portion on the interlayer insulating layer. and a step of forming.
以下本発明の一実施例を図面を用いて説明す
る。 An embodiment of the present invention will be described below with reference to the drawings.
第１図において、１は素子形成を終了したシリ
コン（Si）基板、２は二酸化シリコン（SiO2）
膜のような絶縁膜で、Si基板１表面の電極コンタ
クト窓（図示せず）部を除く他の部分を被覆す
る。このSiO2膜２上に所望の導電材料、例えば
アルミニウム（Al）を被着し、Al層３を形成し、
その上に所定のパターンに従つてホトレジスト膜
４を形成する。上記Al層３の厚さは例えば約
5000〔Å〕とする。 In Figure 1, 1 is a silicon (Si) substrate on which element formation has been completed, and 2 is silicon dioxide (SiO 2 ).
The surface of the Si substrate 1 except for the electrode contact window (not shown) is covered with an insulating film such as a film. A desired conductive material such as aluminum (Al) is deposited on this SiO 2 film 2 to form an Al layer 3,
A photoresist film 4 is formed thereon according to a predetermined pattern. The thickness of the Al layer 3 is, for example, approximately
5000 [Å].
このホトレジスト膜４をマスクとしてAl層３
の露出部分を選択的に除去し、次いでホトレジス
ト膜４を除去して第２図に見られる如く、島状の
第１のAl層３′を形成する。該第１のAl層３′は
図示せる如く端部をテーパ状に形成することが望
ましく、それには例えば燐酸（H3PO4）と硝酸
（HNO3）と酢酸（CH3COOH）とからなる混合
液による湿式エツチング法を用いればよい。 Using this photoresist film 4 as a mask, the Al layer 3 is
Then, the photoresist film 4 is removed to form an island-shaped first Al layer 3' as shown in FIG. The first Al layer 3' is desirably formed with a tapered end as shown in the figure . A wet etching method using a mixed solution may be used.
島状の第１のAl層３′の寸法は、後述する下層
及び上層の配線体間を接続する下層配線体の凸部
より大きなものとしておく。 The dimensions of the island-shaped first Al layer 3' are set to be larger than a convex portion of a lower layer wiring body that connects lower and upper layer wiring bodies, which will be described later.
次いで第３図に示すように、第１のAl層３′上
を含むSi基板１上に所望の導電材料例えばAlを
被着せしめてAl層５を例えば凡そ8000〔Å〕の厚
さに形成し、その上に所望のパターンのホトレジ
スト膜６を形成する。ここで留意すべき点はホト
レジスト膜６の一部が前記第１のAl層３′上を通
ることである。 Next, as shown in FIG. 3, a desired conductive material such as Al is deposited on the Si substrate 1 including the first Al layer 3' to form an Al layer 5 having a thickness of approximately 8000 Å. Then, a photoresist film 6 having a desired pattern is formed thereon. It should be noted here that a portion of the photoresist film 6 passes over the first Al layer 3'.
このように形成したホトレジスト膜６をマスク
として、例えば四弗化炭素（CF4）と酸素（O2）
の混合ガスを反応ガスに用いたプラズマエツチン
グ法等により、前記第２のAl層５の露出せる部
分を選択的に除去すると共に、その下層の第１の
Al層５の不要部を除去し、次いでマスクとして
用いたホトレジスト膜６を除去して、第４図に示
す如く下層配線体７を形成する。 Using the photoresist film 6 thus formed as a mask, for example, carbon tetrafluoride (CF 4 ) and oxygen (O 2 ) are exposed.
The exposed portion of the second Al layer 5 is selectively removed by a plasma etching method using a mixed gas of
Unnecessary portions of the Al layer 5 are removed, and then the photoresist film 6 used as a mask is removed to form a lower wiring body 7 as shown in FIG.
このようにして得られた下層配線体７は、所定
のパターンに形成された第２のAl層５′とその下
に部分的に残留する第１のAl層３″とからなり、
この第１のAl層３″が残留した部分は凸部８が形
成される。 The lower wiring body 7 obtained in this way consists of a second Al layer 5' formed in a predetermined pattern and a first Al layer 3'' partially remaining thereunder,
A convex portion 8 is formed in the portion where the first Al layer 3'' remains.
この凸部８は前述した如くホトレジスト膜６を
マスクとして第１及び第２のAl層３′，５を同時
にパターニングして形成されるので、第５図に見
られる如く、下層配線体７のパターンと凸部８の
位置関係は完全に合致している。即ち凸部８は下
層配線体に自己整合して形成される。従つて本実
施例においては、上記凸部８を形成するパターニ
ングのための位置合せ余裕を必要としない。 As described above, this convex portion 8 is formed by simultaneously patterning the first and second Al layers 3' and 5 using the photoresist film 6 as a mask, so that the pattern of the lower wiring body 7 as shown in FIG. The positional relationship between the convex portion 8 and the convex portion 8 is completely matched. That is, the convex portion 8 is formed in self-alignment with the lower wiring body. Therefore, in this embodiment, no alignment margin is required for patterning to form the convex portions 8.
なお第５図の破線の斜線を引いて示した部分
は、凸部８を形成するためのパターニング工程を
施こす前の第１のAl層３′を示す。このように第
１のAl層３′は予め凸部８を形成すべき位置に、
凸部８の寸法より大きく形成しておく。このよう
にすれば第１のAl層３′に対してホトレジスト膜
６が位置ずれを起こす心配もない。 Note that the portion indicated by the dashed diagonal line in FIG. 5 shows the first Al layer 3' before the patterning process for forming the convex portion 8 is performed. In this way, the first Al layer 3' is placed in advance at the position where the convex portion 8 is to be formed.
It is formed larger than the size of the convex portion 8. In this way, there is no fear that the photoresist film 6 will be misaligned with respect to the first Al layer 3'.
以上により凸部８を有する下層配線体７が形成
されたので、このあとの工程は通常の製造方法に
従つて進めることにより、平坦性のすぐれた多層
配線を形成し得る。 Since the lower wiring body 7 having the convex portions 8 has been formed as described above, a multilayer wiring with excellent flatness can be formed by proceeding with the subsequent steps according to the usual manufacturing method.
例えば特願昭55−033644号に提唱された製造方
法等を用いることができる。 For example, the manufacturing method proposed in Japanese Patent Application No. 55-033644 can be used.
即ち、第６図に示すように回転塗布法によりSi
基板１全面にポリラダ・オルガノシロキサン樹脂
或いはポリイミド樹脂等を塗布し、これに加熱処
理を施こして絶縁層９を形成する。これらの樹脂
膜はすぐれた平坦性を有するので、下地層に凹凸
が存在しても上述のように形成した絶縁層９表面
はほぼ平坦な面に形成される。下地の凹凸が激し
すぎる等の理由により、絶縁層９表面の平坦さが
なお不十分の場合には、第７図に示すようにその
上に更にホトレジスト膜１０を形成する。このよ
うにすればホトレジスト膜１０の表面はほぼ平坦
な面となる。 That is, as shown in Figure 6, Si is coated by spin coating.
Polylada organosiloxane resin, polyimide resin, or the like is applied to the entire surface of the substrate 1, and then heat treated to form an insulating layer 9. Since these resin films have excellent flatness, even if there are irregularities in the underlying layer, the surface of the insulating layer 9 formed as described above is formed to be a substantially flat surface. If the surface of the insulating layer 9 is still insufficiently flat because the underlying surface is too uneven, a photoresist film 10 is further formed thereon as shown in FIG. In this way, the surface of the photoresist film 10 becomes a substantially flat surface.
なお本工程において絶縁層９の表面は凸部８の
表面より高くしておくことが望ましい。 Note that in this step, it is desirable that the surface of the insulating layer 9 be higher than the surface of the convex portion 8.
次いで上記絶縁層９の表層部、もしくはホトレ
ジスト膜１０と絶縁層９の表層部を、例えばアル
ゴン（Ar）を用いたイオンミリング法により除
去して、第８図に示すように凸部８表面を露出さ
せる。イオンミリング法は材質によりエツチング
レートが殆んど変らない非選択性エツチング法で
あるので、凸部８及び絶縁層９′の表面はほぼ同
一高さに形成されると共に、凸部８表面が清浄化
されるという効果がある。なおここに得られた絶
縁層９′は層間絶縁層として用いられる。 Next, the surface layer of the insulating layer 9 or the surface layer of the photoresist film 10 and the insulating layer 9 is removed by, for example, ion milling using argon (Ar) to form the surface of the convex portion 8 as shown in FIG. expose. Since the ion milling method is a non-selective etching method in which the etching rate hardly changes depending on the material, the surfaces of the protrusions 8 and the insulating layer 9' are formed at almost the same height, and the surfaces of the protrusions 8 are clean. It has the effect of becoming Note that the insulating layer 9' obtained here is used as an interlayer insulating layer.
次いで第９図に示すように、凸部８表面に接続
するAl等よりなり、例えば凡そ１〔μm〕の厚さ
の上層配線体１１を層間絶縁層９′上に形成する。 Next, as shown in FIG. 9, an upper wiring body 11 made of Al or the like and having a thickness of approximately 1 μm, for example, is formed on the interlayer insulating layer 9' to be connected to the surface of the convex portion 8.
以上で本実施例による多層配線を具備した半導
体装置が完成する。このようにして得られた多層
配配線はきわめて平坦性にすぐれているのみなら
ず、上層及び下層を接続する凸部８を下層配線体
７と自己整合して形成するので位置合わせ余裕を
設ける必要がなく、従つてパターンを微細化し得
る。 With the above steps, a semiconductor device equipped with multilayer wiring according to this embodiment is completed. The multilayer wiring obtained in this way not only has excellent flatness, but also has a positioning margin that needs to be provided because the convex portion 8 connecting the upper and lower layers is formed in self-alignment with the lower layer wiring body 7. Therefore, the pattern can be made finer.
なお前記一実施例は二層配線を形成する例を掲
げて説明したが、本発明を用いて三層以上の多層
配線を形成し得ることは容易に理解されよう。 Although the above-mentioned embodiment has been described with reference to an example in which two-layer wiring is formed, it will be easily understood that the present invention can be used to form multi-layer wiring of three or more layers.
また前記一実施例では下層配線体のパターンが
第１のAl層上より一方向にのみ配設された例を
示したが、これは２以上の方向に配設してもよい
ことは勿論である。 Furthermore, in the above embodiment, an example was shown in which the pattern of the lower wiring body was arranged only in one direction from the top of the first Al layer, but it is of course possible to arrange it in two or more directions. be.
以上説明した如く、本発明により平坦性のすぐ
れた多層配線構造を形成するに際し、上層及び下
層配線体間の接続体を下層配線体と自己整合して
形成し得るので、素子を微細化、高密度化し得
る。 As explained above, when forming a multilayer wiring structure with excellent flatness according to the present invention, the connection body between the upper layer and the lower layer wiring body can be formed in self-alignment with the lower layer wiring body, so the element can be miniaturized and increased in size. Can be densified.
第１図〜第９図は本発明の一実施例を示す図
で、第５図は要部上面図、他は要部断面図であ
る。
図において、１はシリコン基板、３，３′，
３″は第１の導電体層、５，５′は第２の導電体
層、６はホトレジスト膜、７は下層配線体、８は
凸部、９，９′は層間絶縁層、１１は上層配線体
を示す。
1 to 9 are views showing one embodiment of the present invention, with FIG. 5 being a top view of the main part, and the others being sectional views of the main part. In the figure, 1 is a silicon substrate, 3, 3',
3'' is the first conductor layer, 5 and 5' are the second conductor layers, 6 is the photoresist film, 7 is the lower wiring body, 8 is the convex part, 9 and 9' are the interlayer insulating layers, and 11 is the upper layer. The wiring body is shown.
Claims (1)
さの島状に形成する工程と、該第１の導電体層上
を含む前記半導体基板上に第２の導電体層を形成
し、該第２の導電体層上に前記第１の導電体層上
を通る所定のパターンを有するレジスト膜を形成
し、該レジスト膜をマスクとして前記第２の導電
体層と前記第１の導電体層を選択的に除去して、
凸部を有する下層配線体を形成する工程と、前記
半導体基板上に該下層配線体の凸部上面を露出
し、且つ該凸部の上面と略同一高さを有する層間
絶縁層を形成する工程と、該層間絶縁層上に前記
露出せる下層配線体の凸部表面と接続する上層配
線体を形成する工程とを含むことを特徴とする半
導体装置の製造方法。1. Forming a first conductive layer in the form of an island of a predetermined size on a semiconductor substrate, and forming a second conductive layer on the semiconductor substrate including on the first conductive layer, A resist film having a predetermined pattern passing over the first conductor layer is formed on the second conductor layer, and the resist film is used as a mask to form a resist film on the second conductor layer and the first conductor layer. selectively removing layers;
a step of forming a lower layer wiring body having a convex portion; and a step of forming an interlayer insulating layer on the semiconductor substrate, exposing the upper surface of the convex portion of the lower layer wiring body and having approximately the same height as the upper surface of the convex portion. A method for manufacturing a semiconductor device, comprising the steps of: forming an upper layer wiring body on the interlayer insulating layer to connect to the surface of the exposed convex portion of the lower layer wiring body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13193481A JPS5833853A (en) | 1981-08-21 | 1981-08-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13193481A JPS5833853A (en) | 1981-08-21 | 1981-08-21 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5833853A JPS5833853A (en) | 1983-02-28 |
| JPS6313346B2 true JPS6313346B2 (en) | 1988-03-25 |
Family
ID=15069623
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13193481A Granted JPS5833853A (en) | 1981-08-21 | 1981-08-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5833853A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59195845A (en) * | 1983-04-21 | 1984-11-07 | Toshiba Corp | Fabrication of multilayer interconnection |
| JPS60110141A (en) * | 1983-11-18 | 1985-06-15 | Matsushita Electronics Corp | Manufacture of interlayer connecting wiring layer |
| JPH027470A (en) * | 1988-06-27 | 1990-01-11 | Toshiba Corp | Electrode wiring structure of compound semiconductor device |
| JPH0230137A (en) * | 1988-07-19 | 1990-01-31 | Nec Corp | Method forming wiring of semiconductor device |
-
1981
- 1981-08-21 JP JP13193481A patent/JPS5833853A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5833853A (en) | 1983-02-28 |
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| JPH0425157A (en) | Manufacture of semiconductor device | |
| JPS592351A (en) | Manufacture of semiconductor device |