JPS63205929A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63205929A JPS63205929A JP3945387A JP3945387A JPS63205929A JP S63205929 A JPS63205929 A JP S63205929A JP 3945387 A JP3945387 A JP 3945387A JP 3945387 A JP3945387 A JP 3945387A JP S63205929 A JPS63205929 A JP S63205929A
- Authority
- JP
- Japan
- Prior art keywords
- film
- width
- wiring
- conductor film
- stepped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 239000004020 conductor Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置、とりわけ、その配線構造に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device, and particularly to its wiring structure.
従来の技術
従来例を、第３図ａ−ｄの工程順断面図で説明すると、
半導体基板１上の絶縁膜２に、第３図ａに示すように段
差が存在し、この段差を横ぎって配線を形成する場合、
まず、絶縁膜２の表面に第３図すに示すように配線材料
である導体膜３を形成し、その上にレジスト４を塗布す
ると、第３図Ｃに示すように、段差部の凸部分のレジス
ト４は薄くなる。次にレジストパターンの形成をおこな
うが、レジスト４の膜厚に対してはその膜厚に適切な露
光量が存在し、平坦部に露光量を設定して、上記の段差
凸部分とそれ以外の部分との露光を同時におこなわれる
ので、段差凸部分の露光は過剰となる。すると第３図ｄ
に示すように、段差凸部分でのレジストパターンの幅が
細くなる。このような状態において下層の導体膜３をエ
ツチングすると、上記のレジストパターンの幅が細（な
ったところで、配線導体膜３の幅も細（なってしまう。Conventional technology A conventional example will be explained with reference to step-by-step cross-sectional views of FIGS. 3a to 3d.
When there is a step in the insulating film 2 on the semiconductor substrate 1 as shown in FIG. 3a, and wiring is formed across this step,
First, as shown in FIG. 3C, a conductor film 3, which is a wiring material, is formed on the surface of the insulating film 2, and a resist 4 is applied thereon. As shown in FIG. The resist 4 becomes thinner. Next, a resist pattern is formed, but there is an appropriate exposure amount for the film thickness of resist 4, and the exposure amount is set for the flat part, and the above-mentioned stepped convex part and other parts are Since the exposed portion is simultaneously exposed to light, the stepped portion is overexposed. Then, Figure 3 d
As shown in , the width of the resist pattern becomes narrower at the stepped portion. If the underlying conductor film 3 is etched in such a state, when the width of the resist pattern becomes narrow, the width of the wiring conductor film 3 also becomes narrow.
また上記のエツチングが完全な異方性でない場合、横方
向のエツチングも進行し、これにより、レジストパター
ンの幅のやせ細りの度合いが大きいときは、配線導体膜
３が上記の段差部の凸部分において断線してしまうこと
になる。Furthermore, if the above-mentioned etching is not completely anisotropic, lateral etching also progresses, and as a result, when the width of the resist pattern is narrowed to a large degree, the wiring conductor film 3 is formed in the convex portion of the step portion. This will result in a disconnection.
発明が解決しようとする問題点
上記のように配線を形成する半導体表面に段差がある場
合、その段差凸部で配線が細ったりあるいは断線したり
することがある。本発明ではこのような配線のやせ細り
ゃ断線を防ぐ方策を提供するものである。Problems to be Solved by the Invention As described above, when there is a step on the surface of a semiconductor on which wiring is formed, the wiring may become thin or broken at the raised portion of the step. The present invention provides a measure to prevent such thinning and disconnection of the wiring.
問題点を解決するための手段
本発明は、半導体基板上絶縁膜の段差部を横切る導体膜
配線の幅を、前記段の角頂部でその平面部より幅広く形
成した構成である。Means for Solving the Problems The present invention has a configuration in which the width of the conductor film wiring that crosses the stepped portion of the insulating film on the semiconductor substrate is made wider at the corner top portion of the step than at its flat surface.
作用
本発明によれば、予め、レジストパターンの幅の細りを
考慮して、その段差の角頂部でパターン幅を広くしてお
くことにより、同差部分での配線の断線を防ぐことがで
きる。According to the present invention, by taking into consideration the thinning of the width of the resist pattern and widening the pattern width at the corner apex of the step, it is possible to prevent wiring breakage at the same difference portion.
実施例
第１図は本発明実施例の要部拡大斜視図であり、第２図
は本発明をバイポーラトランジスタと適用した実施例の
平面図を示す。導体膜によるポンディングパッド５，６
下の酸化シリコン膜（絶縁膜）２とベース領域上の酸化
シリコン膜との間には１．５μｍの段差がある。ポンデ
ィングパッドからエミッタおよびベースのコンタクト窓
までの導体膜（電極）の幅は５μｍであるが上記の酸化
シリコン膜表面の段差部分において電極幅を１０ｕｌｌ
とした。このことにより、上記段差部分での電極の断線
を防ぐことができ歩留が向上した。Embodiment FIG. 1 is an enlarged perspective view of essential parts of an embodiment of the present invention, and FIG. 2 is a plan view of an embodiment in which the present invention is applied to a bipolar transistor. Bonding pads 5 and 6 made of conductive film
There is a step difference of 1.5 μm between the lower silicon oxide film (insulating film) 2 and the silicon oxide film on the base region. The width of the conductor film (electrode) from the bonding pad to the contact window of the emitter and base is 5 μm, but the electrode width is increased to 10 μm at the stepped portion of the silicon oxide film surface mentioned above.
And so. This made it possible to prevent disconnection of the electrodes at the stepped portions, thereby improving yield.
発明の効果
本発明によると、絶縁膜の段差部を横切る導体膜配線が
同段差部の角頂部で幅広（構成されたことにより、同導
体膜配線の断線がなくなり、品質向上が達せられる。Effects of the Invention According to the present invention, the conductor film wiring that crosses the stepped portion of the insulating film is configured to be wide at the corner apex of the stepped portion, thereby eliminating breakage of the conductive film wiring and improving quality.
第１図は本発明実施例装置の要部拡大斜視図、第２図は
本発明実施例トランジスタの電極部平面１・・・・・・
半導体基板、２・・・・・・絶縁膜、３・・・・・・導
体膜、４・・・・・・レジスト、５，６・・・・・・ポ
ンディングパッド。
代理人の氏名 弁理士 中尾敏男 ほか１名第１１！ｌ
／−手課体基榎２・−矩緑雁
第 ２ 図
第３図FIG. 1 is an enlarged perspective view of a main part of a device according to an embodiment of the present invention, and FIG. 2 is a plan view of an electrode portion 1 of a transistor according to an embodiment of the present invention.
Semiconductor substrate, 2... Insulating film, 3... Conductor film, 4... Resist, 5, 6... Bonding pad. Name of agent: Patent attorney Toshio Nakao and one other person No. 11! l
/-Tekitei Kien 2・-Rokuryokugandai 2 Figure 3
Claims (1)
、前記段の角頂部でその平面部より幅広く形成したこと
を特徴とする半導体装置。1. A semiconductor device, wherein a width of a conductor film wiring that crosses a stepped portion of an insulating film on a semiconductor substrate is formed to be wider at a corner top portion of the step than at a flat portion thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3945387A JPS63205929A (en) | 1987-02-23 | 1987-02-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3945387A JPS63205929A (en) | 1987-02-23 | 1987-02-23 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63205929A true JPS63205929A (en) | 1988-08-25 |
Family
ID=12553459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3945387A Pending JPS63205929A (en) | 1987-02-23 | 1987-02-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63205929A (en) |
-
1987
- 1987-02-23 JP JP3945387A patent/JPS63205929A/en active Pending
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