JPH0357617B2 - - Google Patents

Info

Publication number
JPH0357617B2
JPH0357617B2 JP59171953A JP17195384A JPH0357617B2 JP H0357617 B2 JPH0357617 B2 JP H0357617B2 JP 59171953 A JP59171953 A JP 59171953A JP 17195384 A JP17195384 A JP 17195384A JP H0357617 B2 JPH0357617 B2 JP H0357617B2
Authority
JP
Japan
Prior art keywords
metal
tool
semiconductor element
metal protrusions
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59171953A
Other languages
Japanese (ja)
Other versions
JPS6150339A (en
Inventor
Kenzo Hatada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP59171953A priority Critical patent/JPS6150339A/en
Publication of JPS6150339A publication Critical patent/JPS6150339A/en
Publication of JPH0357617B2 publication Critical patent/JPH0357617B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体素子もしくは半導体素子を搭載
するための基板に金属突起を形成する方法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for forming metal protrusions on a semiconductor element or a substrate for mounting a semiconductor element.

従来例の構成とその問題点 近年、半導体素子を多数個用いるデバイス、機
器の開発が促進されてきている。例えば、メモリ
ーカード、液晶やELデイスプレイパネル等があ
り、これらは、いずれも多数個のIC、LSIを一定
の面積を有する基板に、高密度にしかも薄型に搭
載しなければならない。IC，LSIの高密度の実装
手段として、フイルムキヤリヤ方式やフリツプチ
ツプ方式が公知であるが、次の様な問題がある。2. Description of the Related Art Structures of Conventional Examples and Their Problems In recent years, the development of devices and equipment that use a large number of semiconductor elements has been promoted. Examples include memory cards, liquid crystal displays, and EL display panels, all of which require a large number of ICs and LSIs to be mounted thinly and densely on a substrate with a certain area. Film carrier methods and flip-chip methods are known as high-density mounting means for ICs and LSIs, but they have the following problems.

いずれの方式も半導体素子の電極上に外部端子
と接続するための金属突起を形成しなければなら
ない。金属突起を形成するために、半導体素子表
面にバリヤメタルと呼ばれるCr−Cu、Ti−Pd等
の多層金属膜を被着し、次いで、前記半導体素子
の電極に相当する領域を開孔した感光性樹脂パタ
ーンを形成する。前記多層金属膜を一方の電極と
し、前記開孔部にAu、Cu、Ag、半田等のメツキ
処理をし、10〜30μｍの高さの金属突起を形成
し、不要となつた感光性樹脂パターンおよび多層
金属膜の一部を除去する。この様に半導体素子の
電極上に金属突起を形成するのに、多数の工程を
必要とし、この工程の途中において前記半導体素
子に損傷を与え、歩留りを低下さす原因となつて
いた。このために著じるしく製造コストが高くな
るばかりか、信頼性おも低下さすものであつた。 In either method, metal protrusions must be formed on the electrodes of the semiconductor element for connection to external terminals. In order to form metal protrusions, a multilayer metal film called a barrier metal such as Cr-Cu, Ti-Pd, etc. is deposited on the surface of the semiconductor element, and then a photosensitive resin is formed in which holes are formed in areas corresponding to the electrodes of the semiconductor element. form a pattern. The multilayer metal film is used as one electrode, and the opening is plated with Au, Cu, Ag, solder, etc. to form metal protrusions with a height of 10 to 30 μm, and the photosensitive resin pattern is no longer needed. and removing part of the multilayer metal film. In this way, forming metal protrusions on the electrodes of a semiconductor element requires a large number of steps, which causes damage to the semiconductor element during these steps, resulting in a decrease in yield. This not only significantly increases manufacturing costs but also significantly reduces reliability.

発明の目的 本発明はこのような従来の問題に鑑み、接続時
工程が著じるしく少なく、安価な接続方法を提供
することを目的とする。OBJECTS OF THE INVENTION In view of these conventional problems, it is an object of the present invention to provide an inexpensive connection method with significantly fewer steps during connection.

発明の構成 本発明は、半導体素子の電極と対応した位置に
金属突起物を形成した基板の前記金属突起物にツ
ールを接触させ加圧・加熱し、前記基板上の金属
突起物を剥離しツールに転写・接合する工程、前
記半導体素子の電極と前記ツール上の金属突起物
とを位置合せ、接合する工程により、前記基板上
の金属突起物を前記半導体素子の電極上に転写・
接合する半導体装置の製造方法を提供する。さら
にまた、本発明は、配線基板の配線パターンと対
応した位置に金属突起物を形成した基板の前記金
属突起物にツールを接触させ加圧・加熱し、前記
基板上の金属突起物を剥離しツールに転写・接合
する工程、前記配線基板の配線パターンと前記ツ
ール上の金属突起物とを位置合せ、接合して前記
基板上の金属突起物を配線基板の配線パターン上
に転写・接合する工程と、前記金属突起物と半導
体素子の電極とを接合する工程とを備えた方法を
提供する。Structure of the Invention The present invention provides a tool for contacting a metal protrusion of a substrate with metal protrusions formed at positions corresponding to electrodes of a semiconductor element, applying pressure and heating, and peeling off the metal protrusion on the substrate. The metal protrusions on the substrate are transferred and bonded onto the electrodes of the semiconductor element by the step of aligning and bonding the electrodes of the semiconductor element and the metal protrusions on the tool.
A method for manufacturing a semiconductor device by bonding is provided. Furthermore, in the present invention, a tool is brought into contact with the metal protrusions of a board on which metal protrusions are formed at positions corresponding to the wiring patterns of the wiring board, and the metal protrusions on the board are peeled off by applying pressure and heating. a step of transferring and bonding to a tool; a step of aligning and bonding the wiring pattern of the wiring board and the metal protrusions on the tool; and transferring and bonding the metal protrusions on the board onto the wiring pattern of the wiring board. and a step of bonding the metal protrusion and an electrode of a semiconductor element.

実施例の説明 第１図で第１の実施例を説明する。基板１はセ
ラミツク、ガラス等の絶縁体上にメツキ用電極と
なる金属膜が形成され、更にその上に絶縁膜が形
成され半導体素子の電極と対応した位置に開孔部
を有し、前記開孔部に金属突起２が形成される。
金属突起２は例えばAuで構成され、電解メツキ
法で前記開孔部上に形成される。ついで、少なく
とも半導体素子のチツプ寸法と同一寸法の底面を
したツール３と前記金属突起２とを位置合せし、
ツール３を下降４せしめる（第１図ａ）。Description of Embodiment A first embodiment will be described with reference to FIG. The substrate 1 has a metal film to serve as a plating electrode formed on an insulator such as ceramic or glass, an insulating film formed thereon, and an opening at a position corresponding to the electrode of the semiconductor element. A metal protrusion 2 is formed in the hole.
The metal protrusion 2 is made of Au, for example, and is formed on the opening by electrolytic plating. Then, aligning the metal protrusion 2 with the tool 3 whose bottom surface has at least the same size as the chip size of the semiconductor element,
Lower the tool 3 (Fig. 1a).

ツール３を基板１上の金属突起２に接触させ加
圧・加熱せしむれば基板１上の金属突起２はツー
ル３の底面に転写・接合される（第１図ｂ）。基
板の構成については第３図で詳細にのべるが、金
属突起を形成する開孔部内の下地の金属膜はメツ
キ処理が容易で、かつ容易に剥離できる材料で構
成される。またツール３は、その底面が多少の凹
凸を有し、金属突起と接し、加圧加熱されること
により、前記凹凸に金属突起が微少に喰い込み、
金属突起がツール側に転写する構成であつても良
いし、ツール底面に前記金属突起と比較的合金を
形成しやすい材料が設けられており、金属突起と
接した時に、少量の合金を形成することによつて
ツール側に金属突起が転写される構成であつても
良い。次に、ツール３に転写・接合された金属突
起２は半導体素子５の電極６と位置合せし、ツー
ル３で加圧・加熱７し（第１図ｃ）、ツール３を
上昇８させれば、金属突起２は半導体素子５の電
極６上に接合される（第１図ｄ）。ツール３の加
圧・加熱条件は、金属突起２がAuで、半導体素
子５の電極６がアルミニウム電極で構成されるな
らば、半導体素子５を100℃〜300℃に加熱した状
態ならば、ツールの温度は350℃〜500℃、加圧力
は金属突起１個当り30ｇ〜100ｇで接合できる。 When the tool 3 is brought into contact with the metal protrusion 2 on the substrate 1 and pressurized and heated, the metal protrusion 2 on the substrate 1 is transferred and bonded to the bottom surface of the tool 3 (FIG. 1b). The structure of the substrate will be described in detail in FIG. 3, but the underlying metal film in the opening where the metal protrusion is formed is made of a material that can be easily plated and easily peeled off. The bottom surface of the tool 3 has some unevenness, and when it comes into contact with the metal protrusion and is heated under pressure, the metal protrusion slightly bites into the unevenness.
The structure may be such that the metal protrusion is transferred to the tool side, or a material that is relatively easy to form an alloy with the metal protrusion is provided on the bottom of the tool, and when it comes into contact with the metal protrusion, a small amount of alloy is formed. In some cases, the metal protrusion may be transferred to the tool side. Next, the metal protrusions 2 transferred and bonded to the tool 3 are aligned with the electrodes 6 of the semiconductor element 5, and the tool 3 is pressed and heated 7 (FIG. 1c), and the tool 3 is raised 8. , the metal protrusion 2 is bonded onto the electrode 6 of the semiconductor element 5 (FIG. 1d). The pressurizing and heating conditions for the tool 3 are such that if the metal projections 2 are made of Au and the electrodes 6 of the semiconductor element 5 are made of aluminum electrodes, and if the semiconductor element 5 is heated to 100 to 300 degrees Celsius, the tool Bonding can be performed at a temperature of 350°C to 500°C and a pressure of 30g to 100g per metal protrusion.

次に他の実施例を第２図で説明する。基板上の
金属突起２をツール３に転写・接合した後、回路
基板１０の配線パターン１１と位置合せし、ツー
ル３を下降せしめる（第２図ａ）。ツールを下降
し、加圧・加熱すればツール３の金属突起２は回
路基板１０の配線パターン１１側に接合される
（第２図ｂ）。これにより配線パターン上に金属突
起が形成される。前記回路基板１０はエポキシ、
ガラス、セラミツクあるいは金属を母体にし表面
に絶縁体を形成した材料であり、配線パターン１
１は、Au又はCu、Agで形成され、Cuの場合に
はその表面にSn、半田、Au等の膜が形成され、
金属突起２と容易に合金を形成しやすい材料を用
いるものである。次にツール１３で半導体素子５
を保持し、半導体素子５の電極６と配線パターン
１１上の金属突起２とを位置合せ（第２図ｃ）
し、ツール１３を下降１２せしめ、加圧・加熱
（第１の実施例で説明した条件と同じ）し、ツー
ル１３を上昇１４すれば第２図ｄの如く半導体素
子５の電極６と配線パターン１１上の金属突起２
とが接合されるものである。 Next, another embodiment will be explained with reference to FIG. After the metal projections 2 on the substrate are transferred and bonded to the tool 3, they are aligned with the wiring pattern 11 of the circuit board 10, and the tool 3 is lowered (FIG. 2a). When the tool is lowered and pressurized and heated, the metal protrusion 2 of the tool 3 is joined to the wiring pattern 11 side of the circuit board 10 (FIG. 2b). As a result, metal protrusions are formed on the wiring pattern. The circuit board 10 is made of epoxy,
It is a material made of glass, ceramic, or metal as a base material with an insulator formed on the surface, and the wiring pattern 1
1 is formed of Au, Cu, or Ag; in the case of Cu, a film of Sn, solder, Au, etc. is formed on its surface;
A material that can easily form an alloy with the metal protrusion 2 is used. Next, use the tool 13 to remove the semiconductor element 5.
and align the electrodes 6 of the semiconductor element 5 and the metal protrusions 2 on the wiring pattern 11 (Fig. 2c)
Then, the tool 13 is lowered 12, pressurized and heated (under the same conditions as described in the first embodiment), and raised 14 to form the electrodes 6 of the semiconductor element 5 and the wiring pattern as shown in FIG. 2d. Metal protrusion 2 on 11
and are joined together.

以上のべた如く本発明は金属突起を別の基板に
形成し、これをツールに転写、次いで半導体素子
あるいは配線パターンに加圧・加熱により接合せ
しめるものである。したがつて、従来の如くバリ
ヤメタルの形成やエツチング等の複雑な工程を必
要としない。 As described above, in the present invention, metal protrusions are formed on another substrate, transferred to a tool, and then bonded to a semiconductor element or wiring pattern by pressure and heating. Therefore, there is no need for complicated processes such as forming and etching a barrier metal as in the prior art.

次に本発明の金属突起を形成するための基板の
構成例について第３図で説明する。ガラス、セラ
ミツク等の絶縁体２０上にito、Pt、Pd等のメツ
キの形成が良好でかつ附着力の弱い導電性材料２
１を全面に設け、この上に半導体素子の電極と対
応した位置に開孔２３を有するSiO2、Si3N4、
Al2O3等の絶縁膜２２を形成する。導電性材料２
１を一方の電極として電解メツキ処理すれば開孔
部２３に金属突起２４が形成される。 Next, an example of the structure of a substrate for forming metal protrusions of the present invention will be explained with reference to FIG. A conductive material 2 with good plating formation such as Ito, Pt, Pd, etc. on an insulator 20 such as glass or ceramic and with weak adhesion.
SiO 2 , Si 3 N 4 , which has openings 23 at positions corresponding to the electrodes of the semiconductor element.
An insulating film 22 of Al 2 O 3 or the like is formed. Conductive material 2
1 as one electrode, a metal protrusion 24 is formed in the opening 23 by electrolytic plating.

金属突起２４がツールに転写・接合され、基板
２０上に金属突起２４が存在しなくなれば、再度
メツキ処理し、繰辺し前記基板を用いるものであ
る。 Once the metal protrusions 24 are transferred and bonded to the tool, and the metal protrusions 24 no longer exist on the substrate 20, plating is performed again and the substrate is used.

発明の効果 (1) 半導体素子の電極や配線パターン上に金属突
起を形成するのに、従来必要としていたバリヤ
メタルの形成、フオトリングラフイ、エツチン
グ等の工程がまつたく不要となり、製造コスト
が著じるしく安価となりまた半導体素子や配線
パターンに処理する必要がないので歩留りの低
下や信頼性を低下さす事がない。Effects of the invention (1) To form metal protrusions on the electrodes and wiring patterns of semiconductor devices, the processes such as barrier metal formation, photolithography, and etching that were conventionally required are completely eliminated, and the manufacturing cost is significantly reduced. It is extremely inexpensive, and since there is no need to process semiconductor elements or wiring patterns, there is no reduction in yield or reliability.

(2) 基板上に形成した金属突起を一たんツールに
転写接合するために、金属突起間の位置寸法が
変動することなく正確に設定され、半導体素子
の電極や配線パターンに接合できるため、不完
全な信頼性の低い接合が発生しないばかりか、
基板から金属突起を転写・接合する時および半
導体素子の電極や配線パターンに接合する時の
位置合せが、ツールの外寸によつて設定できる
ので、位置合せが著じるしく容易である。すな
わちツールの底面の外寸を半導体素子の外寸と
同じくすれば、お互いの外寸のみを重なる如く
位置合せすれば良く、微細な半導体素子の電極
と金属突起の精度の高い位置合せを必要としな
い。この事は、同様に、金属突起を形成する基
板、配線パターン上に前記ツールの外寸と同じ
になる位置合せマークを形成しておけば良いも
のである。(2) Since the metal protrusions formed on the substrate are transferred and bonded to the tool once, the positional dimensions between the metal protrusions are set accurately without changing, and bonding to the electrodes and wiring patterns of the semiconductor element is possible, resulting in less defects. Not only will a completely unreliable bond not occur, but
Positioning when transferring and bonding metal protrusions from a substrate and bonding to electrodes and wiring patterns of a semiconductor element can be set based on the outer dimensions of the tool, making alignment extremely easy. In other words, if the outer dimensions of the bottom of the tool are made the same as the outer dimensions of the semiconductor element, it is only necessary to align the two outer dimensions so that they overlap, which requires highly accurate alignment of the minute electrodes of the semiconductor element and the metal protrusions. do not. This can be achieved by forming alignment marks having the same external dimensions as the tool on the substrate and wiring pattern on which the metal protrusions are to be formed.

【図面の簡単な説明】[Brief explanation of drawings]

第１図ａ〜ｄは本発明の第１の実施例を示す工
程断面図、第２図ａ〜ｄは本発明の他の実施例を
示す工程断面図、第３図は金属突起を形成する基
板の断面図である。 １……基板、２……金属突起、３……ツール、
５……半導体素子、６……電極、１０……回路基
板、１１……配線パターン。 1A to 1D are process cross-sectional views showing a first embodiment of the present invention, FIGS. 2A to 2D are process cross-sectional views showing another embodiment of the present invention, and FIG. 3 is a process cross-sectional view showing a process of forming a metal protrusion. FIG. 3 is a cross-sectional view of the substrate. 1... Board, 2... Metal protrusion, 3... Tool,
5... Semiconductor element, 6... Electrode, 10... Circuit board, 11... Wiring pattern.

Claims (1)

【特許請求の範囲】 １ 半導体素子の電極と対応した位置に金属突起
物を形成した基板の前記金属突起物にツールを接
触させ加圧・加熱し、前記基板上の金属突起物を
剥離しツールに転写・接合する工程、前記半導体
素子の電極と前記ツール上の金属突起物とを位置
合せ、接合する工程により、前記基板上の金属突
起物を前記半導体素子の電極上に転写・接合する
事を特徴とする半導体装置の製造方法。 ２ 配線基板の配線パターンと対応した位置に金
属突起物を形成した基板の前記金属突起物にツー
ルを接触させ加圧・加熱し、前記基板上の金属突
起物を剥離しツールに転写・接合する工程、前記
配線基板の配線パターンと前記ツール上の金属突
起物とを位置合せ、接合して前記基板上の金属突
起物を配線基板の配線パターン上に転写・接合す
る工程と、前記金属突起物と半導体素子の電極と
を接合する工程とを備えた事を特徴とする半導体
装置の製造方法。[Scope of Claims] 1. A tool is brought into contact with the metal protrusions of a substrate on which metal protrusions are formed at positions corresponding to the electrodes of the semiconductor element, and the metal protrusions on the substrate are peeled off by applying pressure and heat. transferring and bonding the metal protrusions on the substrate onto the electrodes of the semiconductor element by aligning and bonding the electrodes of the semiconductor element and the metal protrusions on the tool; A method for manufacturing a semiconductor device, characterized by: 2. A tool is brought into contact with the metal protrusions of the board on which metal protrusions are formed at positions corresponding to the wiring patterns of the wiring board, and pressure and heat are applied to peel off the metal protrusions on the board and transferred and bonded to the tool. a step of aligning and bonding the wiring pattern of the wiring board and the metal protrusion on the tool to transfer and bond the metal protrusion on the board onto the wiring pattern of the wiring board; and the metal protrusion 1. A method for manufacturing a semiconductor device, comprising the steps of: and bonding an electrode of a semiconductor element.
JP59171953A 1984-08-18 1984-08-18 Manufacture of semiconductor device Granted JPS6150339A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59171953A JPS6150339A (en) 1984-08-18 1984-08-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59171953A JPS6150339A (en) 1984-08-18 1984-08-18 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS6150339A JPS6150339A (en) 1986-03-12
JPH0357617B2 true JPH0357617B2 (en) 1991-09-02

Family

ID=15932842

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59171953A Granted JPS6150339A (en) 1984-08-18 1984-08-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6150339A (en)

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US8872771B2 (en) 2009-07-07 2014-10-28 Apple Inc. Touch sensing device having conductive nodes
US8933890B2 (en) 2003-11-25 2015-01-13 Apple Inc. Techniques for interactive input to portable electronic devices
US8952886B2 (en) 2001-10-22 2015-02-10 Apple Inc. Method and apparatus for accelerated scrolling
US9354751B2 (en) 2009-05-15 2016-05-31 Apple Inc. Input device with optimized capacitive sensing
US9360967B2 (en) 2006-07-06 2016-06-07 Apple Inc. Mutual capacitance touch sensing device
US9367151B2 (en) 2005-12-30 2016-06-14 Apple Inc. Touch pad with symbols based on mode
US9405421B2 (en) 2006-07-06 2016-08-02 Apple Inc. Mutual capacitance touch sensing device
US9454256B2 (en) 2008-03-14 2016-09-27 Apple Inc. Sensor configurations of an input device that are switchable based on mode

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8952886B2 (en) 2001-10-22 2015-02-10 Apple Inc. Method and apparatus for accelerated scrolling
US9009626B2 (en) 2001-10-22 2015-04-14 Apple Inc. Method and apparatus for accelerated scrolling
US8933890B2 (en) 2003-11-25 2015-01-13 Apple Inc. Techniques for interactive input to portable electronic devices
US9367151B2 (en) 2005-12-30 2016-06-14 Apple Inc. Touch pad with symbols based on mode
US9360967B2 (en) 2006-07-06 2016-06-07 Apple Inc. Mutual capacitance touch sensing device
US9405421B2 (en) 2006-07-06 2016-08-02 Apple Inc. Mutual capacitance touch sensing device
US8866780B2 (en) 2007-12-03 2014-10-21 Apple Inc. Multi-dimensional scroll wheel
US9454256B2 (en) 2008-03-14 2016-09-27 Apple Inc. Sensor configurations of an input device that are switchable based on mode
US9354751B2 (en) 2009-05-15 2016-05-31 Apple Inc. Input device with optimized capacitive sensing
US8872771B2 (en) 2009-07-07 2014-10-28 Apple Inc. Touch sensing device having conductive nodes

Also Published As

Publication number Publication date
JPS6150339A (en) 1986-03-12

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