JPH0360053A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0360053A JPH0360053A JP19552989A JP19552989A JPH0360053A JP H0360053 A JPH0360053 A JP H0360053A JP 19552989 A JP19552989 A JP 19552989A JP 19552989 A JP19552989 A JP 19552989A JP H0360053 A JPH0360053 A JP H0360053A
- Authority
- JP
- Japan
- Prior art keywords
- external input
- output circuit
- semiconductor chip
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 4
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路に関し、特にゲートアレイ方式
により形成される半導体集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit device formed by a gate array method.
従来、この種の半導体集積回路装置においては、外部入
出力回路が四つのチップ辺に対して平行に一段配置され
ている。第３図は従来の半導体集積回路装置の一例を示
す半導体チップの平面図である。この半導体集積回路装
置は、例えば、第３図に示されるように、半導体チップ
１上の外部入出力回路６−１〜ｎが半導体チップ１の周
辺に対して平行に複数個並び形成され、外部入出力回路
群７−１を形成していた。また、この外部入出力回路群
７−１〜７−４が、半導体チップ１の四辺にそれぞれ形
成されていた。Conventionally, in this type of semiconductor integrated circuit device, external input/output circuits are arranged in one stage parallel to four chip sides. FIG. 3 is a plan view of a semiconductor chip showing an example of a conventional semiconductor integrated circuit device. In this semiconductor integrated circuit device, for example, as shown in FIG. 3, a plurality of external input/output circuits 6-1 to 6-n on a semiconductor chip 1 are arranged parallel to the periphery of the semiconductor chip 1, and external It formed an input/output circuit group 7-1. Further, the external input/output circuit groups 7-1 to 7-4 were formed on each of the four sides of the semiconductor chip 1.
上述した従来の半導体集積回路装置においては、四つの
半導体チップ辺に対して平行に一段だけ外部入出力回路
群を配置していたので、形成されるべき内部論理回路領
域の形状は半導体チップの外形形状の相似な正方形ある
いは長方形になってしまう。一方、元来、内部論理回路
素子群を自動レイアウトすると、内部論理回路は中央付
近に集中してしまうので、その形成領域はほぼ円形状に
なるので、半導体チップの四隅の部分は空領域になって
しまうという無駄なスペースを生ずる。In the conventional semiconductor integrated circuit device described above, the external input/output circuit group is arranged in only one stage parallel to the four sides of the semiconductor chip, so the shape of the internal logic circuit area to be formed depends on the external shape of the semiconductor chip. They end up being squares or rectangles with similar shapes. On the other hand, originally, when the internal logic circuit elements are automatically laid out, the internal logic circuits are concentrated near the center, and the area where they are formed becomes approximately circular, leaving the four corners of the semiconductor chip as empty areas. This creates wasted space.
また、−辺の配置する外部入出力回路群数に制限があり
、制限以上のものを使用したい時はチップサイズの大き
な下地を使用しなければならない。Further, there is a limit to the number of external input/output circuit groups that can be arranged on the - side, and if it is desired to use more than the limit, a base with a large chip size must be used.
そのため、必要以上の内部論理回路部を持った下地を使
用しなければならなくなり、集積度の高い半導体集積回
路装置が得られないという欠点がある。Therefore, it is necessary to use a base having more internal logic circuit parts than necessary, and there is a drawback that a semiconductor integrated circuit device with a high degree of integration cannot be obtained.
本発明の目的は、かかる問題点を解消する半導体集積回
路装置を提供することである。An object of the present invention is to provide a semiconductor integrated circuit device that solves these problems.
本発明の半導体集積回路装置は、内部論理回路部と外部
入出力回路群の二つの形成領域が明確に分かれているゲ
ートアレイ方式の半導体集積回路装置において、半導体
チップの四辺に沿って形成される第１の外部入出力回路
群と、一端が前記半導体チップの４隅より伸びるととも
に前記第１の外部入出力回路群と並んで形成される第２
の外部入出力回路群とを有している。The semiconductor integrated circuit device of the present invention is a gate array type semiconductor integrated circuit device in which two formation regions, an internal logic circuit section and an external input/output circuit group, are clearly separated, and are formed along the four sides of a semiconductor chip. a first external input/output circuit group, and a second external input/output circuit group, one end of which extends from the four corners of the semiconductor chip and is formed in line with the first external input/output circuit group.
It has a group of external input/output circuits.
〔実施例〕 次に本発明について図面を参照して説明する。〔Example〕 Next, the present invention will be explained with reference to the drawings.
第１図は、本発明の半導体集積回路装置の一実施例を示
す半導体チップの平面図である。この半導体集積回路装
置は、第１図に示されるように、半導体チップ上の一辺
に沿ってｎ個の外部入出力回路１−１〜ｎによって形成
される外部入出力回路群２−１を配置し、それと同様に
他の辺にも外部入出力回路群２−２．２−３．２−４を
配置し、また、その内側の４隅に外部入出力回路群２−
５〜８が配置されている。このように配置することによ
って、内部論理回路領域３−１の形状を自動レイアウト
のもっとも効率のよい円形形状にすることができる。第
２図（ａ）及び（ｂ）は、本発明の半導体集積回路装置
の他の実施例を示す半導体チップの平面図である。FIG. 1 is a plan view of a semiconductor chip showing an embodiment of the semiconductor integrated circuit device of the present invention. As shown in FIG. 1, this semiconductor integrated circuit device has an external input/output circuit group 2-1 formed by n external input/output circuits 1-1 to n arranged along one side of a semiconductor chip. Similarly, external input/output circuit groups 2-2.2-3.2-4 are arranged on the other sides, and external input/output circuit groups 2-2.2-3.2-4 are arranged on the inner four corners.
5 to 8 are arranged. By arranging in this manner, the shape of the internal logic circuit area 3-1 can be made into a circular shape that is most efficient for automatic layout. FIGS. 2(a) and 2(b) are plan views of a semiconductor chip showing another embodiment of the semiconductor integrated circuit device of the present invention.
第２図（ａ）においてチップサイズの一次元方向の制限
がＸであるとき、すなわち、半導体チップ１の一辺がＸ
であるとき外部入出力回路群４−１が最大ｘ１までとり
うるとすると、一つの外部入出力回路の幅がｘ２とすれ
ば、外部入出力回路の配置できる数はＸＩ／Ｘ２より少
ない数になる。そこでこれより多く配置したい時には、
第２図（ｂ）のように、外部入出力回路部４−２を配置
することにより、この問題を解決できる。このように、
本発明は、中央に形成される内部論理回路領域の大きさ
に応じて、半導体チップの四辺に沿って形成された第１
の外部入出力回路群の内側に並ぶとともに半導体チップ
の４隅より伸びるように第２の外部入出力回路群を形成
することである。In FIG. 2(a), when the limit in the one-dimensional direction of the chip size is X, that is, one side of the semiconductor chip 1 is
If the external input/output circuit group 4-1 can have a maximum of x1, then if the width of one external input/output circuit is x2, the number of external input/output circuits that can be arranged is less than XI/X2. Become. Therefore, if you want to place more than this,
This problem can be solved by arranging the external input/output circuit section 4-2 as shown in FIG. 2(b). in this way,
According to the present invention, the first area formed along the four sides of the semiconductor chip is
A second external input/output circuit group is formed to line up inside the external input/output circuit group and extend from the four corners of the semiconductor chip.
以上説明したように本発明は、半導体チップの側面に沿
って形成される第１の外部入出力回路群の内側に並ぶと
ともに前記半導体チップの４隅より伸びて形成される第
２の外部入出力回路群を設けることによって、集積度の
高い半導体集積回路装置が得られるという効果がある。As described above, the present invention provides second external input/output circuits arranged inside a first external input/output circuit group formed along the side surface of a semiconductor chip and extending from the four corners of the semiconductor chip. By providing the circuit group, there is an effect that a semiconductor integrated circuit device with a high degree of integration can be obtained.
第１図は、本発明の半導体集積回路装置の一実施例を示
す半導体チップの平面図、第２図は、本発明の半導体集
積回路装置の他の実施例を示す半導体チップの平面図、
第３図は従来の半導体集積回路装置の一例を示す半導体
チップの平面図である。
１・・・半導体チップ、２−１〜８．４−１〜２．７−
１〜４・・・外部入出力回路群、３−１・・・内部論理
回路部、５−１〜ｎ、６−１〜ｎ・・・外部入出力回路
。FIG. 1 is a plan view of a semiconductor chip showing one embodiment of the semiconductor integrated circuit device of the present invention, FIG. 2 is a plan view of a semiconductor chip showing another embodiment of the semiconductor integrated circuit device of the present invention,
FIG. 3 is a plan view of a semiconductor chip showing an example of a conventional semiconductor integrated circuit device. 1... Semiconductor chip, 2-1 to 8.4-1 to 2.7-
1-4... External input/output circuit group, 3-1... Internal logic circuit section, 5-1-n, 6-1-n... External input/output circuit.
Claims (1)
明確に分かれているゲートアレイ方式の半導体集積回路
装置において、半導体チップの四辺に沿って形成される
第１の外部入出力回路群と、一端が前記半導体チップの
４隅より伸びるとともに前記第１の外部入出力回路群と
並んで形成される第２の外部入出力回路群とを有するこ
とを特徴とする半導体集積回路装置。In a gate array type semiconductor integrated circuit device in which two formation areas, an internal logic circuit section and an external input/output circuit group, are clearly separated, a first external input/output circuit group and a first external input/output circuit group formed along the four sides of the semiconductor chip are used. A semiconductor integrated circuit device comprising: a second external input/output circuit group, one end of which extends from the four corners of the semiconductor chip and is formed in parallel with the first external input/output circuit group.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19552989A JPH0360053A (en) | 1989-07-27 | 1989-07-27 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19552989A JPH0360053A (en) | 1989-07-27 | 1989-07-27 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0360053A true JPH0360053A (en) | 1991-03-15 |
Family
ID=16342606
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19552989A Pending JPH0360053A (en) | 1989-07-27 | 1989-07-27 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0360053A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6134704A (en) * | 1998-04-03 | 2000-10-17 | International Business Machines Corporation | Integrated circuit macro apparatus |
| JP2007155494A (en) * | 2005-12-05 | 2007-06-21 | Kurabo Ind Ltd | Twin flow cell and concentration measuring system using it |
-
1989
- 1989-07-27 JP JP19552989A patent/JPH0360053A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6134704A (en) * | 1998-04-03 | 2000-10-17 | International Business Machines Corporation | Integrated circuit macro apparatus |
| JP2007155494A (en) * | 2005-12-05 | 2007-06-21 | Kurabo Ind Ltd | Twin flow cell and concentration measuring system using it |
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