JPS6252943A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6252943A
JPS6252943A JP60192545A JP19254585A JPS6252943A JP S6252943 A JPS6252943 A JP S6252943A JP 60192545 A JP60192545 A JP 60192545A JP 19254585 A JP19254585 A JP 19254585A JP S6252943 A JPS6252943 A JP S6252943A
Authority
JP
Japan
Prior art keywords
chip
integrated circuit
bonding pads
capacitance elements
capacitance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60192545A
Other languages
Japanese (ja)
Inventor
Tatsuya Koyama
達也 小山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP60192545A priority Critical patent/JPS6252943A/en
Publication of JPS6252943A publication Critical patent/JPS6252943A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11898—Input and output buffer/driver structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the size of a chip by providing capacitance elements in all spaces between all bonding pads which are arranged in the circumference of an integrated circuit chip. CONSTITUTION:Bonding pads 4, 4... are arranged in the circumference of an integrated circuit chip divided by scribe lines 7. Further, capacitance elements 1 are provided between respective bonding pads 4. Necessary capacity is distributed to circuit blocks 3, 3, 3 and 3, which are provided at four corners of the chip respectively, by connecting necessary number of the capacitance elements 1 with external wirings 2. In the drawings, the reference numeral 5 denotes an I/O buffer and the reference numeral 6 denotes an internal cell.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路、特に、ダイオード。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit, particularly a diode.

トランジスタなどの素子を予じめチップ内に形成してお
き、蒸着配線の段階で素子間の接続を色々選択し、それ
ぞれ異なった製品を得ることのできるマスタスライス方
式の半導体集積回路装ｆＫ関する。The present invention relates to a master slicing type semiconductor integrated circuit device fK in which elements such as transistors are formed in advance in a chip and various connections between the elements are selected at the stage of vapor deposition wiring to obtain different products.

〔従来の技術〕[Conventional technology]

従来、上述のマスタスライス方式半導体集積回路装置に
おいて、前記集積回路チップ内回路で必要とされる容量
は、容量を必要とする回路近傍に必要な容量値分の容量
素子を形成していた。Conventionally, in the above-described master slice type semiconductor integrated circuit device, the capacitance required in the circuit within the integrated circuit chip has been achieved by forming a capacitive element with a required capacitance value in the vicinity of the circuit that requires the capacitance.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のチップ内容量配置では、容量を必要とす
る回路を数多く含むマスタスライス方式半導体集積回路
装量においては、チップ内素子配置有効面積にしめる容
量素子の面積の割合が大きく、又、大きな容量値を必要
とする容量を形成する場合、当然のことながら容量素子
自体も大きくなってしまう。その結果、チップサイズの
増大がさけられなくなシ、集積度の低下、さらには歩留
シの低下という欠点を生み出す。In the conventional chip capacity arrangement described above, in a master slice semiconductor integrated circuit device that includes many circuits that require capacitance, the ratio of the area of the capacitive element to the effective area for element arrangement within the chip is large; When forming a capacitor that requires a large value, the capacitive element itself naturally becomes large. As a result, there are disadvantages such as an unavoidable increase in chip size, a decrease in the degree of integration, and further a decrease in yield.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置は、マスタスライス方式半導体集積
回路装置において、前記集積回路チップ周辺に配列され
たボンディングパッドのパッド間全てに容量素子を配置
し、それらを外部配線等で相互接続し、チップ内回路で
必要とされる容量あるいは電源安定化の為の容量として
使用することによシ、今まで容量を必要とする回路近傍
につくっていた容量素子をはふき、その分チップサイズ
の縮小を行なう。The semiconductor device of the present invention is a master slice type semiconductor integrated circuit device, in which capacitive elements are arranged between all bonding pads arranged around the integrated circuit chip, and these are interconnected by external wiring etc. By using it as the capacitance required in the circuit or for power supply stabilization, it is possible to eliminate the capacitive elements that were previously created near the circuits that require capacitance, and reduce the chip size accordingly. .

〔実施例〕〔Example〕

つぎに実施例により本発明を説明する。 Next, the present invention will be explained with reference to Examples.

第１図は本発明の一実施例の平面図、第２図は第１図の
丸印内の部分拡大図である。これらの図において、スク
ライブライン７にて区画されている集積回路チップの周
辺には、ボンディングバット４，４．・・・・・・が配
列されている。さらに、各ボンディングパッド４の間に
は、容量素子１が配置されている。そして、チップの四
隅部に、それぞれ設けられている回路ブロック３，３，
３．３に必要な容量を、容量素子１の所要個数を外部配
線２で接続して、回路ブロック３に振り分けている。FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is an enlarged view of the parts within the circles in FIG. In these figures, bonding butts 4, 4 . ... are arranged. Further, a capacitive element 1 is arranged between each bonding pad 4 . Circuit blocks 3, 3, and 3 are provided at the four corners of the chip, respectively.
The capacitance required for 3.3 is distributed to circuit blocks 3 by connecting the required number of capacitive elements 1 with external wiring 2.

なお、５は入出力バッファ、６は内部セルを示す。Note that 5 indicates an input/output buffer, and 6 indicates an internal cell.

〔発明の効果〕〔Effect of the invention〕

以上説明したように１本発明の半導体装置によれば、マ
スタスライス方式半導体集積回路装置内部に従来方法で
形成していた容量素子をはふき、チップ周辺に配列され
たボンディングパッドのパッド間合てに容量素子を配置
している為、チップサイズが縮小でき、集積度及び歩留
シの向上が可能となる。またそれら容量素子の接続方法
により、連光な容量値を得ることができる。As explained above, according to the semiconductor device of the present invention, the capacitive element formed by the conventional method inside the master slice type semiconductor integrated circuit device is removed, and the pad spacing of the bonding pads arranged around the chip is improved. Since the capacitive element is placed in the chip, the chip size can be reduced and the degree of integration and yield can be improved. Further, depending on the method of connecting these capacitive elements, continuous light capacitance values can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例の平面図、第２図は館１図の
丸印内の部分拡大図である。 １・・・・・・容量素子、２・・・・・・容量素子接続
の外部配線、３・・・・・・容量を必要とする回路ブロ
ック、４・・・・・・ボンディングパッド、５・・・・
・・人出力バッ７ア、６・・・・・・内部セル、７・・
・・・・スクライプ線。 ／、− 代理人　弁理士　　内　原　　　晋／、−“こ。 第　ｉ　図 易２図FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is an enlarged view of the parts within the circles in FIG. 1... Capacitive element, 2... External wiring for connecting the capacitive element, 3... Circuit block requiring capacitance, 4... Bonding pad, 5・・・・・・
...Person output buffer 7a, 6...Internal cell, 7...
...Scripe line. /, - Agent Patent Attorney Susumu Uchihara /, - “K.

Claims (1)

【特許請求の範囲】[Claims] マスタスライス方式半導体集積回路装置において、前記
集積回路チップ周辺に配列されたボンディングパッドの
パッド間全てに容量素子が配置されていることを特徴と
する半導体装置。1. A master slice type semiconductor integrated circuit device, wherein a capacitive element is arranged between all bonding pads arranged around the integrated circuit chip.
JP60192545A 1985-08-30 1985-08-30 Semiconductor device Pending JPS6252943A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60192545A JPS6252943A (en) 1985-08-30 1985-08-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60192545A JPS6252943A (en) 1985-08-30 1985-08-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6252943A true JPS6252943A (en) 1987-03-07

Family

ID=16293060

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60192545A Pending JPS6252943A (en) 1985-08-30 1985-08-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6252943A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01196162A (en) * 1988-01-30 1989-08-07 Sony Corp Semiconductor device
CN110739299A (en) * 2018-07-20 2020-01-31 三星电子株式会社 Semiconductor package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01196162A (en) * 1988-01-30 1989-08-07 Sony Corp Semiconductor device
CN110739299A (en) * 2018-07-20 2020-01-31 三星电子株式会社 Semiconductor package
CN110739299B (en) * 2018-07-20 2024-01-09 三星电子株式会社 Semiconductor package

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