JPH073637Y2 - Bonding pattern - Google Patents

Bonding pattern

Info

Publication number
JPH073637Y2
JPH073637Y2 JP1989024503U JP2450389U JPH073637Y2 JP H073637 Y2 JPH073637 Y2 JP H073637Y2 JP 1989024503 U JP1989024503 U JP 1989024503U JP 2450389 U JP2450389 U JP 2450389U JP H073637 Y2 JPH073637 Y2 JP H073637Y2
Authority
JP
Japan
Prior art keywords
bonding pattern
bonding
chip
pattern
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1989024503U
Other languages
Japanese (ja)
Other versions
JPH02114931U (en
Inventor
正行 清宮
Original Assignee
セイコー電子工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by セイコー電子工業株式会社 filed Critical セイコー電子工業株式会社
Priority to JP1989024503U priority Critical patent/JPH073637Y2/en
Publication of JPH02114931U publication Critical patent/JPH02114931U/ja
Application granted granted Critical
Publication of JPH073637Y2 publication Critical patent/JPH073637Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Wire Bonding (AREA)

Description

【考案の詳細な説明】 〔産業上の利用分野〕 本考案は、ICチップを搭載する回路基板に関し、特に千
鳥状に配設された第二ボンディングパターンに関する。[Detailed Description of the Invention] [Industrial field of application] The present invention relates to a circuit board on which an IC chip is mounted, and more particularly to a second bonding pattern arranged in a staggered pattern.

〔従来の技術〕 第２図に従来の千鳥状に配設された第２ボンディングパ
ターンを示す。[Prior Art] FIG. 2 shows a conventional second zigzag-shaped bonding pattern.

図面において第二ボンディングパターン1a及び1bは、各
々四角形で形成されており、かつICチップ２より近距離
の第二ボンディングパターン1aと遠距離の第二ボンディ
ングパターン1bとは一定の距離l1を持つように千鳥状に
配設されている。In the drawing, the second bonding patterns 1a and 1b are each formed in a quadrangle, and the second bonding pattern 1a located closer to the IC chip 2 and the second bonding pattern 1b located farther from the IC chip 2 have a constant distance l 1 . It is arranged in a staggered manner.

〔考案が解決しようとする問題点〕[Problems to be solved by the invention]

しかし乍らこれらのパターンでは、回路基板製造工程内
でパターン同志のショートが起こらないように、ICチッ
プ２より近距離の第二ボンディングパターン1aと、ICチ
ップ２より遠距離の第二ボンディングパターン1bとの間
にスキマl2を設ける必要があり、そのためにICチップ２
より遠距離の第二ボンディングパターン1bとICチップ２
上の第一ボンディングパターンとの間の距離l3が大きく
なってしまい、それだけ実装面積が大きくなってしまう
という欠点があった。However, with these patterns, the second bonding pattern 1a, which is closer to the IC chip 2, and the second bonding pattern 1b, which is farther from the IC chip 2, are formed so that short circuits between the patterns do not occur in the circuit board manufacturing process. It is necessary to provide a gap l 2 between the IC chip 2 and
Second bonding pattern 1b and IC chip 2 at a longer distance
There is a drawback that the distance l 3 from the first bonding pattern above becomes large and the mounting area becomes large accordingly.

本考案は従来の上記欠点を除去する為になされたもので
あり、その目的とするところは実装面積を縮小化するこ
とを可能とした第二ボンディングパターンを提供するこ
とにある。The present invention has been made to eliminate the above-mentioned drawbacks of the related art, and an object thereof is to provide a second bonding pattern capable of reducing the mounting area.

〔問題点を解決するための手段〕[Means for solving problems]

本考案は、千鳥状に配設された第二ボンディングパター
ンを、各々互いに噛合状に配設することにした。In the present invention, the second bonding patterns arranged in a zigzag pattern are arranged so as to mesh with each other.

〔作用〕[Action]

これにより、ICチップ上の第一ボンディングパターンか
ら第二ボンディングパターンまでの距離を短縮すること
ができ実装面積を縮小することが可能となった。As a result, the distance from the first bonding pattern to the second bonding pattern on the IC chip can be shortened and the mounting area can be reduced.

〔実施例〕〔Example〕

次に本考案の実施例を図面に基づいて説明する。 Next, an embodiment of the present invention will be described with reference to the drawings.

第１図は本考案の実施例のボンディングパターンの要部
平面図である。FIG. 1 is a plan view of an essential part of a bonding pattern according to an embodiment of the present invention.

第１図に示すように、回路基板４上にICチップ２を実装
する。この時ICチップ２上の第一ボンディングパターン
３に相対応して、回路基板４上に、第一の端子配設部と
しての第二ボンディングパターン1Aと、第二の端子配設
部としての第二ボンディングパターン1Bとが各々２列に
しかも千鳥状に配設されている。しかもICチップ２から
より近距離にある第二ボンディングパターン1Aとそれよ
り遠距離にある第二ボンディングパターン1Bの各々の形
状は、図のようにそれぞれ互いに噛合状に形成配置され
ている。As shown in FIG. 1, the IC chip 2 is mounted on the circuit board 4. At this time, corresponding to the first bonding pattern 3 on the IC chip 2, the second bonding pattern 1A as the first terminal arrangement portion and the second bonding pattern 1A as the second terminal arrangement portion are provided on the circuit board 4. The two bonding patterns 1B are arranged in two rows and in a zigzag pattern. Moreover, the respective shapes of the second bonding pattern 1A located closer to the IC chip 2 and the second bonding pattern 1B located farther from the IC chip 2 are formed and arranged so as to mesh with each other as shown in the figure.

図に明示されているように千鳥状に配設された第二ボン
ディングパターン1Aと第二ボンディングパターン1Bの各
々の間のスキマL2を第２図に示す従来のボンディングパ
ターン1aとボンディングパターン1B間のスキマl2を仮に
同距離（L2＝l1）としても、第二ボンディングパターン
1Aと第二ボンディングパターン1Bのそれぞれの中心の間
の有効距離L1は、第二図に示す従来のボンディングパタ
ーン1aとボンディングパターン1b間のそれぞれの中心の
間の有効距離l1より短縮（L2＜l1）することが可能とな
る。するとICチップ２上の第一ボンディングパターン３
と第二ボンディングパターン1Bとの間の距離L3は、第２
図に示す従来のICチップ２上の第一ボンディングパター
ン３と第二ボンディングパターン1bとの間の距離l3より
短縮（L3＜l3）することが可能となり、その分リードワ
イヤ５を短縮することができ、実装面積を縮小すること
が可能となる。As shown in FIG. 2 , a gap L 2 between each of the second bonding pattern 1A and the second bonding pattern 1B arranged in a zigzag pattern is shown in FIG. 2 between the conventional bonding pattern 1a and the bonding pattern 1B. Even if the gap l 2 of is the same distance (L 2 = l 1 ), the second bonding pattern
The effective distance L 1 between the centers of 1A and the second bonding pattern 1B is shorter than the effective distance l 1 between the centers of the conventional bonding patterns 1a and 1b shown in FIG. 2 (L 2 <l 1 ) is possible. Then, the first bonding pattern 3 on the IC chip 2
The distance L 3 between the second bonding pattern 1B and the second bonding pattern 1B is the second
The distance l 3 between the first bonding pattern 3 and the second bonding pattern 1b on the conventional IC chip 2 shown in the figure can be shortened (L 3 <l 3 ) and the lead wire 5 can be shortened accordingly. Therefore, the mounting area can be reduced.

〔考案の効果〕[Effect of device]

本考案によれば千鳥状に配設された第二ボンディングパ
ターンをそれぞれ噛合状に配設することができるので、
リードワイヤを短縮することができ、実装面積の縮小化
が可能となる。According to the present invention, it is possible to arrange the second bonding patterns arranged in a staggered manner in a meshed manner,
The lead wire can be shortened, and the mounting area can be reduced.

【図面の簡単な説明】[Brief description of drawings]

第１図はこの考案の一実施例のボンディングパターンの
要部平面図、第２図は従来例の要部平面図である。 1A、1B……第二ボンディングパターン 1a、1b……第二ボンディングパターン ２……ICチップ ３……第一ボンディングパターン ４……回路基板 ５……リードワイヤFIG. 1 is a plan view of an essential part of a bonding pattern according to an embodiment of the present invention, and FIG. 2 is a plan view of an essential part of a conventional example. 1A, 1B …… second bonding pattern 1a, 1b …… second bonding pattern 2 …… IC chip 3 …… first bonding pattern 4 …… circuit board 5 …… lead wire

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項１】回路基板上にICチップを搭載し、ICチップ
上の第一ボンディングパターンと回路基板上の第二ボン
ディングパターンとの間をワイヤボンディングによって
接続をとる回路基板のボンディングパターンにおいて、
前記第二ボンディングパターンの各々が第一の端子配設
部あるいは第二の端子配設部の一方を交互に有してい
て、前記第一の端子配設部と第二の端子配設部とが千鳥
状に配設されるとともに、噛合状に形成配置されている
ことを特徴としたボンディングパターン。1. A bonding pattern of a circuit board, wherein an IC chip is mounted on a circuit board, and a first bonding pattern on the IC chip and a second bonding pattern on the circuit board are connected by wire bonding.
Each of the second bonding patterns alternately has one of the first terminal arrangement portion or the second terminal arrangement portion, and the first terminal arrangement portion and the second terminal arrangement portion The bonding patterns are characterized in that they are arranged in a zigzag pattern and are formed in a meshed shape.
JP1989024503U 1989-03-03 1989-03-03 Bonding pattern Expired - Lifetime JPH073637Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989024503U JPH073637Y2 (en) 1989-03-03 1989-03-03 Bonding pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989024503U JPH073637Y2 (en) 1989-03-03 1989-03-03 Bonding pattern

Publications (2)

Publication Number Publication Date
JPH02114931U JPH02114931U (en) 1990-09-14
JPH073637Y2 true JPH073637Y2 (en) 1995-01-30

Family

ID=31244405

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989024503U Expired - Lifetime JPH073637Y2 (en) 1989-03-03 1989-03-03 Bonding pattern

Country Status (1)

Country Link
JP (1) JPH073637Y2 (en)

Also Published As

Publication number Publication date
JPH02114931U (en) 1990-09-14

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