JPH04334055A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH04334055A JPH04334055A JP10298391A JP10298391A JPH04334055A JP H04334055 A JPH04334055 A JP H04334055A JP 10298391 A JP10298391 A JP 10298391A JP 10298391 A JP10298391 A JP 10298391A JP H04334055 A JPH04334055 A JP H04334055A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor integrated
- internal logic
- integrated circuit
- clock driver
- circuit section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は半導体集積回路装置に関
し、特にゲートアレイ方式(配置)で設計される半導体
集積回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device designed using a gate array method (arrangement).
【0002】0002
【従来の技術】従来のこの種のゲートアレイ方式による
半導体集積回路装置では、図3に示すように、内部論理
回路部31と外部入出力回路部32とが領域的に明確に
分かれており、内部論理回路部31は、基本セル34が
、一次元方向及び二次元方向に複数個配置されている。
その為、クロックドライバを構成する際は、基本セル3
4を複数個使用して構成していた。2. Description of the Related Art In a conventional semiconductor integrated circuit device using this type of gate array system, as shown in FIG. 3, an internal logic circuit section 31 and an external input/output circuit section 32 are clearly separated in area. In the internal logic circuit section 31, a plurality of basic cells 34 are arranged in a one-dimensional direction and a two-dimensional direction. Therefore, when configuring the clock driver, the basic cell 3
It was constructed using multiple 4.
【0003】0003
【発明が解決しようとする課題】前述した従来のゲート
アレイ方式の半導体集積回路装置では、自動配置配線を
行なった場合、中央付近に配置配線が集中し、内部論理
回路部31の四隅に配置配線の密度の低い領域が発生し
、全体に対する基本セル34の使用率が高くならないと
いう欠点があった。[Problems to be Solved by the Invention] In the conventional gate array type semiconductor integrated circuit device described above, when automatic placement and wiring is performed, the placement and wiring is concentrated near the center, and the placement and wiring is concentrated in the four corners of the internal logic circuit section 31. This has the disadvantage that areas with low density occur, and the usage rate of the basic cells 34 relative to the whole cannot be increased.
【0004】本発明の目的は、前記欠点を解決し、基本
セルの使用率を高めた半導体集積回路装置を提供するこ
とにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device that solves the above-mentioned drawbacks and increases the usage rate of basic cells.
【0005】[0005]
【課題を解決するための手段】本発明の構成は、半導体
チップ上に内部論理回路部と外部入出力回路部との二つ
の領域が明確に分かれているゲートアレイ配置された半
導体集積回路装置において、前記内部論理回路部の四隅
に、クロックドライバ専用回路部を有することを特徴と
する。[Means for Solving the Problems] The structure of the present invention is applied to a semiconductor integrated circuit device in which a gate array is arranged on a semiconductor chip, in which two areas, an internal logic circuit section and an external input/output circuit section, are clearly separated. , characterized in that the internal logic circuit section has clock driver dedicated circuit sections at four corners.
【0006】本発明は、前述した構成をすることにより
、従来内部論理回路で構成していたクロックドライバを
クロックドライバ専用領域に配置することができる。[0006] According to the present invention, by having the above-described configuration, the clock driver, which was conventionally constituted by an internal logic circuit, can be placed in the clock driver-dedicated area.
【0007】[0007]
【実施例】図1は本発明の一実施例の半導体集積回路装
置のチップを示す平面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a plan view showing a chip of a semiconductor integrated circuit device according to an embodiment of the present invention.
【0008】図1において、本実施例は、内部論理回路
部11と外部入出力回路部12とクロックドライバ専用
回路部13との領域で構成されている。ここで、クロッ
クドライバ専用回路部13は、内部論理回路部11の四
隅に配置される。In FIG. 1, this embodiment is comprised of an internal logic circuit section 11, an external input/output circuit section 12, and a clock driver dedicated circuit section 13. Here, the clock driver dedicated circuit section 13 is arranged at the four corners of the internal logic circuit section 11.
【0009】図2は本発明の他の実施例のチップを示す
平面図である。FIG. 2 is a plan view showing a chip according to another embodiment of the present invention.
【0010】図2において本実施例は、四隅に配置され
たクロックドライバ専用回路部の領域が、二つの機能の
違った回路部21,22から構成される。また、他のク
ロックドライバ専用回路部23,24,25も、機能の
違った構成を有する。In FIG. 2, in this embodiment, the area of the clock driver dedicated circuit section arranged at the four corners is composed of two circuit sections 21 and 22 having different functions. Further, the other clock driver dedicated circuit units 23, 24, and 25 also have configurations with different functions.
【0011】[0011]
【発明の効果】以上説明したように、本発明は、内部論
理回路部の四隅にクロックドライバ専用領域を有するこ
とによって、全体の基本セルの使用率を高くすることが
でき、また特にクロックドライバ専用領域を複数個有す
る為、回路の機能に応じたクロックドライバ専用領域を
選択することができ、クロックドライバを内部論理回路
部で構成する場合も、内部論理回路の四隅で構成した場
合も、回路に及ぼす影響はなく、以上のことから従来内
部論理回路部で構成していたクロックドライバを回路動
作に影響なく、配置配線の密度の低い内部論理回路部の
四隅に移動することが可能となる等の効果がある。As explained above, the present invention can increase the usage rate of the entire basic cell by having areas dedicated to clock drivers at the four corners of the internal logic circuit section, and can also increase the usage rate of the entire basic cell. Since it has multiple areas, it is possible to select a dedicated area for the clock driver according to the function of the circuit.Whether the clock driver is configured in the internal logic circuit section or in the four corners of the internal logic circuit, From the above, it is now possible to move the clock driver, which was conventionally configured in the internal logic circuit section, to the four corners of the internal logic circuit section where the wiring density is low, without affecting circuit operation. effective.
【図1】本発明の一実施例の半導体集積回路装置のチッ
プを示す平面図である。FIG. 1 is a plan view showing a chip of a semiconductor integrated circuit device according to an embodiment of the present invention.
【図2】本発明の他の実施例のチップを示す平面図であ
る。FIG. 2 is a plan view showing a chip according to another embodiment of the present invention.
【図3】従来の半導体集積回路装置のチップを示す平面
図である。FIG. 3 is a plan view showing a chip of a conventional semiconductor integrated circuit device.
11,13 内部論理回路部
12,32 外部入出力回路部
13,21〜25,33 クロックドライバ専用
回路部
34 基本セル11, 13 Internal logic circuit section 12, 32 External input/output circuit section 13, 21 to 25, 33 Clock driver dedicated circuit section 34 Basic cell
Claims (2)
部入出力回路部との二つの領域が明確に分かれているゲ
ートアレイ配置された半導体集積回路装置において、前
記内部論理回路部の四隅に、クロックドライバ専用回路
部を有することを特徴とする半導体集積回路装置。1. In a semiconductor integrated circuit device in which a gate array is arranged on a semiconductor chip, in which two areas, an internal logic circuit section and an external input/output circuit section, are clearly separated, at the four corners of the internal logic circuit section, A semiconductor integrated circuit device comprising a clock driver dedicated circuit section.
異なる機能を有する請求項1記載の半導体集積回路装置
。2. The semiconductor integrated circuit device according to claim 1, wherein the clock driver dedicated circuit sections have different functions.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10298391A JPH04334055A (en) | 1991-05-09 | 1991-05-09 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10298391A JPH04334055A (en) | 1991-05-09 | 1991-05-09 | Semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04334055A true JPH04334055A (en) | 1992-11-20 |
Family
ID=14341959
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10298391A Pending JPH04334055A (en) | 1991-05-09 | 1991-05-09 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04334055A (en) |
-
1991
- 1991-05-09 JP JP10298391A patent/JPH04334055A/en active Pending
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