JPH02230672A - 電極上への導電性粒子の配置方法 - Google Patents
電極上への導電性粒子の配置方法Info
- Publication number
- JPH02230672A JPH02230672A JP1050904A JP5090489A JPH02230672A JP H02230672 A JPH02230672 A JP H02230672A JP 1050904 A JP1050904 A JP 1050904A JP 5090489 A JP5090489 A JP 5090489A JP H02230672 A JPH02230672 A JP H02230672A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- conductive particles
- layer
- resin
- resin layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- 241000270708 Testudinidae Species 0.000 description 1
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- 150000001298 alcohols Chemical class 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
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- 150000002576 ketones Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 238000000016 photochemical curing Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/245—Reinforcing conductive patterns made by printing techniques or by other techniques for applying conductive pastes, inks or powders; Reinforcing other conductive patterns by such techniques
- H05K3/247—Finish coating of conductors by using conductive pastes, inks or powders
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
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Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、たとえば半導体集81回路基板、プリント基
板、ガラス基板、フレキシブル基板、あるいはセラミッ
ク基板などの回路基板の電極を相互に圧接によって電気
的に接続するために好適に実施される電極上への導電性
粒子の配置方法に関する. 従来の技術 従来、回路基板同士の電極を電気的に接続する方法とし
ては、通常、半田付けが行われている。
板、ガラス基板、フレキシブル基板、あるいはセラミッ
ク基板などの回路基板の電極を相互に圧接によって電気
的に接続するために好適に実施される電極上への導電性
粒子の配置方法に関する. 従来の技術 従来、回路基板同士の電極を電気的に接続する方法とし
ては、通常、半田付けが行われている。
半田付けによる方法では、一方の回路基板の電極上にめ
っき法や印刷法などによって半田層を形成し、この半田
層を200〜250℃程度の高温に加熱し、溶融して他
方の回路基板の電極に接続する。したがって電極材料と
して゛、予めAu.Cu、Niなどの親半田金属を用い
る必要がある。
っき法や印刷法などによって半田層を形成し、この半田
層を200〜250℃程度の高温に加熱し、溶融して他
方の回路基板の電極に接続する。したがって電極材料と
して゛、予めAu.Cu、Niなどの親半田金属を用い
る必要がある。
このような半田付けという高温処理による回路基板など
への熱的な弊害や、親半田金属を用いることによるコス
ト高を回避するために、最近では、接着剤中に導電性粒
子を分散させて成る異方性導電シートを用いる傾向にあ
る。異方性導電シートは、このシートに加えられる圧力
方向に対してのみ・導電性を示し、それ以外の方向に対
しては非導電性であるという異方性を利用し、接続した
い電極や端子などの間にこの異方性導電シートを介在し
、電極間に介在したシーl・部分をシー1・厚み方向に
わたって加圧および加熱して両電極間の電気的接続を行
う。特に、配線材料としてITO(Indium Ti
n Oxide)を使用する液晶表示板の端子の接続に
は、その接続の容易性および熱的条件の点から異方性導
電シー1〜が多く用いられている.発明が解決しようと
する課題 上記した異方性導電シートは、樹脂中に導電性粒子を分
散させた構成である.したがって隣接端子間のピッチ幅
が微細となった場合、シート中に存在する導電性粒子に
起因して電気的短絡が生じ、微小ピッチ幅での接続が困
難であるという問題点がある. 本発明の目的は、上記問題点を解決して、接続すべき電
極上にのみ導電性の粒子を配置することができ、したが
って電極の微細化に対応することができるとともに、接
続の信頼性を向上することができる電極上への導電性粒
子の配置方法をti供することである. 課題を解決するための手段 本発明は、電極が形成された回路基板」二に、硬化が可
能であるか、または、硬化およびその後の再軟化が可能
であるかのいずれか一方の特性に選ばれる樹脂材料を塗
布して樹脂層を形成し、前記電極上の樹脂材料のみが軟
化した状態で、この軟化した樹脂層の屑厚より大径の導
電性の粒子を前記回路基板」二に散布して、電極上の樹
脂層に付着させ、電極上以外に付薯した前記粒子は除去
するようにしたことを特徴とする電極上への導電性粒子
の配置方法である. 作 用 本発明に従えば、電極を含む回路基板上には樹脂材料が
塗布されて樹脂層が形成される.この樹脂材料は、硬化
が可能であるか、または、硬化およびその後の再軟化が
可能であるかのいずれが−方の特性に選ばれる.この回
路基板上の樹脂層を、電極上の樹脂材料のみが軟化した
状態とし、この軟化した樹脂層にその層厚より大径の導
電性粒子を散布して付着させるとともに、電極上以外に
付着した粒子は除去する.IK極上の樹脂材料のみが軟
化した状態にあるので、散布された導電性粒子は容易に
電極上の樹脂層に付着し、1!極上以外に付着した導電
性粒子は除去されて、導電性粒子は選択的に電極上へ配
置される. したがってこの電極上へ配置された導電性粒子を樹脂層
に埋設して保持し、突起した電極を形成することができ
る.これによって回路基板上に突起した電極を@栖に形
成することができ、t極の微細化に対応して高い信頼性
で他の回路基板に接続することができる回路基板が構成
される。
への熱的な弊害や、親半田金属を用いることによるコス
ト高を回避するために、最近では、接着剤中に導電性粒
子を分散させて成る異方性導電シートを用いる傾向にあ
る。異方性導電シートは、このシートに加えられる圧力
方向に対してのみ・導電性を示し、それ以外の方向に対
しては非導電性であるという異方性を利用し、接続した
い電極や端子などの間にこの異方性導電シートを介在し
、電極間に介在したシーl・部分をシー1・厚み方向に
わたって加圧および加熱して両電極間の電気的接続を行
う。特に、配線材料としてITO(Indium Ti
n Oxide)を使用する液晶表示板の端子の接続に
は、その接続の容易性および熱的条件の点から異方性導
電シー1〜が多く用いられている.発明が解決しようと
する課題 上記した異方性導電シートは、樹脂中に導電性粒子を分
散させた構成である.したがって隣接端子間のピッチ幅
が微細となった場合、シート中に存在する導電性粒子に
起因して電気的短絡が生じ、微小ピッチ幅での接続が困
難であるという問題点がある. 本発明の目的は、上記問題点を解決して、接続すべき電
極上にのみ導電性の粒子を配置することができ、したが
って電極の微細化に対応することができるとともに、接
続の信頼性を向上することができる電極上への導電性粒
子の配置方法をti供することである. 課題を解決するための手段 本発明は、電極が形成された回路基板」二に、硬化が可
能であるか、または、硬化およびその後の再軟化が可能
であるかのいずれか一方の特性に選ばれる樹脂材料を塗
布して樹脂層を形成し、前記電極上の樹脂材料のみが軟
化した状態で、この軟化した樹脂層の屑厚より大径の導
電性の粒子を前記回路基板」二に散布して、電極上の樹
脂層に付着させ、電極上以外に付薯した前記粒子は除去
するようにしたことを特徴とする電極上への導電性粒子
の配置方法である. 作 用 本発明に従えば、電極を含む回路基板上には樹脂材料が
塗布されて樹脂層が形成される.この樹脂材料は、硬化
が可能であるか、または、硬化およびその後の再軟化が
可能であるかのいずれが−方の特性に選ばれる.この回
路基板上の樹脂層を、電極上の樹脂材料のみが軟化した
状態とし、この軟化した樹脂層にその層厚より大径の導
電性粒子を散布して付着させるとともに、電極上以外に
付着した粒子は除去する.IK極上の樹脂材料のみが軟
化した状態にあるので、散布された導電性粒子は容易に
電極上の樹脂層に付着し、1!極上以外に付着した導電
性粒子は除去されて、導電性粒子は選択的に電極上へ配
置される. したがってこの電極上へ配置された導電性粒子を樹脂層
に埋設して保持し、突起した電極を形成することができ
る.これによって回路基板上に突起した電極を@栖に形
成することができ、t極の微細化に対応して高い信頼性
で他の回路基板に接続することができる回路基板が構成
される。
また、両回路基板の少なくとも一方の回路基板に前記突
起した電極を形成して圧接する場合に、両回路基板間に
比較的低温度で硬化する接着剤を充填してこの接着剤を
硬化させれば、前記突起した電極から成る電気的な接続
部分が樹脂によって封止され、接続の信頼性がさらに向
上する.実施例 第1図は、本発明の一実施例である半導体装置6の横成
を示す断面図である.半導体装置6は、基板1と、この
基板1上に予め形成される電極2と、接着M M 8
aと、導電性粒子5とを含む.半導体装置6の電極2と
しては、通常、AIにStを1%程度添加したAI−
S iが使用されている.AI−Stは、その表面にご
く薄いアルミナなどの絶縁性の酸化膜を形成し、接続時
の抵抗が高くなり易い.この接続抵抗を低減するために
、AI・Stの電極2上にCr,Ti,W.Cu,Ni
、Au.Ag,PtおよびP dなどのうちのいずれか
の金属、あるいはこれら金属の合金を材料として、1層
もしくは2層以上の金属層を被覆するようにしてもよい
. 被覆の方法としては5上記金属を半導体装置6」二にス
パッタリング法あるいはエレクトロンビーム法などによ
って蒸着し、その後フォトリソグラフィ法によってパタ
ーン形成して、電fi!2上に選択的に金属層を被覆す
る.あるいは、AI−Siから成る電極2上には、Ni
は直接無電解めっきできないので、まずP dを電極2
上に選゛択的に無電解めっきし、その後、Pdに対して
N1を無電解めっきによって置換し、電fi2上にNi
の金属層を被覆することもできる. 基板1上の電極2が形成されていない領域には表面保護
層3が形成されている.この表面保護層3は、たとえば
SiN,Sin,,あるいはポリイミドなどから成る. 半導体装1j6のさらに第1図上層′には、接着剤M
8 aが形成されている.この接着剤7118 aは、
後述する方法によって、導電性粒子5の一端が電極2の
表面に接触し、他端が接着剤M8aから突出した状態で
硬化される。接着剤屑8は、たとえばアクリル系制Lポ
リエステル系樹脂、ウレタン系樹脂、エボキシ系樹脂、
あるいはシリコーン系樹脂などの各種合成樹脂を使用す
ることができる. また、導電性粒子5としては、Au,Ag、Pt.Cu
.Ni,C、I n.Sn.PbおよびPdなどの金属
あるいはこれらの2種類以上の合金を使用することがで
きる.また第1図に示したように、高分子材料か、らな
る弾性粒子5bの表面に導電性材料からなる被覆屑5a
を形成した導電性粒子5を用いてもよい.この場合、弾
性粒子5bとしてはポリイミド系樹脂、エボキシ系樹脂
、アクリル系樹脂などの合成樹脂、およびシリコーンゴ
ム、ウレタンゴムなどの合成ゴムが使用できる. また被覆層5aの導電性材料としては、A I1、Ag
,Pt.Cu.Ni= C.In.Sn,PbおよびP
dなどの金属、あるいはこれらの合金を1層もしくは2
層以上として使用することができる.2層以上で被覆層
5aを形成する場合には、弾性粒子5bへの密着性に優
れるたとえばNiなとの金属層を先に形成し、さらにそ
のような金属の酸化防止のために、Auなとの金属層を
被覆することが好ましい.被覆の方法としては、スパッ
タリング法、エレク)〜ロンビーム法などに1よる蒸着
法、あるいは無電解めっきなどの方法を用いることがで
きる. 第2図は、第1図に示した半導体装置6を製造する工程
を説明する断面図である.第2図(】)に示されるよう
に、予め電極2および表面保護層3が形成されている基
板1において、この電極2および表面保護層3の表面に
、たとえばスビンコートあるいはロールコートなどの方
法によって、たとえば光硬化性樹脂を全面に塗布し、樹
脂層8を形成する. 樹脂層8とI−では、たどえばアクリル系やポリエステ
ル系の熱可塑性樹脂を基材としてそれに光硬化剤を混入
するか、または基材に光反応性の基を付加したもの、あ
るいは基材として光硬化性樹脂を用い、それに熱可塑性
樹脂を混入したものなどを用いることができる。
起した電極を形成して圧接する場合に、両回路基板間に
比較的低温度で硬化する接着剤を充填してこの接着剤を
硬化させれば、前記突起した電極から成る電気的な接続
部分が樹脂によって封止され、接続の信頼性がさらに向
上する.実施例 第1図は、本発明の一実施例である半導体装置6の横成
を示す断面図である.半導体装置6は、基板1と、この
基板1上に予め形成される電極2と、接着M M 8
aと、導電性粒子5とを含む.半導体装置6の電極2と
しては、通常、AIにStを1%程度添加したAI−
S iが使用されている.AI−Stは、その表面にご
く薄いアルミナなどの絶縁性の酸化膜を形成し、接続時
の抵抗が高くなり易い.この接続抵抗を低減するために
、AI・Stの電極2上にCr,Ti,W.Cu,Ni
、Au.Ag,PtおよびP dなどのうちのいずれか
の金属、あるいはこれら金属の合金を材料として、1層
もしくは2層以上の金属層を被覆するようにしてもよい
. 被覆の方法としては5上記金属を半導体装置6」二にス
パッタリング法あるいはエレクトロンビーム法などによ
って蒸着し、その後フォトリソグラフィ法によってパタ
ーン形成して、電fi!2上に選択的に金属層を被覆す
る.あるいは、AI−Siから成る電極2上には、Ni
は直接無電解めっきできないので、まずP dを電極2
上に選゛択的に無電解めっきし、その後、Pdに対して
N1を無電解めっきによって置換し、電fi2上にNi
の金属層を被覆することもできる. 基板1上の電極2が形成されていない領域には表面保護
層3が形成されている.この表面保護層3は、たとえば
SiN,Sin,,あるいはポリイミドなどから成る. 半導体装1j6のさらに第1図上層′には、接着剤M
8 aが形成されている.この接着剤7118 aは、
後述する方法によって、導電性粒子5の一端が電極2の
表面に接触し、他端が接着剤M8aから突出した状態で
硬化される。接着剤屑8は、たとえばアクリル系制Lポ
リエステル系樹脂、ウレタン系樹脂、エボキシ系樹脂、
あるいはシリコーン系樹脂などの各種合成樹脂を使用す
ることができる. また、導電性粒子5としては、Au,Ag、Pt.Cu
.Ni,C、I n.Sn.PbおよびPdなどの金属
あるいはこれらの2種類以上の合金を使用することがで
きる.また第1図に示したように、高分子材料か、らな
る弾性粒子5bの表面に導電性材料からなる被覆屑5a
を形成した導電性粒子5を用いてもよい.この場合、弾
性粒子5bとしてはポリイミド系樹脂、エボキシ系樹脂
、アクリル系樹脂などの合成樹脂、およびシリコーンゴ
ム、ウレタンゴムなどの合成ゴムが使用できる. また被覆層5aの導電性材料としては、A I1、Ag
,Pt.Cu.Ni= C.In.Sn,PbおよびP
dなどの金属、あるいはこれらの合金を1層もしくは2
層以上として使用することができる.2層以上で被覆層
5aを形成する場合には、弾性粒子5bへの密着性に優
れるたとえばNiなとの金属層を先に形成し、さらにそ
のような金属の酸化防止のために、Auなとの金属層を
被覆することが好ましい.被覆の方法としては、スパッ
タリング法、エレク)〜ロンビーム法などに1よる蒸着
法、あるいは無電解めっきなどの方法を用いることがで
きる. 第2図は、第1図に示した半導体装置6を製造する工程
を説明する断面図である.第2図(】)に示されるよう
に、予め電極2および表面保護層3が形成されている基
板1において、この電極2および表面保護層3の表面に
、たとえばスビンコートあるいはロールコートなどの方
法によって、たとえば光硬化性樹脂を全面に塗布し、樹
脂層8を形成する. 樹脂層8とI−では、たどえばアクリル系やポリエステ
ル系の熱可塑性樹脂を基材としてそれに光硬化剤を混入
するか、または基材に光反応性の基を付加したもの、あ
るいは基材として光硬化性樹脂を用い、それに熱可塑性
樹脂を混入したものなどを用いることができる。
樹脂層8が形成された基板1に対して、第2図(2)に
示されるように、マスク9を介して紫外線20を照射ず
る.マスク9には、紫外線20を遮断する遮断部9aと
紫外線20が通過可能な透孔9bとが形成されている.
基板1の電極2が形成された領域とマスク9の透孔9b
とが位置合わせされ、紫外線20が照射される6これに
よって電極2が形成された領域の樹脂層8aのみが硬化
され、紫外線20の照射が行われなかった樹脂屑8bは
未硬化の状態に残される。
示されるように、マスク9を介して紫外線20を照射ず
る.マスク9には、紫外線20を遮断する遮断部9aと
紫外線20が通過可能な透孔9bとが形成されている.
基板1の電極2が形成された領域とマスク9の透孔9b
とが位置合わせされ、紫外線20が照射される6これに
よって電極2が形成された領域の樹脂層8aのみが硬化
され、紫外線20の照射が行われなかった樹脂屑8bは
未硬化の状態に残される。
次に、このように選択的に紫外線20が照射された樹脂
層8に対して溶剤を用いて現像を行う。
層8に対して溶剤を用いて現像を行う。
溶剤としては、アセトンやメチルエチルケトンなどのケ
トン類およびアルコール類が使用される.一般に、硬化
した樹脂は溶剤に対して溶け難くなるので、現像は容易
である。
トン類およびアルコール類が使用される.一般に、硬化
した樹脂は溶剤に対して溶け難くなるので、現像は容易
である。
すなわち、紫外線20が照射されて硬化した接着剤層8
aにおいては、紫外線20に基づく架橋反応などが生じ
ており、溶剤に対しては不溶性または難溶性である.一
方、紫外線20が照射されずに未硬化の接着剤718
1)においては、前記反応は生じておらず、溶剤によっ
て容易に溶出し除去される9これによって電極2上にの
み接着剤層8aを形成することができる。
aにおいては、紫外線20に基づく架橋反応などが生じ
ており、溶剤に対しては不溶性または難溶性である.一
方、紫外線20が照射されずに未硬化の接着剤718
1)においては、前記反応は生じておらず、溶剤によっ
て容易に溶出し除去される9これによって電極2上にの
み接着剤層8aを形成することができる。
次に、基板1を50〜200℃程度にまで加熱し、硬化
した接着剤層8aを熱によって再軟化させる,この状態
で、第2図(3》に示されるように、前記導電性粒子5
を散布し、電極2」二の樹脂屑8aに付着させる.この
とき熱軟化した樹脂層8aは粘着性を有しており、これ
によって導電性粒子5を吸着する9一方、接薯剤屑8a
が形成されていない表面保護層3上などでは、導電性粒
子5が単に付着した状態である.したがって電極2以外
の他の領域に静電気力などによって付着した不要な導電
性粒子5は、エアブローによって、またははけなどを使
用して容易に除去することができる。
した接着剤層8aを熱によって再軟化させる,この状態
で、第2図(3》に示されるように、前記導電性粒子5
を散布し、電極2」二の樹脂屑8aに付着させる.この
とき熱軟化した樹脂層8aは粘着性を有しており、これ
によって導電性粒子5を吸着する9一方、接薯剤屑8a
が形成されていない表面保護層3上などでは、導電性粒
子5が単に付着した状態である.したがって電極2以外
の他の領域に静電気力などによって付着した不要な導電
性粒子5は、エアブローによって、またははけなどを使
用して容易に除去することができる。
上述のようにして電極2上の樹脂711 8 aに配置
された導電性粒子5は、導電性粒子5の一端が電掻2表
面に接触し、その他端は樹脂層8aから突出するように
樹脂M8aに埋設される。あるいは、導電性粒子5が電
極上に配置された半導体装置6を、他の回路基板に圧接
によって接続する際に、両回路基板に加えられた圧力に
よって導電性粒子5が樹脂M8aを貫通して、その一端
が電極2に接触するようにしてもよい.また導電性粒子
5を介して両回路基板の相互に対応する電極が接続され
るように加圧する際に、予め両回路基板間に接着剤を充
填して硬化させるようにしてもよい.これによって電気
的な接続部分が樹脂によって封止され、接続の信頼性が
向上する. 第3図は、本発明の半導体装置6が実装された液晶表示
装置10の断面図である.また第4図は第3図の切断面
線■一■から見た一部断面図であり、第5図は第4図の
細部を詳細に示す拡大断面図である. 第3図を参照して、表面に電極13および対向電極】6
がそれぞれ形成された一対の液晶表示板11.12は、
シール樹脂15′を介して貼りhわされており、その間
に液晶17が封入されている。
された導電性粒子5は、導電性粒子5の一端が電掻2表
面に接触し、その他端は樹脂層8aから突出するように
樹脂M8aに埋設される。あるいは、導電性粒子5が電
極上に配置された半導体装置6を、他の回路基板に圧接
によって接続する際に、両回路基板に加えられた圧力に
よって導電性粒子5が樹脂M8aを貫通して、その一端
が電極2に接触するようにしてもよい.また導電性粒子
5を介して両回路基板の相互に対応する電極が接続され
るように加圧する際に、予め両回路基板間に接着剤を充
填して硬化させるようにしてもよい.これによって電気
的な接続部分が樹脂によって封止され、接続の信頼性が
向上する. 第3図は、本発明の半導体装置6が実装された液晶表示
装置10の断面図である.また第4図は第3図の切断面
線■一■から見た一部断面図であり、第5図は第4図の
細部を詳細に示す拡大断面図である. 第3図を参照して、表面に電極13および対向電極】6
がそれぞれ形成された一対の液晶表示板11.12は、
シール樹脂15′を介して貼りhわされており、その間
に液晶17が封入されている。
液晶表示装置10において、電極13は液晶表示板11
上を図面右方に延び、液晶表示装210の表示駆動を行
うために実装された半導体装置6と導電性粒子5を介し
て接続されている.また、半導体装置6と液晶表示板1
1との接続部分は接着剤14によって封止されている. 半導体装置6は、シリコンあるいはガリウムヒ素などの
基板上に拡散層(図示せず)が形成され、これによって
多数のトランジスタやダイオードなどが構成されて液晶
表示装置10の表示駆動を行う機能を有する。半導体装
置6は、前述した本発明に従って、電極2上に導電性粒
子5が樹脂層8aによって埋設して保持されている.一
方、液晶表示板11の電極13は、たとえばソーダガラ
スなどの表面上にI T O ( Indium Ti
n Oxide) .あるいは接触抵抗を低減するため
にNiでめっきしたITOなどが形成されて成り、通常
厚みは50〜200nm程度である。
上を図面右方に延び、液晶表示装210の表示駆動を行
うために実装された半導体装置6と導電性粒子5を介し
て接続されている.また、半導体装置6と液晶表示板1
1との接続部分は接着剤14によって封止されている. 半導体装置6は、シリコンあるいはガリウムヒ素などの
基板上に拡散層(図示せず)が形成され、これによって
多数のトランジスタやダイオードなどが構成されて液晶
表示装置10の表示駆動を行う機能を有する。半導体装
置6は、前述した本発明に従って、電極2上に導電性粒
子5が樹脂層8aによって埋設して保持されている.一
方、液晶表示板11の電極13は、たとえばソーダガラ
スなどの表面上にI T O ( Indium Ti
n Oxide) .あるいは接触抵抗を低減するため
にNiでめっきしたITOなどが形成されて成り、通常
厚みは50〜200nm程度である。
第6図に示されるように、半導体装置6の導電性粒子5
から成る突起電極が形成された表面ど、液晶表示板11
の電極13が形成された表面とは対向され、導電性粒子
5と電極13とが位置合わせされる.位置合わぜされた
基板1,11間には、接着剤14が充填され、半導体装
W6は液晶表示板11に対して導電性粒子5および接着
剤14を介して矢符19方向に、電極2,13間が第5
図示の所定の間隔l1となるまで加圧される。この加圧
状態において接着剤14を硬化させることによって、半
導体装W.6が液晶表示板11に実装される。
から成る突起電極が形成された表面ど、液晶表示板11
の電極13が形成された表面とは対向され、導電性粒子
5と電極13とが位置合わせされる.位置合わぜされた
基板1,11間には、接着剤14が充填され、半導体装
W6は液晶表示板11に対して導電性粒子5および接着
剤14を介して矢符19方向に、電極2,13間が第5
図示の所定の間隔l1となるまで加圧される。この加圧
状態において接着剤14を硬化させることによって、半
導体装W.6が液晶表示板11に実装される。
接着剤14としては,たとえば反応硬化性、嫌気硬化性
、熱硬化性、光硬化性などの各種接着剤を使用すること
ができる.特に本実施例においては,液晶表示板11が
透光性材料であるガラスから成るので、接着剤14には
、高速接合可能な光硬化性接着剤を使用することが有効
である.以上説明したように、本発明に従って配置され
た導電性粒子5を有する半導体装置6は、第2図の液晶
表示装W.10のように、他の回路基板に圧接した状態
で、予め両回路基板間に充填された接着剤を硬化して回
路基板相互を接続し、実装することができる. また上記実施例においては、半導体装置6上に導電性杓
子5を配置する場合について説明したけれども、半導体
装置に限定する必要はなく、他の回路基板上に導電性粒
子を配置して圧接する場今についても本発明は実施する
ことができる.発明の効果 以上説明したように本発明によれば、簡単な方法によっ
て回路基板の電極−]こに導電性粒子を配置することが
できる.これによって電極の微細化に対応して、この導
電性粒子によって突起した電極が形成された回路基板と
他の回路基板とを圧接によって接続する場合の信頼性が
向J二する.したがって生産性が向上し、コスl・を低
減することができる.
、熱硬化性、光硬化性などの各種接着剤を使用すること
ができる.特に本実施例においては,液晶表示板11が
透光性材料であるガラスから成るので、接着剤14には
、高速接合可能な光硬化性接着剤を使用することが有効
である.以上説明したように、本発明に従って配置され
た導電性粒子5を有する半導体装置6は、第2図の液晶
表示装W.10のように、他の回路基板に圧接した状態
で、予め両回路基板間に充填された接着剤を硬化して回
路基板相互を接続し、実装することができる. また上記実施例においては、半導体装置6上に導電性杓
子5を配置する場合について説明したけれども、半導体
装置に限定する必要はなく、他の回路基板上に導電性粒
子を配置して圧接する場今についても本発明は実施する
ことができる.発明の効果 以上説明したように本発明によれば、簡単な方法によっ
て回路基板の電極−]こに導電性粒子を配置することが
できる.これによって電極の微細化に対応して、この導
電性粒子によって突起した電極が形成された回路基板と
他の回路基板とを圧接によって接続する場合の信頼性が
向J二する.したがって生産性が向上し、コスl・を低
減することができる.
第1図は本発明の一実施例の半導体装置6の断面図、第
2図は第1図示の半導体装置6の製造工程を説明する断
面図、第3図は半導体装W.6が実装された液晶表示装
置10の断面図、第4図は第3図の切断面線■−IVか
ら見た断面図、第5図は第4図の一部拡大断面図、第6
図は圧接によって第4図示の接続を得るための断面図で
ある。 1・・・基板、2,13.16・・・電極、5・・・導
電性粒子、6・・半導体装置、8・・・樹脂層、10・
・・液晶表示装置,19・加圧方向、20・・・紫外線
代理人 弁理士 西教 圭一郎 亀 図 第 図
2図は第1図示の半導体装置6の製造工程を説明する断
面図、第3図は半導体装W.6が実装された液晶表示装
置10の断面図、第4図は第3図の切断面線■−IVか
ら見た断面図、第5図は第4図の一部拡大断面図、第6
図は圧接によって第4図示の接続を得るための断面図で
ある。 1・・・基板、2,13.16・・・電極、5・・・導
電性粒子、6・・半導体装置、8・・・樹脂層、10・
・・液晶表示装置,19・加圧方向、20・・・紫外線
代理人 弁理士 西教 圭一郎 亀 図 第 図
Claims (1)
- 【特許請求の範囲】 電極が形成された回路基板上に、硬化が可能であるか、
または、硬化およびその後の再軟化が可能であるかのい
ずれか一方の特性に選ばれる樹脂材料を塗布して樹脂層
を形成し、 前記電極上の樹脂材料のみが軟化した状態で、この軟化
した樹脂層の層厚より大径の導電性の粒子を前記回路基
板上に散布して、電極上の樹脂層に付着させ、電極上以
外に付着した前記粒子は除去するようにしたことを特徴
とする電極上への導電性粒子の配置方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5090489A JPH0740496B2 (ja) | 1989-03-01 | 1989-03-01 | 電極上への導電性粒子の配置方法 |
US07/485,745 US5034245A (en) | 1989-03-01 | 1990-02-27 | Method of producing connection electrodes |
EP19900302214 EP0385787B1 (en) | 1989-03-01 | 1990-03-01 | Method of producing connection electrodes |
DE69020009T DE69020009T2 (de) | 1989-03-01 | 1990-03-01 | Verfahren zum Herstellen von Verbindungselektroden. |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5090489A JPH0740496B2 (ja) | 1989-03-01 | 1989-03-01 | 電極上への導電性粒子の配置方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02230672A true JPH02230672A (ja) | 1990-09-13 |
JPH0740496B2 JPH0740496B2 (ja) | 1995-05-01 |
Family
ID=12871746
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5090489A Expired - Fee Related JPH0740496B2 (ja) | 1989-03-01 | 1989-03-01 | 電極上への導電性粒子の配置方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5034245A (ja) |
EP (1) | EP0385787B1 (ja) |
JP (1) | JPH0740496B2 (ja) |
DE (1) | DE69020009T2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04290489A (ja) * | 1991-03-19 | 1992-10-15 | Shin Etsu Polymer Co Ltd | ヒートシールコネクターの製造方法 |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ATE138225T1 (de) * | 1989-08-17 | 1996-06-15 | Canon Kk | Prozess zur gegenseitigen konnektion von elektrodenanschlüssen |
JPH0540274A (ja) * | 1990-09-13 | 1993-02-19 | Canon Inc | 液晶装置 |
US5153023A (en) * | 1990-12-03 | 1992-10-06 | Xerox Corporation | Process for catalysis of electroless metal plating on plastic |
JPH0521519A (ja) * | 1991-07-16 | 1993-01-29 | Sharp Corp | 半導体装置 |
US5330790A (en) * | 1992-02-07 | 1994-07-19 | Calkins Noel C | Impact implantation of particulate material into polymer surfaces |
SG54297A1 (en) * | 1992-09-15 | 1998-11-16 | Texas Instruments Inc | Ball contact for flip-chip devices |
US5401913A (en) * | 1993-06-08 | 1995-03-28 | Minnesota Mining And Manufacturing Company | Electrical interconnections between adjacent circuit board layers of a multi-layer circuit board |
US6365500B1 (en) * | 1994-05-06 | 2002-04-02 | Industrial Technology Research Institute | Composite bump bonding |
US5393697A (en) * | 1994-05-06 | 1995-02-28 | Industrial Technology Research Institute | Composite bump structure and methods of fabrication |
TW277152B (ja) * | 1994-05-10 | 1996-06-01 | Hitachi Chemical Co Ltd | |
EP0827190A3 (en) * | 1994-06-24 | 1998-09-02 | Industrial Technology Research Institute | Bump structure and methods for forming this structure |
US5578527A (en) * | 1995-06-23 | 1996-11-26 | Industrial Technology Research Institute | Connection construction and method of manufacturing the same |
US6881611B1 (en) | 1996-07-12 | 2005-04-19 | Fujitsu Limited | Method and mold for manufacturing semiconductor device, semiconductor device and method for mounting the device |
EP1271640A3 (en) * | 1996-07-12 | 2003-07-16 | Fujitsu Limited | Mold for manufacturing semiconductor device |
JP3711873B2 (ja) * | 2001-02-19 | 2005-11-02 | ソニーケミカル株式会社 | バンプレスicチップの製造方法 |
JP3882624B2 (ja) * | 2002-01-29 | 2007-02-21 | 三菱電機株式会社 | 固定子コアとその製造方法とその製造装置 |
US20060286721A1 (en) * | 2005-06-16 | 2006-12-21 | Daoqiang Lu | Breakable interconnects and structures formed thereby |
KR100801073B1 (ko) * | 2005-10-06 | 2008-02-11 | 삼성전자주식회사 | 도전성 입자를 포함하는 범프를 구비하는 반도체 칩 및 이의 제조 방법 |
KR101309319B1 (ko) * | 2006-11-22 | 2013-09-13 | 삼성디스플레이 주식회사 | 액정표시장치 구동회로 및 그의 제조방법과 액정표시장치구동회로가 실장 된 액정표시장치 |
Citations (2)
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JPS6222383A (ja) * | 1985-07-22 | 1987-01-30 | 古河電気工業株式会社 | 電子回路部材の接続方法 |
JPS6258812U (ja) * | 1985-06-05 | 1987-04-11 |
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GB1095117A (en) * | 1963-12-26 | 1967-12-13 | Matsushita Electric Ind Co Ltd | Method of making printed circuit board |
US3951063A (en) * | 1973-11-30 | 1976-04-20 | Xerox Corporation | Process for preparing reversible cure waterless lithographic masters |
US4049844A (en) * | 1974-09-27 | 1977-09-20 | General Electric Company | Method for making a circuit board and article made thereby |
US4075049A (en) * | 1976-09-01 | 1978-02-21 | Minnesota Mining And Manufacturing Company | Method of preparing retroreflective sheeting |
US4327124A (en) * | 1978-07-28 | 1982-04-27 | Desmarais Jr Raymond C | Method for manufacturing printed circuits comprising printing conductive ink on dielectric surface |
US4401686A (en) * | 1982-02-08 | 1983-08-30 | Raymond Iannetta | Printed circuit and method of forming same |
US4469777A (en) * | 1983-12-01 | 1984-09-04 | E. I. Du Pont De Nemours And Company | Single exposure process for preparing printed circuits |
US4654752A (en) * | 1984-12-04 | 1987-03-31 | Kyle James C | Terminal assembly and method of making terminal assembly |
US4572764A (en) * | 1984-12-13 | 1986-02-25 | E. I. Du Pont De Nemours And Company | Preparation of photoformed plastic multistrate by via formation first |
JPS61161536A (ja) * | 1985-01-11 | 1986-07-22 | Seiko Epson Corp | 入力装置 |
JPS62176139A (ja) * | 1986-01-29 | 1987-08-01 | Fuji Xerox Co Ltd | 異方導電材料およびこれを用いた半導体装置の実装方法 |
US4807021A (en) * | 1986-03-10 | 1989-02-21 | Kabushiki Kaisha Toshiba | Semiconductor device having stacking structure |
JPS6355527A (ja) * | 1986-08-25 | 1988-03-10 | Nec Corp | 液晶表示装置の製造方法 |
DE3629712A1 (de) * | 1986-09-01 | 1988-03-03 | Kunz Gerhard K | Verfahren und schaltungsanordnung zur messung des beladungsgrades eines ionenaustauschfilters |
US4863757A (en) * | 1987-02-06 | 1989-09-05 | Key-Tech, Inc. | Printed circuit board |
-
1989
- 1989-03-01 JP JP5090489A patent/JPH0740496B2/ja not_active Expired - Fee Related
-
1990
- 1990-02-27 US US07/485,745 patent/US5034245A/en not_active Expired - Lifetime
- 1990-03-01 DE DE69020009T patent/DE69020009T2/de not_active Expired - Fee Related
- 1990-03-01 EP EP19900302214 patent/EP0385787B1/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6258812U (ja) * | 1985-06-05 | 1987-04-11 | ||
JPS6222383A (ja) * | 1985-07-22 | 1987-01-30 | 古河電気工業株式会社 | 電子回路部材の接続方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04290489A (ja) * | 1991-03-19 | 1992-10-15 | Shin Etsu Polymer Co Ltd | ヒートシールコネクターの製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JPH0740496B2 (ja) | 1995-05-01 |
EP0385787B1 (en) | 1995-06-14 |
EP0385787A3 (en) | 1990-10-31 |
US5034245A (en) | 1991-07-23 |
DE69020009D1 (de) | 1995-07-20 |
DE69020009T2 (de) | 1995-11-23 |
EP0385787A2 (en) | 1990-09-05 |
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