JPH0521519A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH0521519A
JPH0521519A JP3175113A JP17511391A JPH0521519A JP H0521519 A JPH0521519 A JP H0521519A JP 3175113 A JP3175113 A JP 3175113A JP 17511391 A JP17511391 A JP 17511391A JP H0521519 A JPH0521519 A JP H0521519A
Authority
JP
Japan
Prior art keywords
electrodes
chip
substrate
wiring
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3175113A
Other languages
English (en)
Inventor
Hisashi Shin
久司 新
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP3175113A priority Critical patent/JPH0521519A/ja
Priority to DE4223280A priority patent/DE4223280A1/de
Publication of JPH0521519A publication Critical patent/JPH0521519A/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3442Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171Chromium [Cr] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29399Coating material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01024Chromium [Cr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01058Cerium [Ce]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203Fillers and particles
    • H05K2201/0206Materials
    • H05K2201/0212Resin particles
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203Fillers and particles
    • H05K2201/0206Materials
    • H05K2201/0215Metallic fillers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0979Redundant conductors or connections, i.e. more than one current path between two points
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10636Leadless chip, e.g. chip capacitor or resistor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04Soldering or other types of metallurgic bonding
    • H05K2203/041Solder preforms in the shape of solder balls
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 【構成】 チップ電極7と基板電極11との間に応力吸
収球13が配置されている。応力吸収球13は高分子球
の表面にPb−Sn共晶ハンダをメッキしたものであ
る。Pb−Sn共晶ハンダと電極11、7とは拡散接合
している。 【効果】 熱応力が発生しても応力吸収球13の高分子
球が吸収するので、チップ電極7と基板電極11との接
続が不良となることはない。また、拡散接合で接続され
ているので電気抵抗を下げることができる。

Description

【発明の詳細な説明】
【0001】
【産業上の利用分野】この発明は半導体装置に関するも
のであり、特にフェイスダウンボンディングによって接
続されている部品を有する半導体装置に関するものであ
る。
【0002】
【従来の技術】従来、各種の配線基板上に半導体ベアチ
ップを搭載する技術としてIBM社によって開発された
ハンダバンプを用いたものがよく知られている(いわゆ
るC4接続法、P.A.Totta and R.P.
Sopher:IBM Journal of Res
earch and Development,Vo
l.13(1969)p.226)。この技術を図3を
用いて説明する。
【0003】半導体装置1は半導体チップ3と配線基板
5とを備えている。半導体チップ3には電子回路が形成
されており、この電子回路はチップ電極7と接続されて
いる。配線基板5には配線が形成されており、この配線
は基板電極11と接続されている。
【0004】チップ電極7と基板電極11とはハンダバ
ンプ9によって接続されている。すなわち、半導体チッ
プ3は配線基板5にフェイスダウンボンディングによっ
て接続されている。
【0005】しかし、この技術では温度変化が激しい条
件下で使用した場合、チップ電極7と基板電極11との
接続が不良になることが多い。すなわち、半導体チップ
3、配線基板5、ハンダバンプ9それぞれの線膨張係数
やヤング率の差に起因する熱応力のため、ハンダバンプ
9が破損したり、ハンダバンプ9と電極7、11との接
続が外れることがあるのである。
【0006】この欠点を解決する1つの技術として、半
導体チップ3と配線基板5との界面にハンダバンプ9と
ほぼ等しい線膨張係数をもつエポキシ樹脂を封入するこ
とが考えられる。このようにすれば熱応力はハンダバン
プ9とエポキシ樹脂とに作用するので、ハンダバンプ9
に作用する熱応力が小さくなる。しかし、このようなエ
ポキシ樹脂を開発する期間や材料コストの点で不利であ
る。
【0007】接続が不良になるという欠点を解消する他
の技術として、M.Masudaet al:Proc
eedings of 1989 Internati
onal Electronics Manufact
uring Technology Symposiu
m(1989)p.57がある。この技術を図4、図5
を用いて説明する。
【0008】この技術はチップ電極7と基板電極11と
の間に応力吸収球13を介在させている。応力吸収球1
3は図5に示すように、弾性を有する高分子球15の表
面にAuメッキ17を施したものである。熱応力が発生
しても高分子球15が吸収してくれるので、チップ電極
7と基板電極11との接続が不良になることはない。
【0009】
【発明が解決しようとする課題】しかし、図4に示す技
術は応力吸収球13と電極7、11とを接着剤で加圧接
触させているだけなので、接続部の電気抵抗値が0.1
〜1Ωと大きくなる欠点を有している。
【0010】この発明は係る従来の問題点を解決するた
めになされたものである。この発明の目的は、熱応力が
原因で電極部の接続が不良になることなく、かつ電極間
部の電気抵抗値を下げることができる半導体装置を提供
することである。
【0011】
【課題を解決するための手段】この発明に従った半導体
装置はフェイスダウンボンディングによって接続されて
いる部品を有する半導体装置であって、電子回路および
電子回路と接続した電極が形成された第1基板と、配線
が形成された第2基板と、電極と配線との間に位置し、
第1基板の線膨張係数と第2基板の線膨張係数との差が
原因で生じる応力を吸収する応力吸収部材と、を備えて
いる。応力吸収部材は表面に導電部材を有し、導電部材
は電極および配線と拡散接合している。
【0012】
【作用】この発明に従った半導体装置は、電極と配線と
の間に第1基板の線膨張係数と第2基板の線膨張係数と
の差が原因で生じる応力を吸収する応力吸収部材があ
る。このため電極と配線との接続部に熱応力が作用して
も応力吸収部材が熱応力を吸収するので、接続が不良に
なることはない。
【0013】また、応力吸収部材は表面に導電部材を有
し、導電部材は電極および配線と拡散接合しているの
で、第1,第2基板を接着剤で加圧接触させる場合に比
べ接続部の電気抵抗を下げることができる。
【0014】なお、ここでいう第2基板には電子回路を
形成した基板および配線回路を形成した基板が含まれ
る。また、配線には電極も含まれる。
【0015】
【実施例】図1はこの発明に従った半導体装置の一実施
例の断面図である。半導体装置1は半導体チップ3と配
線基板5とを備えている。半導体チップ3には電子回路
が形成されており、この電子回路はチップ電極7と接続
されている。配線基板5には配線が形成されており、こ
の配線は基板電極11と接続されている。
【0016】チップ電極7は最表層から順にAu、C
u、Niなどの親ハンダ金属層、Ti−W、Ti、Cr
のなどの拡散防止金属層、Al−Si、Al−Si−C
uなどの金属層からなる。金属層が半導体チップ3に形
成された配線層と接続している。拡散防止金属層は、親
ハンダ金属層中の原子が電子回路に拡散するのを防ぐ層
である。基板電極11はAu、Cu、Niなどの親ハン
ダ金属である。親ハンダ金属で配線が構成されている。
配線基板5には電子回路が形成されていないので拡散防
止金属層は形成されていない。
【0017】応力吸収球13は図2に示すようにスチレ
ンやジビニルベンゼンなどを重合させた高分子球15の
表面にPb−Sn共晶ハンダ19をメッキしたものであ
る。ハンダのメッキ方法としては、たとえば河内他:第
5回プリント回路学会学術講演会論文集に記載されてい
る。熱応力が発生しても高分子球15が吸収してくれる
のでチップ電極7と基板電極11との接続が不良になる
ことはない。
【0018】Pb−Sn共晶ハンダ19と電極7、11
の親ハンダ金属とが拡散接合している。したがって、チ
ップ電極7と基板電極11との接続部の電気抵抗を下げ
ることができる。ハンダの材料によって電極7、11の
親ハンダ金属を変える必要がある。表1はハイブリッド
マイクロエレクトロニクス用材料すなわちここでいう親
ハンダ金属とハンダの成分元素との関係を示すものであ
る。表の縦の金属と表の横の金属との組合わせのうち、
合金組成の記載がある組合わせを用いる。この表は、ハ
イブリッドマイクロエレクトロニクス協会(編集):
「ハイブリッドマイクロエレクトロニクスハンドブッ
ク」(1989・工業調査会)p.790から引用した
ものである。
【0019】
【表1】
【0020】応力吸収球13は基板電極11またはチッ
プ電極7上に配置する必要があるが、応力吸収球13を
半導体チップ3のうちチップ電極7上に選択的に配置す
る技術として、たとえば次の3つがある。回路基板5の
うち基板電極11上に選択的に配置する場合も同じであ
る。
【0021】 先に従来例で挙げたM.Masuda
et al:Proceedings of 198
9 International Electroni
csManufacturing Technolog
y Symposium(1989)p.57に示され
ているように熱硬化性樹脂や光硬化性樹脂の中に応力吸
収球13を混ぜたものを印刷法によって電極11上にだ
け供給する。この場合、熱硬化性樹脂あるいは光硬化性
樹脂は半導体チップ3と配線基板5との界面の封止の役
割もする。
【0022】 特開平01−227444,特開平0
2−23623に示されているように、予め半導体ウエ
ハの表面に塗布した応力吸収球13の直径よりも薄い膜
厚の光硬化性樹脂層にマスク露光を施し、照射部と非照
射部とへの光硬化性樹脂の粘着力の差を利用してチップ
電極7上にだけ応力吸収球13を供給する。この場合、
光硬化性樹脂は半導体チップ3と配線基板5との界面の
封止の役割もする。
【0023】 M.Kinoshita et a
l:Proceedings ofthe 6th I
nternational Microelectro
nics Symposium(1990)p.243
に示されているようにメタルマスクを用いてチップ電極
7上だけに応力吸収球13を供給する。
【0024】たとえば直径80μmの電極をもつ半導体
チップ3にの方法を採用して直径10μmの応力吸収
球13をチップ電極7上に配置した場合、約30〜40
個の応力吸収球13を配置することができた。この半導
体チップ3と配線基板5とをフリップチップボンダーに
より加圧・加熱接続すると図1に示す半導体装置1が得
られた。加圧・加熱条件は、200個のチップ電極7を
もつ13mm×6mmの半導体チップ3の場合、6Kg
f、200℃で適当である。
【0025】この実施例では配線基板に半導体チップを
フェイスダウンボンディングによって接続していれば、
半導体チップ同士をフェイスダウンボンディングによっ
て接続してもよい。
【0026】また、高分子球は任意の大きさにできるの
で、電極とほぼ同じ大きさの高分子球も用いることがで
きる。
【0027】さらに、高分子球はその重合度を変えるこ
とにより弾性係数を変えることができるので、ボンディ
ング時に必要な加圧力に応じて最適なる弾性係数をもつ
高分子球を採用すればよい。
【0028】この実施例では応力吸収球は球状している
が、熱応力を吸収でき、かつ拡散接合できるものであれ
ばいかなる形状でもよい。
【0029】この実施例では、電極7,11間に介在さ
せた材料を球形としたが、これ以外の形状でも機能が満
たされれば何ら問題はない。
【0030】この実施例では応力吸収球は高分子球とP
b−Sn共晶ハンダからなるが、電極と拡散接合し、か
つ熱応力を吸収できれば1つの材料でもよい。
【0031】
【発明の効果】以上説明したようにこの発明によれば、
フェイスダウンボンディングによって接続されている接
続部を有する半導体装置であっても、熱応力によって接
続部の接続が不良となったりすることはない。また、接
続部の電気抵抗を下げることができる。
【図面の簡単な説明】
【図1】この発明に従った半導体装置の一実施例の断面
図である。
【図2】この発明に従った半導体装置の一実施例に使わ
れる応力吸収球の断面図である。
【図3】従来の半導体装置の一例の断面図である。
【図4】従来の半導体装置の他の例の断面図である。
【図5】従来の半導体装置の他の例に使われる応力吸収
球の斜視図である。
【符号の説明】
1 半導体装置 3 半導体チップ 5 配線基板 7 チップ電極 11 基板電極 13 応力吸収球

Claims (1)

  1. 【特許請求の範囲】 【請求項1】 フェイスダウンボンディングによって接
    続されている部品を有する半導体装置であって、 電子回路および前記電子回路と接続した電極が形成され
    た第1基板と、 配線が形成された第2基板と、 前記電極と前記配線との間に位置し、前記第1基板の線
    膨張係数と前記第2基板の線膨張係数との差が原因で生
    じる応力を吸収する応力吸収部材と、を備え、前記応力
    吸収部材は表面に導電部材を有し、 前記導電部材は前記電極および前記配線と拡散接合して
    いる半導体装置。
JP3175113A 1991-07-16 1991-07-16 半導体装置 Withdrawn JPH0521519A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP3175113A JPH0521519A (ja) 1991-07-16 1991-07-16 半導体装置
DE4223280A DE4223280A1 (de) 1991-07-16 1992-07-15 Schaltkreistraeger-baueinheit und verfahren zu deren herstellung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3175113A JPH0521519A (ja) 1991-07-16 1991-07-16 半導体装置

Publications (1)

Publication Number Publication Date
JPH0521519A true JPH0521519A (ja) 1993-01-29

Family

ID=15990503

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3175113A Withdrawn JPH0521519A (ja) 1991-07-16 1991-07-16 半導体装置

Country Status (2)

Country Link
JP (1) JPH0521519A (ja)
DE (1) DE4223280A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100349896B1 (ko) * 1994-12-28 2002-12-26 삼성에스디아이 주식회사 집적회로칩의실장구조체및그실장방법
KR100376044B1 (ko) * 1999-05-13 2003-03-15 한오근 반도체 패키지의 솔더 및 이를 이용한 반도체 패키지
US8120188B2 (en) 2006-11-28 2012-02-21 Panasonic Corporation Electronic component mounting structure and method for manufacturing the same

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2722916A1 (fr) * 1994-02-22 1996-01-26 Nec Corp Element de connexion et procede de connexion mettant en oeuvre cet element
US5393697A (en) * 1994-05-06 1995-02-28 Industrial Technology Research Institute Composite bump structure and methods of fabrication
EP0827190A3 (en) * 1994-06-24 1998-09-02 Industrial Technology Research Institute Bump structure and methods for forming this structure
US5578527A (en) * 1995-06-23 1996-11-26 Industrial Technology Research Institute Connection construction and method of manufacturing the same
FR2736569B1 (fr) * 1995-07-13 1997-08-08 Thomson Csf Dispositif de connexion et procede de connexion
FI970822A (fi) * 1997-02-27 1998-08-28 Nokia Mobile Phones Ltd Menetelmä ja järjestely komponentin liittämiseksi
WO1999049536A1 (en) * 1998-03-24 1999-09-30 Raytheon Company Stacked electrical circuit having an improved interconnect and alignment system

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4667219A (en) * 1984-04-27 1987-05-19 Trilogy Computer Development Partners, Ltd. Semiconductor chip interface
JPS61173471A (ja) * 1985-01-28 1986-08-05 シャープ株式会社 熱圧着コネクタ−
US4902857A (en) * 1988-12-27 1990-02-20 American Telephone And Telegraph Company, At&T Bell Laboratories Polymer interconnect structure
JPH0793342B2 (ja) * 1988-12-29 1995-10-09 シャープ株式会社 電極の形成方法
JPH0740496B2 (ja) * 1989-03-01 1995-05-01 シャープ株式会社 電極上への導電性粒子の配置方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100349896B1 (ko) * 1994-12-28 2002-12-26 삼성에스디아이 주식회사 집적회로칩의실장구조체및그실장방법
KR100376044B1 (ko) * 1999-05-13 2003-03-15 한오근 반도체 패키지의 솔더 및 이를 이용한 반도체 패키지
US8120188B2 (en) 2006-11-28 2012-02-21 Panasonic Corporation Electronic component mounting structure and method for manufacturing the same

Also Published As

Publication number Publication date
DE4223280A1 (de) 1993-01-21

Similar Documents

Publication Publication Date Title
US5801446A (en) Microelectronic connections with solid core joining units
US6583515B1 (en) Ball grid array package for enhanced stress tolerance
KR100886778B1 (ko) 컴플라이언트 전기 단자들을 갖는 장치 및 그 제조 방법들
US6265775B1 (en) Flip chip technique for chip assembly
JP4698125B2 (ja) バンプおよびポリマー層を有しない、基板アセンブリのためのフリップチップ
US6696757B2 (en) Contact structure for reliable metallic interconnection
US4902857A (en) Polymer interconnect structure
JP2825083B2 (ja) 半導体素子の実装構造
US7423348B2 (en) Chip structure and chip package structure
US20030197285A1 (en) High density substrate for the packaging of integrated circuits
JPH09199535A (ja) 半導体集積回路の電極構造およびそのパッケージ形成方法
JP3450236B2 (ja) 半導体装置及びその製造方法
JPH09232373A (ja) 半導体装置
KR20030080032A (ko) 플립 칩 상호연결을 구비한 칩 스케일 패키지
US20020041037A1 (en) Semiconductor device and process of producing same
US6841884B2 (en) Semiconductor device
US20010031515A1 (en) Semiconductor device and method of manufacturing the same, circuit board and electronic instrument
JPH0521519A (ja) 半導体装置
JP2000269271A (ja) 半導体回路装置およびその製造方法
JP3339881B2 (ja) 半導体集積回路装置およびその製造方法
US6649833B1 (en) Negative volume expansion lead-free electrical connection
JPH0666355B2 (ja) 半導体装置の実装体およびその実装方法
JP4029255B2 (ja) 接着部材
JP3529507B2 (ja) 半導体装置
Zakel et al. Fluxless flip chip assembly on rigid and flexible polymer substrates using the Au-Sn metallurgy

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19981008