JPH02146757A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02146757A
JPH02146757A JP63301435A JP30143588A JPH02146757A JP H02146757 A JPH02146757 A JP H02146757A JP 63301435 A JP63301435 A JP 63301435A JP 30143588 A JP30143588 A JP 30143588A JP H02146757 A JPH02146757 A JP H02146757A
Authority
JP
Japan
Prior art keywords
semiconductor
die
solder
semiconductor die
die pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63301435A
Other languages
Japanese (ja)
Inventor
Seizo Omae
大前　誠蔵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP63301435A priority Critical patent/JPH02146757A/en
Publication of JPH02146757A publication Critical patent/JPH02146757A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8314—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features

Abstract

PURPOSE:To make the thickness of a solder below a semiconductor die uniform and obtain a highly reliable semiconductor device by placing a plurality of protruding bases which are of the same height for placing a semiconductor die on the surface of a die pad of a semiconductor frame. CONSTITUTION:In a semiconductor device for mounting a semiconductor die 2 on a die pad 1 of a semiconductor lead frame through a solder 3, a plurality of protruding bases 4 which are of the same height for placing the semiconductor die are placed. Thus, when the solder 3 is adhered and the semiconductor die 2 is mounted, the lower surface of the semiconductor die 2 comes into contact with the protruding base 4 and is adhered between the surfaces of the semiconductor die 2 and the die pad 1 through the solder 3. Since the height of the protruding base 4 is uniform, the thickness of the solder 3 also becomes uniform. Therefore, with a simple configuration, a highly reliable semiconductor device can be obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体ダイを搭載する半導体リードフレー
ムに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor lead frame on which a semiconductor die is mounted.

〔従来の技術〕[Conventional technology]

第３図は従来の半導体リードフレームのダイパッド上に
半導体ダイを搭載した状態を示す斜視図であり、第４図
はその断面図である。第３図、第４図において、１は表
面が一様に平坦な半導体リードフレームのダイパッドで
あり、このダイパッドの平坦な表面上に、半導体ダイ２
をソルダー３を介して搭載したものである。ところでこ
のとき、ソルダー３として半田（Ｐｂ／Ｓｎ　）を用い
る場合は搭載時に半導体リードフレームのダイパッド１
上に半田を付着して加熱した後、半導体ダイ２を圧着す
る。また、ソルダー３に樹脂を使用する場合は、この樹
脂を半導体リードフレームのダイハツトｌ上に付着して
半導体ダイ２を圧着した後、加熱し、硬化するものであ
る。以上の方法により、半導体２を半導体リードフレー
ムのダイパッド１上に接着する。FIG. 3 is a perspective view showing a state in which a semiconductor die is mounted on a die pad of a conventional semiconductor lead frame, and FIG. 4 is a sectional view thereof. 3 and 4, 1 is a die pad of a semiconductor lead frame whose surface is uniformly flat, and a semiconductor die 2 is placed on the flat surface of this die pad.
is mounted via solder 3. By the way, at this time, if solder (Pb/Sn) is used as the solder 3, the die pad 1 of the semiconductor lead frame is
After applying solder thereon and heating it, the semiconductor die 2 is crimped. Further, when a resin is used for the solder 3, the resin is adhered onto the die hat l of the semiconductor lead frame, the semiconductor die 2 is pressed, and then heated and cured. By the above method, the semiconductor 2 is bonded onto the die pad 1 of the semiconductor lead frame.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の半導体リードフレームのダイパッド表面が平坦な
場合、これに半導体ダイを搭載するとき、ソルダーは液
相のため、第４図に示すように、半導体ダイがダイパッ
ド表面に対して傾くという問題点があった。そしてこの
傾きは、半導体ダイの下のソルダーの厚みが均一でない
ということから、放熱性、耐熱ストレス性等に関して信
頼性の低い半導体装置となってしまうという問題があっ
た。If the die pad surface of a conventional semiconductor lead frame is flat, when a semiconductor die is mounted on it, the problem is that the semiconductor die is tilted with respect to the die pad surface, as shown in Figure 4, because the solder is in a liquid phase. there were. This slope causes a problem in that the thickness of the solder under the semiconductor die is not uniform, resulting in a semiconductor device with low reliability in terms of heat dissipation, heat stress resistance, etc.

この発明は上記のような問題点を解消するためになされ
たもので、半導体ダイの下のソルダーの厚みを均一にし
、信頼性の高い半導体装置を得ることを目的とする。This invention was made to solve the above-mentioned problems, and aims to make the thickness of the solder under the semiconductor die uniform and obtain a highly reliable semiconductor device.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置は、半導体リードフレームの
ダイパッドの表面に、半導体ダイか安定して載置し得る
同一高さの複数の突起台を配設したものである。In the semiconductor device according to the present invention, a plurality of protrusions having the same height on which a semiconductor die can be stably placed are arranged on the surface of a die pad of a semiconductor lead frame.

〔作用〕[Effect]

この発明における突起台により、半導体ダイの下にある
ソルダーの厚みが均一になり、このことにより、半導体
装置として使用したとき半導体ダイから発生する熱が半
導体リードフレームに均一に放散され、才な、半導体装
置を基板に実装する際に発生する熱ストレスに対して信
頼性が高い。The protruding base in this invention makes the thickness of the solder under the semiconductor die uniform, and thereby, when used as a semiconductor device, the heat generated from the semiconductor die is uniformly dissipated to the semiconductor lead frame. High reliability against thermal stress that occurs when semiconductor devices are mounted on substrates.

〔実施例〕〔Example〕

以下この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第１図は半導体リードフレームのダイパッドの斜視図、
第２図はダイパッド上に半導体ダイを搭載した状態の断
面図である。Figure 1 is a perspective view of the die pad of a semiconductor lead frame.
FIG. 2 is a cross-sectional view of a semiconductor die mounted on a die pad.

上記従来例のものと異なるところは、半導体リードフレ
ームのダイパッド１の表面（半導体ダイ２を搭載する面
）に、同一高さの複数（図では４個）の突起台４を配設
したものである。The difference from the conventional example above is that a plurality of (four in the figure) protrusion bases 4 of the same height are arranged on the surface of the die pad 1 of the semiconductor lead frame (the surface on which the semiconductor die 2 is mounted). be.

このようなものにおいて、ソルダー３を付着して半導体
ダイ２を搭載すると、半導体ダイ２の下面が突起台４に
接触し載置されるとともに、半導体ダイ２とダイパッド
１の表面の間にソルダー３が介在して接着される。そし
てこのとき突起台の高さが均一のため、ソルダーの厚み
も均一になるものである。In such a device, when the semiconductor die 2 is mounted with the solder 3 attached, the lower surface of the semiconductor die 2 is placed in contact with the protrusion base 4, and the solder 3 is placed between the semiconductor die 2 and the surface of the die pad 1. is interposed and bonded. At this time, since the height of the protruding base is uniform, the thickness of the solder is also uniform.

なお上記実施例では、突起台の形状を円筒形としたが、
他の形状でもよく、半導体ダイと接触する部が平坦であ
ればよい。才な突起台の数を４個としたが、数量はいく
らでもよい。In the above embodiment, the shape of the protrusion base is cylindrical, but
Other shapes may be used as long as the portion that contacts the semiconductor die is flat. Although the number of protrusions was set at four, any number may be used.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、ダイパッドの表面に複
数の同一高さの突起台を設けるという極めて簡単な構成
により、信頼性の高い半導体装置が得られる効果がある
。As described above, according to the present invention, a highly reliable semiconductor device can be obtained with an extremely simple configuration in which a plurality of protruding bases of the same height are provided on the surface of a die pad.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明の一実施例による半導体リードフレー
ムのダイパッドを示す斜視図、第２図はこのダイパッド
上に半導体ダイを搭載した状態を示す断面図、第３図は
従来の半導体リードフレームのダイパッドに半導体ダイ
を搭載した状態を示す斜視図、第４図は第３図の断面図
である。 図中、１は半導体リードフレームのダイパッド、２は半
導体ダイ、３はソルダー、４は突起台である。 なお、図中同一符号は同−又は相当部分を示す。FIG. 1 is a perspective view showing a die pad of a semiconductor lead frame according to an embodiment of the present invention, FIG. 2 is a sectional view showing a semiconductor die mounted on the die pad, and FIG. 3 is a perspective view of a conventional semiconductor lead frame. FIG. 4 is a perspective view showing a state in which a semiconductor die is mounted on the die pad, and FIG. 4 is a sectional view of FIG. 3. In the figure, 1 is a die pad of a semiconductor lead frame, 2 is a semiconductor die, 3 is a solder, and 4 is a protrusion base. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 半導体リードフレームのダイパッド上に半導体ダイをソ
ルダーを介して搭載する半導体装置において、上記ダイ
パッド表面に、その上に上記半導体ダイを載せるための
同一高さの複数の突起台を配設したことを特徴とする半
導体装置。A semiconductor device in which a semiconductor die is mounted on a die pad of a semiconductor lead frame via a solder, characterized in that a plurality of protrusions having the same height are provided on the surface of the die pad for mounting the semiconductor die thereon. semiconductor device.
JP63301435A 1988-11-28 1988-11-28 Semiconductor device Pending JPH02146757A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63301435A JPH02146757A (en) 1988-11-28 1988-11-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63301435A JPH02146757A (en) 1988-11-28 1988-11-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02146757A true JPH02146757A (en) 1990-06-05

Family

ID=17896850

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63301435A Pending JPH02146757A (en) 1988-11-28 1988-11-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02146757A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05243469A (en) * 1992-02-28 1993-09-21 Nec Kyushu Ltd Lead frame for semiconductor device
JP2002093855A (en) * 2000-09-18 2002-03-29 Toshiba Corp Semiconductor device
DE10139681A1 (en) * 2001-08-11 2003-03-06 Infineon Technologies Ag Electronic component used in MOSFETs comprises a plate-like support element having a contact zone and a semiconductor body applied on the contact zone of the support element
EP1134806A3 (en) * 2000-03-16 2003-11-12 Microchip Technology Inc. Stress reducing lead-frame for plastic encapsulation
JP2009087964A (en) * 2007-09-27 2009-04-23 Kyocera Corp Electronic component
CN103426780A (en) * 2012-05-14 2013-12-04 万国半导体(开曼)股份有限公司 Solder ball array used as height cushion block and solder fixture
WO2014061204A1 (en) * 2012-10-18 2014-04-24 株式会社デンソー Semiconductor device and method for manufacturing same
EP2690658A4 (en) * 2011-03-24 2015-10-28 Mitsubishi Electric Corp Power semiconductor module and power unit device
IT202000008119A1 (en) * 2020-04-16 2021-10-16 St Microelectronics Srl Production of integrated devices from lead-frames with spacers
JPWO2020175619A1 (en) * 2019-02-28 2021-12-16 京セラ株式会社 Package for mounting electronic components, electronic devices and light emitting devices
US11916353B2 (en) 2020-04-16 2024-02-27 Stmicroelectronics (Grenoble 2) Sas Electronic chip support device and corresponding manufacturing method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02144954A (en) * 1988-11-28 1990-06-04 Matsushita Electron Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02144954A (en) * 1988-11-28 1990-06-04 Matsushita Electron Corp Semiconductor device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05243469A (en) * 1992-02-28 1993-09-21 Nec Kyushu Ltd Lead frame for semiconductor device
EP1134806A3 (en) * 2000-03-16 2003-11-12 Microchip Technology Inc. Stress reducing lead-frame for plastic encapsulation
JP2002093855A (en) * 2000-09-18 2002-03-29 Toshiba Corp Semiconductor device
DE10139681A1 (en) * 2001-08-11 2003-03-06 Infineon Technologies Ag Electronic component used in MOSFETs comprises a plate-like support element having a contact zone and a semiconductor body applied on the contact zone of the support element
JP2009087964A (en) * 2007-09-27 2009-04-23 Kyocera Corp Electronic component
EP2690658A4 (en) * 2011-03-24 2015-10-28 Mitsubishi Electric Corp Power semiconductor module and power unit device
CN103426780A (en) * 2012-05-14 2013-12-04 万国半导体(开曼)股份有限公司 Solder ball array used as height cushion block and solder fixture
WO2014061204A1 (en) * 2012-10-18 2014-04-24 株式会社デンソー Semiconductor device and method for manufacturing same
JPWO2020175619A1 (en) * 2019-02-28 2021-12-16 京セラ株式会社 Package for mounting electronic components, electronic devices and light emitting devices
IT202000008119A1 (en) * 2020-04-16 2021-10-16 St Microelectronics Srl Production of integrated devices from lead-frames with spacers
US11916353B2 (en) 2020-04-16 2024-02-27 Stmicroelectronics (Grenoble 2) Sas Electronic chip support device and corresponding manufacturing method

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