JPH05243469A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPH05243469A
JPH05243469A JP9898492A JP9898492A JPH05243469A JP H05243469 A JPH05243469 A JP H05243469A JP 9898492 A JP9898492 A JP 9898492A JP 9898492 A JP9898492 A JP 9898492A JP H05243469 A JPH05243469 A JP H05243469A
Authority
JP
Japan
Prior art keywords
lead frame
island
semiconductor element
semiconductor device
protruding parts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9898492A
Other languages
Japanese (ja)
Other versions
JP2852155B2 (en
Inventor
Takashi Okumura
敬司 奥村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP4098984A priority Critical patent/JP2852155B2/en
Publication of JPH05243469A publication Critical patent/JPH05243469A/en
Application granted granted Critical
Publication of JP2852155B2 publication Critical patent/JP2852155B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8314—Guiding structures outside the body

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To easily set a semiconductor element so as to be parallel with an island and ensure a specified distance from the island, by forming protruding parts in the island part of a lead frame. CONSTITUTION:In the island part 1 of a lead frame, protruding parts 2 having a specified height are arranged at the parts corresponding to four corners and the center of a semiconductor device. The rear of the semiconductor element 4 comes into point contact with the protruding parts, and is set in parallel with the island. Soldering material 5 permeates into the part between the protruding parts 2, so that the semiconductor element 4 can ensure a gap from the island which gap is equal to the height of the protruding parts 2, which can be set in the course of manufacturing the lead frame. When the five protruding parts are formed and a square frame taping is arranged, the semiconductor device 4 is in parallel with the island part 1 and the specified height can be ensured, so that the influence of expansion coefficient can be avoided.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は半導体装置用リードフレ
ーム、さらに詳しくいえば、半導体素子を搭載するアイ
ランド部の構造を考慮したリードフレームに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for a semiconductor device, and more particularly to a lead frame in consideration of the structure of an island portion on which a semiconductor element is mounted.

【０００２】[0002]

【従来の技術】従来の樹脂封止形半導体装置の製造過程
において半導体素子をリードフレームに固定する方法は
図３に示すような平坦なアイランド部に接着剤（以下
「ロー材」という）を塗布する際、塗布量調整加圧を調
整し、多量のロー材をアイランド部に塗布し、所望の厚
さ（３０±１０μｍ）になるように設定していた。これ
は樹脂封止後、半導体素子とリードフレームのアイラン
ド部の膨張率の相違により発生する封止樹脂クラック対
策のためである。2. Description of the Related Art A conventional method for fixing a semiconductor element to a lead frame in the process of manufacturing a resin-sealed semiconductor device is to apply an adhesive (hereinafter referred to as "raw material") to a flat island portion as shown in FIG. At this time, the application amount adjustment pressure was adjusted, a large amount of brazing material was applied to the island portion, and the desired thickness (30 ± 10 μm) was set. This is to prevent a sealing resin crack that occurs due to a difference in expansion coefficient between the semiconductor element and the island portion of the lead frame after the resin sealing.

【０００３】[0003]

【発明が解決しようとする課題】上述の従来の半導体装
置用リードフレームでは、アイランド部が平坦になって
いるので、ロー材を厚く塗布した後、半導体素子を接着
する際、半導体素子が傾いたり、所望のロー材厚にする
ための条件出し工数が多くなるという欠点があった。本
発明の目的は上記欠点を解決するもので、アイランド部
に半導体素子を接着する際、接着のための工数を少なく
できる半導体装置用リードフレームを提供することにあ
る。In the conventional lead frame for a semiconductor device described above, since the island portion is flat, the semiconductor element may be tilted when the semiconductor element is bonded after the brazing material is applied thickly. However, there is a drawback that the number of man-hours for setting conditions for obtaining a desired brazing material thickness increases. An object of the present invention is to solve the above drawbacks and to provide a lead frame for a semiconductor device, which can reduce the number of steps for bonding when bonding a semiconductor element to an island portion.

【０００４】[0004]

【課題を解決するための手段】前記目的を達成するため
に本発明による半導体装置用リードフレームは半導体素
子をマウントするリードフレームにおいて、リードフレ
ームのアイランド部に半導体素子の下面を支持する凸部
を有して構成されている。そして、前記アイランド部の
凸部は半導体素子の四隅および中央部に設けて構成する
ことができる。また、前記アイランド部の凸部はテープ
で構成することもできる。In order to achieve the above object, a lead frame for a semiconductor device according to the present invention is a lead frame for mounting a semiconductor element, wherein a projecting portion for supporting a lower surface of the semiconductor element is provided on an island portion of the lead frame. It is configured to have. The convex portions of the island portion can be provided at the four corners and the central portion of the semiconductor element. Further, the convex portion of the island portion may be made of tape.

【０００５】[0005]

【作用】上記構成によれば、半導体素子を平行、かつア
イランドより一定の距離を保つことができ、従来の半導
体装置の製造過程に比較し接着工数を少なくすることが
できる。According to the above structure, the semiconductor elements can be kept parallel to each other and can be kept at a constant distance from the island, and the number of bonding steps can be reduced as compared with the conventional semiconductor device manufacturing process.

【０００６】[0006]

【実施例】以下、図面を参照して本発明をさらに詳しく
説明する。図１（ａ）は本発明による半導体装置用リー
ドフレームの実施例を示す斜視図である。リードフレー
ムのアイランド部１には、半導体素子の四隅と中央部に
対応する部分に一定の高さの凸部２を設けてある。図１
（ｂ）は図１（ａ）のアイランド部１に半導体素子を搭
載した状態を示す断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in more detail below with reference to the drawings. FIG. 1A is a perspective view showing an embodiment of a lead frame for a semiconductor device according to the present invention. The island portion 1 of the lead frame is provided with convex portions 2 having a constant height at portions corresponding to the four corners and the central portion of the semiconductor element. Figure 1
FIG. 1B is a sectional view showing a state in which a semiconductor element is mounted on the island portion 1 of FIG.

【０００７】半導体素子４の裏面が凸部２と点接点とな
り、アイランド１に対し平行になる。そして、凸部２の
間にはロー材５が入り込むので、半導体素子４はアイラ
ンド部１との間で凸部２の高さだけ間隔を保つことがで
きる。ここで、凸部の高さはリードフレーム製造工程中
において設定が可能である。The back surface of the semiconductor element 4 forms a point contact with the convex portion 2 and is parallel to the island 1. Then, since the brazing material 5 enters between the convex portions 2, the semiconductor element 4 can keep a distance from the island portion 1 by the height of the convex portion 2. Here, the height of the convex portion can be set during the lead frame manufacturing process.

【０００８】図２は本発明の他の実施例を示すリードフ
レームの斜視図である。図１ではアイランド部に合計５
個の凸部を設けたが、この実施例では四角枠のテーピン
グ６を施している。このように構成しても半導体素子と
アイランド部が平行、かつ所定の高さが得られ、膨張率
の影響を受けないようにすることができる。FIG. 2 is a perspective view of a lead frame showing another embodiment of the present invention. In Figure 1, a total of 5 islands
Although the individual convex portions are provided, taping 6 of a rectangular frame is applied in this embodiment. Even with such a configuration, the semiconductor element and the island portion are parallel to each other and a predetermined height can be obtained, so that the influence of the expansion coefficient can be prevented.

【０００９】[0009]

【発明の効果】以上、説明したように本発明はリードフ
レームのアイランド部に凸部を設けてあるので、半導体
素子をアイランド部に接着する際、アイランドに対する
平行度および所定の間隔を容易に得ることができ、接着
のための工数を減少させることができる。As described above, according to the present invention, the projecting portion is provided on the island portion of the lead frame. Therefore, when the semiconductor element is bonded to the island portion, the parallelism with respect to the island and a predetermined interval can be easily obtained. Therefore, the number of steps for bonding can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図１】（ａ）は本発明による半導体装置用リードフレ
ームの実施例を示す斜視図である。（ｂ）は半導体素子
マウント後の断面図である。FIG. 1A is a perspective view showing an embodiment of a lead frame for a semiconductor device according to the present invention. (B) is a cross-sectional view after mounting the semiconductor element.

【図２】本発明の他の実施例を示す斜視図である。FIG. 2 is a perspective view showing another embodiment of the present invention.

【図３】従来のリードフレームのアイランド部を示す斜
視図である。FIG. 3 is a perspective view showing an island portion of a conventional lead frame.

【符号の説明】[Explanation of symbols]

１…リードフレームのアイランド部 ２…凸部 ３…インナリード ４…半導体素子 ５…ロー材 ６…テーピング 1 ... Island part of lead frame 2 ... Convex part 3 ... Inner lead 4 ... Semiconductor element 5 ... Brazing material 6 ... Taping

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 半導体素子をマウントするリードフレー
ムにおいて、 リードフレームのアイランド部に半導体素子の下面を支
持する凸部を有することを特徴とする半導体装置用リー
ドフレーム。1. A lead frame for mounting a semiconductor element, comprising: a lead frame for a semiconductor device, wherein an island portion of the lead frame has a convex portion for supporting a lower surface of the semiconductor element. 【請求項２】 前記アイランド部の凸部は半導体素子の
四隅および中央部に設けたことを特徴とする請求項１記
載の半導体装置用リードフレーム。2. The lead frame for a semiconductor device according to claim 1, wherein the convex portions of the island portion are provided at four corners and a central portion of the semiconductor element. 【請求項３】 前記アイランド部の凸部はテープである
請求項１記載の半導体装置用リードフレーム。3. The lead frame for a semiconductor device according to claim 1, wherein the convex portion of the island portion is a tape.
JP4098984A 1992-02-28 1992-02-28 Lead frame for semiconductor device Expired - Fee Related JP2852155B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4098984A JP2852155B2 (en) 1992-02-28 1992-02-28 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4098984A JP2852155B2 (en) 1992-02-28 1992-02-28 Lead frame for semiconductor device

Publications (2)

Publication Number Publication Date
JPH05243469A true JPH05243469A (en) 1993-09-21
JP2852155B2 JP2852155B2 (en) 1999-01-27

Family

ID=14234270

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4098984A Expired - Fee Related JP2852155B2 (en) 1992-02-28 1992-02-28 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JP2852155B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19802575B4 (en) * 1997-01-25 2005-10-13 LG Semicon Co., Ltd., Cheongju A method of manufacturing a unit for a ball grid array semiconductor device and producing a ball grid array semiconductor device
WO2014061204A1 (en) * 2012-10-18 2014-04-24 株式会社デンソー Semiconductor device and method for manufacturing same
JPWO2020175619A1 (en) * 2019-02-28 2021-12-16 京セラ株式会社 Package for mounting electronic components, electronic devices and light emitting devices

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01154545A (en) * 1987-12-10 1989-06-16 Mitsubishi Electric Corp Resin-sealed semiconductor device
JPH02146757A (en) * 1988-11-28 1990-06-05 Mitsubishi Electric Corp Semiconductor device
JPH03149864A (en) * 1989-11-07 1991-06-26 Matsushita Electron Corp Lead frame

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01154545A (en) * 1987-12-10 1989-06-16 Mitsubishi Electric Corp Resin-sealed semiconductor device
JPH02146757A (en) * 1988-11-28 1990-06-05 Mitsubishi Electric Corp Semiconductor device
JPH03149864A (en) * 1989-11-07 1991-06-26 Matsushita Electron Corp Lead frame

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19802575B4 (en) * 1997-01-25 2005-10-13 LG Semicon Co., Ltd., Cheongju A method of manufacturing a unit for a ball grid array semiconductor device and producing a ball grid array semiconductor device
WO2014061204A1 (en) * 2012-10-18 2014-04-24 株式会社デンソー Semiconductor device and method for manufacturing same
JPWO2020175619A1 (en) * 2019-02-28 2021-12-16 京セラ株式会社 Package for mounting electronic components, electronic devices and light emitting devices

Also Published As

Publication number Publication date
JP2852155B2 (en) 1999-01-27

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A02 Decision of refusal

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Effective date: 19980421

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