JP2002093855A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2002093855A
JP2002093855A JP2000281212A JP2000281212A JP2002093855A JP 2002093855 A JP2002093855 A JP 2002093855A JP 2000281212 A JP2000281212 A JP 2000281212A JP 2000281212 A JP2000281212 A JP 2000281212A JP 2002093855 A JP2002093855 A JP 2002093855A
Authority
JP
Japan
Prior art keywords
chip
mounting portion
semiconductor chip
semiconductor device
chip mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000281212A
Other languages
Japanese (ja)
Inventor
Takahito Nakazawa
沢 孝 仁 中
Kazuyasu Tanaka
中 一 安 田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2000281212A priority Critical patent/JP2002093855A/en
Publication of JP2002093855A publication Critical patent/JP2002093855A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To ensure an ohmic contact for the problem, where electrical continuity between a semiconductor chip and the pad of a chip-mounting portion for mounting thereon the semiconductor chip is to be secured, while making it lead-free, by improving the structure of an attaching portion of the semiconductor chip to the chip-mounting portion. SOLUTION: In a form where conductive particles 12, composed of a conductive material, are scattered in between a semiconductor chip 4 and a chip- mounting portion 5, the semiconductor chip 4 and the chip-mounting portion 5 are bonded to each other by a die-attaching material 6, which is composed of a material containing no lead. Thereby, electrical continuity between the semiconductor chip 4 and the chip-mounting portion 5 is ensured entirely by the conductive particles 12, and proper electrical continuity properties are obtained.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置に係
り、例えばＭＯＳ−ＦＥＴやＩＧＢＴなどのオーミック
コンタクトが必要なディスクリート製品において鉛フリ
ーを実現するに好適な半導体チップのパッケージへの実
装構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a mounting structure of a semiconductor chip suitable for realizing lead-free in a discrete product requiring an ohmic contact such as a MOS-FET or IGBT.

【０００２】[0002]

【従来の技術】一般に、パワー素子を実装する半導体装
置では、内部でオーミックコンタクトを採ることが非常
に重要とされている。そして、このような半導体装置で
は、チップすなわちダイを、リードフレームに接着する
ためのダイアタッチ材として、鉛を含んだ多元系金属が
使われている。近年、鉛の環境問題がクローズアップさ
れいるものの、このようなダイアタッチ材において鉛フ
リーとすることにはほとんど関心が払われていない。2. Description of the Related Art Generally, it is very important to form an ohmic contact inside a semiconductor device on which a power element is mounted. In such a semiconductor device, a multi-component metal containing lead is used as a die attach material for bonding a chip or a die to a lead frame. In recent years, although the environmental problems of lead have been highlighted, little attention has been paid to making such die attach materials lead-free.

【０００３】鉛系に代わるダイアタッチ材としては、銀
フィラ入りのエポキシ樹脂ペーストが知られているが、
金属と比較すると、電気伝導性が低く、必要な特性を得
ることができないという問題点がある。[0003] An epoxy resin paste containing silver filler is known as a die attach material in place of a lead-based material.
As compared with metals, there is a problem in that electric conductivity is low and required characteristics cannot be obtained.

【０００４】図６は、一般的な半導体装置の正面図であ
り、特にパワートランジスタの外観を示すものである。
図示しないパワートランジスタのチップは、モールド樹
脂１１に封入されており、モールド樹脂１１からそれぞ
れエミッタ、コレクタ、ベースに相当する端子（アウタ
ー端子）１、２、３が導出されている。これらの端子
１、２、３はこの半導体装置のリードフレームを構成す
る。FIG. 6 is a front view of a general semiconductor device, and particularly shows the appearance of a power transistor.
A power transistor chip (not shown) is sealed in a mold resin 11, and terminals (outer terminals) 1, 2, and 3 corresponding to an emitter, a collector, and a base are led out of the mold resin 11, respectively. These terminals 1, 2, and 3 constitute a lead frame of the semiconductor device.

【０００５】さて、図７は、図６のような半導体装置の
内部構造を示す従来例であり、正面から見た透視図であ
る。また、図８は、従来例に係る半導体装置の縦断面図
であり、特に、図６のＡ−Ａに対応する線で得た断面図
を示すものである。FIG. 7 is a conventional example showing the internal structure of the semiconductor device as shown in FIG. 6, and is a perspective view seen from the front. FIG. 8 is a longitudinal sectional view of a semiconductor device according to a conventional example, and particularly shows a sectional view taken along a line corresponding to AA in FIG.

【０００６】各図において示すように、パワートランジ
スタを構成する半導体チップ４は、端子１、２、３と共
にリードフレームを形成するチップ搭載部５にダイアタ
ッチ材６により接着されている。As shown in each figure, a semiconductor chip 4 constituting a power transistor is bonded to a chip mounting portion 5 forming a lead frame together with terminals 1, 2, and 3 by a die attach material 6.

【０００７】なお、パワートランジスタのコレクタは、
半導体チップ４のチップ裏面１０となっているため、ダ
イアタッチ材６からチップ搭載部５を介して、端子２に
対する電気的な接続が行われる。その結果、半導体チッ
プ４のコレクタが、モールド樹脂１１外の端子２に導出
される。The collector of the power transistor is
Since it is the chip back surface 10 of the semiconductor chip 4, electrical connection to the terminal 2 is made from the die attach material 6 via the chip mounting portion 5. As a result, the collector of the semiconductor chip 4 is led out to the terminal 2 outside the mold resin 11.

【０００８】半導体チップ４をチップ搭載部５に接着す
るダイアタッチ材６には、Ｐｂ・Ｓｎ・Ａｇ・Ｃｕ、Ｐ
ｂ・ＳｎまたはＳｎ・Ｓｂ・Ｐなどの半田材が使われ
る。The die attach material 6 for bonding the semiconductor chip 4 to the chip mounting portion 5 includes Pb, Sn, Ag, Cu, P
A solder material such as b.Sn or Sn.Sb.P is used.

【０００９】半導体チップ４の表面には、それぞれパワ
ートランジスタのエミッタ、ベースに対応するボンディ
ングパッド７が形成されている。これらのボンディング
パッド７は、端子１、３と共にリードフレームを形成す
るボンディングポスト８と、Ａｕ、Ｃｕ、Ａｌなどの材
質で作られるボンディングワイア９により電気的に結ば
れる。その結果、半導体チップ４のエミッタ、ベース
が、それぞれモールド樹脂１１外の端子１、３に導出さ
れる。On the surface of the semiconductor chip 4, bonding pads 7 corresponding to the emitter and the base of the power transistor are formed, respectively. These bonding pads 7 are electrically connected to bonding posts 8 forming a lead frame together with the terminals 1 and 3 by bonding wires 9 made of a material such as Au, Cu, or Al. As a result, the emitter and the base of the semiconductor chip 4 are led out to the terminals 1 and 3 outside the mold resin 11, respectively.

【００１０】さて、半導体チップ４をチップ搭載部５に
接着するダイアタッチ材６の材料の選択は、ワイヤボン
ディングに用いられるボンディングワイア９と関係す
る。例えば、直径が２０〜５０μｍと比較的細いＡｕ／
Ｃｕ線をボンディングする場合は、ボンディング温度が
２８０から３００℃と高温であるため、融点が比較的高
めの半田Ｐｂ・Ｓｎ・Ａｇ・Ｃｕ（融点３６０℃）を用
いる。一方、ボンディングワイア９の直径が数１００μ
ｍと比較的太いＡｌ線をボンディングする場合は、ボン
ディング温度が常温でよいので、比較的融点の低いＰｂ
・Ｓｎ半田（共晶：融点１８２℃）やＳｎ・Ｓｂ・Ｐ
（融点２４５℃）を選択する。Now, the selection of the material of the die attach material 6 for bonding the semiconductor chip 4 to the chip mounting portion 5 is related to the bonding wire 9 used for wire bonding. For example, a relatively thin Au /
When bonding a Cu wire, since the bonding temperature is as high as 280 to 300 ° C., solder Pb, Sn, Ag, Cu having a relatively high melting point (melting point 360 ° C.) is used. On the other hand, the diameter of the bonding wire 9 is several hundred μm.
When bonding an Al wire having a relatively large thickness of m, the bonding temperature may be room temperature, so that Pb having a relatively low melting point may be used.
・ Sn solder (eutectic: melting point 182 ° C) or Sn ・ Sb ・ P
(Melting point: 245 ° C.).

【００１１】なお、半導体チップ４のチップ裏面１０に
はＶ／Ｎｉ／Ａｕ金属が蒸着されている。このチップ裏
面１０とチップ搭載部５はオーミックコンタクトを形成
しなくてはならないので、信頼性の面からはもちろん、
電気的にも非常に重要な接合である。Note that V / Ni / Au metal is deposited on the chip back surface 10 of the semiconductor chip 4. Since the chip back surface 10 and the chip mounting portion 5 must form an ohmic contact, of course, from the viewpoint of reliability,
This is a very important junction electrically.

【００１２】ダイアタッチ材６による半導体チップ４の
チップ搭載部５へのダイアタッチが終了し、ボンディン
グワイア９によるボンディングパッド７とボンディング
ポスト８の間のボンディングが終了すると、端子１、
２、３を残して、全体をエポキシ樹脂によりモールドし
て、モールド樹脂１１により全体を覆う。When the die attach of the semiconductor chip 4 to the chip mounting portion 5 by the die attach material 6 is completed and the bonding between the bonding pad 7 and the bonding post 8 by the bonding wire 9 is completed, the terminals 1 and 2 are removed.
Except for a few parts, the whole is molded with epoxy resin, and the whole is covered with mold resin 11.

【００１３】モールド完了後に、端子１、２、３の露出
部分を、共晶Ｐｂ・Ｓｎ半田によりメッキする。After the completion of molding, the exposed portions of the terminals 1, 2, and 3 are plated with eutectic Pb.Sn solder.

【００１４】なお、モールド工程に先立って、ボンディ
ングワイア９および半導体チップ４を、シリコーン樹脂
などでエンキャップする場合もある。Note that the bonding wire 9 and the semiconductor chip 4 may be encapsulated with a silicone resin or the like before the molding step.

【００１５】ゲートアレイのようなＡＳＩＣ、汎用ロジ
ック、メモリなどでは、ダイアタッチ材としてエポキシ
樹脂やアクリル樹脂をベースにして、これに銀フィラを
混ぜた銀ペーストが用いられている。このため、鉛フリ
ーのためには、このような銀ペーストを用いるのがよ
い。In an ASIC such as a gate array, a general-purpose logic, a memory, and the like, a silver paste obtained by mixing a silver filler with an epoxy resin or an acrylic resin as a die attach material is used. Therefore, it is preferable to use such a silver paste for lead-free.

【００１６】しかし、銀ペーストは、トンネル電流によ
り電気的導通が可能であるが、接触抵抗が高く、半田に
比較すると電気的な特性が劣るという問題点がある。体
積抵抗率で比較すると、Ｐｂ・Ｓｎ半田が、約５Ｘ１０
Ｅ−５Ω・ｃｍであるのに対して、フィラ量８５Ｗｔ％
〜９０Ｗｔ％と、高充填の銀ペーストでも、約１〜２Ｘ
１０Ｅ−４Ω・ｃｍと大きい。今後、鉛フリーである銀
ペーストの電気伝導性を更に改良しても、現在の鉛入り
の半田に匹敵する程度まで向上することは期待できな
い。[0016] However, silver paste can be electrically conducted by a tunnel current, but has a problem in that it has a high contact resistance and is inferior in electric characteristics as compared with solder. Comparing by volume resistivity, Pb.Sn solder is about 5 × 10
E-5Ω · cm, but filler amount 85Wt%
~ 90Wt%, even with highly filled silver paste, about 1-2X
It is as large as 10E-4Ω · cm. In the future, even if the electrical conductivity of the lead-free silver paste is further improved, it cannot be expected to be improved to a level comparable to the current lead-containing solder.

【００１７】以上のように、銀ペーストは電気伝導性が
悪いため、パワートランジスタのようにオーミックコン
タクトが必要な半導体装置では使うことができない。こ
のため、パワートランジスタでは、外装メッキだけでは
なく、ダイアタッチの接着層に使っている半田も鉛入り
となることが多い。As described above, since silver paste has poor electric conductivity, it cannot be used in a semiconductor device requiring an ohmic contact such as a power transistor. For this reason, in the power transistor, not only the outer plating but also the solder used for the adhesive layer of the die attach often contains lead.

【００１８】一方、一般的な傾向として、開発コストの
低減、装置価格の低減などの観点から、チップをシュリ
ンクする試みが多くなされているが、チップ面積の低減
は、そのままチップ裏面１０の面積の低減につながる訳
で、電気的伝導性の確保は、ますます難しくなる方向で
あり、何らかの対応策が強く求められている。On the other hand, as a general tendency, many attempts have been made to shrink chips from the viewpoint of reduction of development cost and reduction of device cost. Because of the reduction, securing electrical conductivity is becoming increasingly difficult, and some countermeasures are strongly required.

【００１９】[0019]

【発明が解決しようとする課題】以上述べたように、従
来の半導体装置は、パワートランジスタを実装する場合
に、ダイアタッチ材として鉛入りの半田を用いていたの
で、このままでは鉛フリーの動きに対応できず、鉛フリ
ーのダイアタッチ材である銀ペーストを適用しように
も、オーミックコンタクトを確保できずに、使用不可で
あり、一方、チップ面積の縮小という一般的な傾向に対
しても、電気伝導性確保という観点からは、ますます厳
しい条件をクリアする必要があり、何らかの解決策が強
く求められている。As described above, the conventional semiconductor device uses lead-containing solder as a die attach material when mounting a power transistor. It cannot be used and cannot be used to apply silver paste, which is a lead-free die attach material, because it cannot secure an ohmic contact. From the viewpoint of ensuring conductivity, it is necessary to clear increasingly strict conditions, and some solution is strongly required.

【００２０】本発明は、上記のような従来技術の課題を
解決しようとするものであり、鉛フリー化と、ダイ裏面
とダイを搭載するパッドとの電気的導通の確保という課
題に対して、半導体チップをチップ搭載部に取りつける
部分の構造を改善することにより、対応可能とした半導
体装置を提供することを目的とする。The present invention has been made to solve the above-mentioned problems of the prior art, and has been made to solve the problems of lead-free and ensuring electrical conduction between the back surface of the die and the pad on which the die is mounted. It is an object of the present invention to provide a semiconductor device capable of handling by improving the structure of a portion where a semiconductor chip is mounted on a chip mounting portion.

【００２１】[0021]

【課題を解決するための手段】本発明は、第１の面に任
意数の第１の接続端子が形成されこの第１の面と向かい
合う第２の面に面状の第２の接続端子が形成された半導
体チップを、任意数のアウター端子を有しそのアウター
端子の少なくとも１つにおけるチップ搭載部に、電気的
に導通するように導電体を介在させて搭載する半導体装
置において、前記チップ搭載部と前記チップにおける前
記第１又は第２の接続端子とを、前記導電体のまわりに
充填した、鉛を含まない接着材によって接着するように
したことを特徴とするものとして構成される。According to the present invention, an arbitrary number of first connection terminals are formed on a first surface, and a second planar connection terminal is formed on a second surface opposite to the first surface. A semiconductor device comprising a semiconductor chip having an arbitrary number of outer terminals and mounted on a chip mounting portion of at least one of the outer terminals via a conductor so as to be electrically conductive. The portion and the first or second connection terminal of the chip are bonded by a lead-free adhesive filled around the conductor.

【００２２】さらに、本発明は、前記の半導体装置にお
いて、前記半導体チップは、前記第２の面が前記チップ
搭載部に向かい合うように搭載され、前記第２の面にお
ける面状の前記第２の接続端子が前記導電体によって前
記チップ搭載部に電気的に接続されていることを特徴と
するものとして構成される。Further, according to the present invention, in the semiconductor device described above, the semiconductor chip is mounted such that the second surface faces the chip mounting portion, and the second surface having the planar shape on the second surface is provided. A connection terminal is electrically connected to the chip mounting portion by the conductor.

【００２３】または、本発明は、前記の半導体装置にお
いて、前記半導体チップは、主面としての前記第２の面
が前記チップ搭載部に向かい合うように搭載されて、前
記面状の第２の接続端子を有する前記第２の面が外側に
向けられており、さらに前記第１の面における前記第１
の接続端子が前記導電体によって前記チップ搭載部に電
気的に接続されていることを特徴とするものとして構成
される。Alternatively, in the semiconductor device according to the present invention, in the semiconductor device, the semiconductor chip is mounted such that the second surface as a main surface faces the chip mounting portion, and the second planar connection is provided. The second surface having the terminal is directed outward, and the first surface on the first surface is
Are electrically connected to the chip mounting portion by the conductor.

【００２４】[0024]

【発明の実施の形態】以下、図面を参照しながら、本発
明の実施形を説明する。Embodiments of the present invention will be described below with reference to the drawings.

【００２５】実施形１．図１は、本発明の実施形１の半
導体装置の縦断面図であり、特に、図６のＡ−Ａに対応
する線で得た断面図を示すものである。図１において、
（Ｅ）、（Ｃ）、（Ｂ）はそれぞれエミッタ、コレク
タ、ベースに対応する部分を示している。これは、以下
の各図においても同様である。これからわかるように、
チップ主面は上向きとしている。Embodiment 1 FIG. 1 is a longitudinal sectional view of a semiconductor device according to a first embodiment of the present invention, and particularly shows a sectional view taken along a line corresponding to AA in FIG. In FIG.
(E), (C), and (B) show portions corresponding to the emitter, collector, and base, respectively. This is the same in the following drawings. As you can see,
The chip main surface is upward.

【００２６】図において示すように、パワートランジス
タの半導体チップ４をチップ搭載部５に搭載するに当た
り、ダイアタッチ材６を用いるが、この場合、ダイアタ
ッチ材６としては鉛の入っていない銀ペースト等の樹脂
を用いる。この樹脂は、電気的に絶縁であっても導電で
あっても構わない。As shown in the figure, a die attach material 6 is used to mount the semiconductor chip 4 of the power transistor on the chip mounting portion 5. In this case, the die attach material 6 is a lead-free silver paste or the like. Is used. This resin may be electrically insulating or conductive.

【００２７】一方、半導体チップ４とチップ搭載部５の
間には、略９０％以上の成分が単一金属である導電粒子
（導電体）１２を介在させ、この導電粒子１２を半導体
チップ４のチップ裏面１０及びチップ搭載部５の両方に
接触または接合させる。この場合、半導体チップ４をチ
ップ搭載部５に搭載するに当たり、半導体チップ４をチ
ップ搭載部５に向かって押しつけることにより、両者の
導電粒子１２を介しての導通を確保する。On the other hand, between the semiconductor chip 4 and the chip mounting portion 5, conductive particles (conductive material) 12 in which approximately 90% or more of the component is a single metal are interposed. Both the chip back surface 10 and the chip mounting portion 5 are contacted or joined. In this case, when the semiconductor chip 4 is mounted on the chip mounting portion 5, the semiconductor chip 4 is pressed toward the chip mounting portion 5, thereby ensuring conduction between the two via the conductive particles 12.

【００２８】さて、導電粒子１２としては、例えば、Ｎ
ｉでできた金属粒子であっても、樹脂性の粒子の回り
に、導電性のＡｕやＳｎ等の金属をメッキして導電性を
持たせたものであっても良い。As the conductive particles 12, for example, N
Metal particles made of i may be used, or conductive particles may be formed by plating a conductive metal such as Au or Sn around resin particles.

【００２９】また、導電粒子１２は、半導体チップ４を
チップ搭載部５に接着するに当たり、事前に接着面に散
布しても、接着用のダイアタッチ材６に予め混入してお
いても良い。In bonding the semiconductor chip 4 to the chip mounting portion 5, the conductive particles 12 may be sprayed on the bonding surface in advance, or may be mixed in the bonding die attach material 6 in advance.

【００３０】以上述べたような構成により、半導体チッ
プ４とチップ搭載部５の間のオーミックコンタクトは、
導電粒子１２により確保されるので、鉛を用いた半田を
用いることなく電気的導通の良好性を得ることができ
る。With the configuration described above, the ohmic contact between the semiconductor chip 4 and the chip mounting portion 5 is
Since it is secured by the conductive particles 12, good electrical continuity can be obtained without using solder using lead.

【００３１】なお、上記樹脂６として銀ペーストを用い
ることにより、耐衝撃性、耐クラック性を向上させさら
に密着性も向上させ、はがれにくくすることができる。By using a silver paste as the resin 6, the impact resistance and the crack resistance can be improved, the adhesion can be improved, and the resin 6 can be hardly peeled off.

【００３２】実施形２．図２は、本発明の実施形２の半
導体装置の縦断面図であり、特に、図６のＡ−Ａに対応
する線で得た断面図を示すものである。Embodiment 2 FIG. 2 is a longitudinal sectional view of the semiconductor device according to the second embodiment of the present invention, and particularly shows a sectional view taken along a line corresponding to AA in FIG.

【００３３】図において示すように、パワートランジス
タの半導体チップ４をチップ搭載部５に搭載するに当た
り、ダイアタッチ材６を用いるが、この場合、ダイアタ
ッチ材６としては鉛の入っていない樹脂を用いる。この
樹脂は、電気的に絶縁であっても導電であっても構わな
い。As shown in the figure, a die attach material 6 is used to mount the semiconductor chip 4 of the power transistor on the chip mounting portion 5. In this case, a resin containing no lead is used as the die attach material 6. . This resin may be electrically insulating or conductive.

【００３４】一方、半導体チップ４とチップ搭載部５の
間には、スタッドバンプ１３が介在するが、これはチッ
プ搭載部５の上にＡｕやＳｎなどのボンディングワイア
９と同じ材料で形成される。On the other hand, a stud bump 13 is interposed between the semiconductor chip 4 and the chip mounting portion 5 and is formed on the chip mounting portion 5 with the same material as the bonding wire 9 such as Au or Sn. .

【００３５】つまり、半導体チップ４をチップ搭載部５
の上に搭載するに先立ち、チップ搭載部５の上に、ボン
ディングワイア９を使ってスタッドバンプ１３を形成す
る。その後、ダイアタッチ材６を転写し、続いて半導体
チップ４をチップ搭載部５の上に搭載し、半導体チップ
４をスタッドバンプ１３に押しつけることにより、チッ
プ裏面１０とスタッドバンプ（導電体）１３を接触させ
る。結果として、半導体チップ４とチップ搭載部５の間
の導通を確保する。That is, the semiconductor chip 4 is mounted on the chip mounting portion 5.
Prior to mounting on the chip mounting portion 5, the stud bump 13 is formed on the chip mounting portion 5 using the bonding wire 9. After that, the die attach material 6 is transferred, and then the semiconductor chip 4 is mounted on the chip mounting portion 5, and the semiconductor chip 4 is pressed against the stud bumps 13 so that the chip back surface 10 and the stud bumps (conductors) 13 are formed. Make contact. As a result, conduction between the semiconductor chip 4 and the chip mounting portion 5 is ensured.

【００３６】なお、スタッドバンプ１３は、ボンディン
グワイア９と同じ材料でなくても、別材料の表面に、Ａ
ｕやＳｎなどの良導体をメッキすることで形成するよう
にしても良い。The stud bumps 13 may be formed on the surface of another material even if they are not made of the same material as the bonding wires 9.
It may be formed by plating a good conductor such as u or Sn.

【００３７】更に、スタッドバンプ１３は、チップ搭載
部５の表面ではなく、半導体チップ４側に設けるように
してもよい。Further, the stud bumps 13 may be provided not on the surface of the chip mounting portion 5 but on the semiconductor chip 4 side.

【００３８】以上述べたような構成により、半導体チッ
プ４とチップ搭載部５の間のオーミックコンタクトは、
スタッドバンプ１３により確保されるので、鉛を用いた
半田を用いることなく電気的導通の良好性を得ることが
できる。With the configuration described above, the ohmic contact between the semiconductor chip 4 and the chip mounting portion 5 is
Since it is ensured by the stud bumps 13, good electrical continuity can be obtained without using solder using lead.

【００３９】実施形３．図３は、本発明の実施形２の半
導体装置の縦断面図であり、特に、図６のＡ−Ａに対応
する線で得た断面図を示すものである。Embodiment 3 FIG. 3 is a longitudinal sectional view of the semiconductor device according to the second embodiment of the present invention, and particularly shows a sectional view taken along a line corresponding to AA in FIG.

【００４０】図において示すように、パワートランジス
タの半導体チップ４をチップ搭載部５に搭載するに当た
り、ダイアタッチ材６を用いるが、この場合、ダイアタ
ッチ材６としては鉛の入っていない樹脂を用いる。この
樹脂は、電気的に絶縁であっても導電であっても構わな
い。As shown in the figure, a die attach material 6 is used for mounting the power transistor semiconductor chip 4 on the chip mounting portion 5. In this case, a resin containing no lead is used as the die attach material 6. . This resin may be electrically insulating or conductive.

【００４１】一方、半導体チップ４とチップ搭載部５の
間には、リードフレーム突起１４が存在するが、これは
チップ搭載部５の上に予めＡｕやＳｎなどをメッキする
か、チップ搭載部５の形成時にパターンニングするなど
して形成する。On the other hand, there is a lead frame projection 14 between the semiconductor chip 4 and the chip mounting portion 5, which is formed by plating Au or Sn on the chip mounting portion 5 in advance, or It is formed by patterning at the time of forming.

【００４２】以上のような構成において、半導体チップ
４をチップ搭載部５の上に搭載するに当たり、半導体チ
ップ４をスタッドバンプ１３に押しつけることにより、
チップ裏面１０とリードフレーム突起（導電体）１４を
接触させ、半導体チップ４とチップ搭載部５の間の電気
的導通を確保する。In the above configuration, when the semiconductor chip 4 is mounted on the chip mounting portion 5, the semiconductor chip 4 is pressed against the stud bump 13,
The chip back surface 10 and the lead frame protrusions (conductors) 14 are brought into contact with each other to ensure electrical conduction between the semiconductor chip 4 and the chip mounting portion 5.

【００４３】以上述べたような構成により、半導体チッ
プ４とチップ搭載部５の間のオーミックコンタクトは、
リードフレーム突起１４により確保されるので、鉛を用
いた半田を用いることなく電気的導通の良好性を得るこ
とができる。With the configuration described above, the ohmic contact between the semiconductor chip 4 and the chip mounting portion 5 is
Since it is secured by the lead frame projections 14, good electrical continuity can be obtained without using solder using lead.

【００４４】実施形４．さて、図４は、本発明の実施形
４の半導体装置の内部構造を示す図であり、特に、図６
のような外観構造の正面から見た透視図を示すものであ
る。また、図５は、本実施形の半導体装置の縦断面図で
あり、特に、図６のＢ−Ｂに対応する線で得た断面図を
示すものである。Embodiment 4 FIG. 4 is a diagram showing the internal structure of the semiconductor device according to the fourth embodiment of the present invention.
FIG. 2 is a perspective view of the external structure as viewed from the front. FIG. 5 is a longitudinal sectional view of the semiconductor device of the present embodiment, and particularly shows a sectional view taken along a line corresponding to BB in FIG.

【００４５】この例では、半導体チップ４を、これまで
の例（図１〜図３）とは上下を反転している。つまり、
チップ主面を下向きとしている。In this example, the semiconductor chip 4 is turned upside down from the previous examples (FIGS. 1 to 3). That is,
The chip main surface faces downward.

【００４６】図において示すように、半導体チップ４
は、ボンディングパッド７を有しているが、これらのボ
ンディングパッド７は、パワートランジスタのエミッ
タ、ベースに対応して、Ｖ／Ｎｉ／Ａｕ層をメッキまた
は蒸着することにより形成されている。一方、パワート
ランジスタのコレクタとしてのいわゆるチップ裏面１０
は、図５では表側に向けられている。As shown in FIG.
Has a bonding pad 7, which is formed by plating or depositing a V / Ni / Au layer corresponding to the emitter and base of the power transistor. On the other hand, a so-called chip back surface 10 as a collector of a power transistor
Are turned to the front side in FIG.

【００４７】エミッタ、ベースに対応する端子１、３と
一体に形成されるリードフレームの一部は、チップ搭載
部５として、それぞれ対応するボンディングパッド７に
対面している。A part of the lead frame formed integrally with the terminals 1 and 3 corresponding to the emitter and the base faces the corresponding bonding pad 7 as the chip mounting portion 5.

【００４８】半導体チップ４をチップ搭載部５に搭載す
るに当たり、ボンディングパッド７とチップ搭載部５の
間に、バンプ１５を介在させ、半導体チップ４をチップ
搭載部５に向かって押しつけることにより、導電体を構
成するボンディングパッド７とバンプ１５によりチップ
搭載部５とチップ４との間の導通を確保する。When the semiconductor chip 4 is mounted on the chip mounting portion 5, the semiconductor chip 4 is pressed toward the chip mounting portion 5 by interposing a bump 15 between the bonding pad 7 and the chip mounting portion 5, thereby providing a conductive material. The conduction between the chip mounting portion 5 and the chip 4 is ensured by the bonding pads 7 and the bumps 15 constituting the body.

【００４９】なお、バンプ１５は、チップ搭載部５上に
予め形成させておいても良い。The bumps 15 may be formed on the chip mounting portion 5 in advance.

【００５０】なお、この場合、半導体チップ４とチップ
搭載部５の間に、ボンディングパッド７やバンプ１５に
相当する分の隙間ができるが、この隙間に樹脂により形
成されたダイアタッチ材６の層を介在させる。In this case, a gap corresponding to the bonding pads 7 and the bumps 15 is formed between the semiconductor chip 4 and the chip mounting portion 5. In this gap, a layer of the die attach material 6 formed of resin is formed. Intervene.

【００５１】ちなみに、ダイアタッチ材６の層は、リー
ドフレームのチップ搭載部５の上に予めダイアタッチ材
６を転写しておき、半導体チップ４を搭載した後に、加
熱、加圧して、形成する。Incidentally, the layer of the die attach material 6 is formed by transferring the die attach material 6 on the chip mounting portion 5 of the lead frame in advance, mounting the semiconductor chip 4, and then applying heat and pressure. .

【００５２】ダイアタッチ材としては、熱可塑性のもの
と熱硬化性のものがある。また、性状が固体状（シート
状）のものと、液状のものに分かれる。熱可塑性シート
状の場合はポリエーテルアミドイミドがよく使われる。
熱硬化性のものは、ビスフェールＡ型、ビスフェールＦ
型、ナフタレン型などのエポキシ樹脂、フェノール樹脂
やアクリル系樹脂を主成分とする。主成分以外に、フィ
ラを含有している場合もある。フィラはシリカ（ＳｉＯ
2）、アルミナ（Ａｌ2Ｏ3）、窒化ホウ酸（ＢＮ）など
の無機物が一般的であり、剛性、熱伝導性など必要特性
に合せ充填量を変える。もちろん、ニッケル、金、銀な
どの金属粒子、プラスチックをコアにして表面をニッケ
ルめっきしたものも使うことができる。As the die attach material, there are a thermoplastic material and a thermosetting material. Further, properties are divided into a solid (sheet) and a liquid. In the case of a thermoplastic sheet, polyetheramideimide is often used.
Thermosetting materials include Bispher A type and Bispher F
The main component is an epoxy resin such as a mold or a naphthalene type, a phenol resin or an acrylic resin. In some cases, a filler is contained in addition to the main component. The filler is silica (SiO
2 ) Inorganic substances such as alumina (Al 2 O 3 ) and boric acid nitride (BN) are generally used, and the filling amount is changed according to required characteristics such as rigidity and thermal conductivity. Of course, metal particles such as nickel, gold, silver, and the like, and a plastic whose core is plated with nickel can also be used.

【００５３】しかる後に、ボンディングワイア９を用い
て、半導体チップ４の表面と、端子２と一体になったリ
ードフレームを接続する。つまり、この例では、コレク
タに対応するチップ裏面１０をそのままでチップの端子
として表向きとして用いており、これも一つの特徴とし
ているのである。After that, the surface of the semiconductor chip 4 is connected to the lead frame integrated with the terminal 2 by using the bonding wire 9. That is, in this example, the chip back surface 10 corresponding to the collector is used as it is as a terminal of the chip face up as it is, which is also a feature.

【００５４】なお、ダイアタッチ材６としては、先の実
施形と同様、鉛の入っていない樹脂を用いる。この樹脂
は、電気的に絶縁であっても導電であっても構わない。As the die attach material 6, a resin containing no lead is used as in the previous embodiment. This resin may be electrically insulating or conductive.

【００５５】以上述べたような構成により、半導体チッ
プ４とチップ搭載部５の間のオーミックコンタクトは、
バンプ１５により確保されるので、鉛を用いた半田を用
いることなく電気的導通の良好性を得ることができる。With the configuration described above, the ohmic contact between the semiconductor chip 4 and the chip mounting portion 5 is
Since it is secured by the bumps 15, good electrical continuity can be obtained without using solder using lead.

【００５６】なお、この実施形４の変形として、バンプ
１５を用いる代わりに、実施形１で例示した導電粒子１
２や、実施形３で例示したリードフレーム突起１４を適
用しても同様の効果を得られることは言うまでもない。As a modification of the fourth embodiment, the conductive particles 1 illustrated in the first embodiment are replaced with the bumps 15.
It is needless to say that the same effect can be obtained by applying the lead frame protrusion 14 exemplified in the second embodiment or the third embodiment.

【００５７】[0057]

【発明の効果】以上述べたように、本発明の半導体装置
は、半導体チップをリードフレーム上のチップ搭載部に
接着する接着材（ダイアタッチ材）としては、鉛を含ま
ない材料を用いたので、半導体チップとチップ搭載部の
間の電気的な導通が、鉛フリーを実現しながら、実現す
ることが可能になるという効果がある。As described above, the semiconductor device of the present invention uses a lead-free material as an adhesive (die attach material) for bonding a semiconductor chip to a chip mounting portion on a lead frame. This has the effect that electrical continuity between the semiconductor chip and the chip mounting portion can be realized while realizing lead-free.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施形１の半導体装置の縦断面図であ
る。FIG. 1 is a vertical sectional view of a semiconductor device according to a first embodiment of the present invention.

【図２】本発明の実施形２の半導体装置の縦断面図であ
る。FIG. 2 is a longitudinal sectional view of a semiconductor device according to a second embodiment of the present invention.

【図３】本発明の実施形３の半導体装置の縦断面図であ
る。FIG. 3 is a longitudinal sectional view of a semiconductor device according to a third embodiment of the present invention.

【図４】本発明の実施形４の半導体装置の内部構造を示
す透視図である。FIG. 4 is a perspective view showing an internal structure of a semiconductor device according to a fourth embodiment of the present invention.

【図５】本発明の実施形４の半導体装置の縦断面図であ
る。FIG. 5 is a longitudinal sectional view of a semiconductor device according to a fourth embodiment of the present invention.

【図６】一般的なパワートランジスタを構成する半導体
装置の正面図である。FIG. 6 is a front view of a semiconductor device forming a general power transistor.

【図７】従来の半導体装置の内部構造を示す透視図であ
る。FIG. 7 is a perspective view showing the internal structure of a conventional semiconductor device.

【図８】従来の半導体装置の縦断面図である。FIG. 8 is a longitudinal sectional view of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１、２、３ 端子 ４ 半導体チップ ５ チップ搭載部 ６ ダイアタッチ材 ７ ボンディングパッド ８ ボンディングポスト ９ ボンディングワイア １０ チップ裏面 １１ モールド樹脂 １２ 導電粒子 １３ スタッドバンプ １４ リードフレーム突起 １５ バンプ 1, 2, 3 terminals 4 Semiconductor chip 5 Chip mounting part 6 Die attach material 7 Bonding pad 8 Bonding post 9 Bonding wire 10 Chip back surface 11 Mold resin 12 Conductive particles 13 Stud bump 14 Lead frame protrusion 15 Bump

───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 5F044 AA00 KK05 KK16 KK18 KK19 LL07 LL13 QQ07  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F044 AA00 KK05 KK16 KK18 KK19 LL07 LL13 QQ07

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】第１の面に任意数の第１の接続端子が形成
されこの第１の面と向かい合う第２の面に面状の第２の
接続端子が形成された半導体チップを、任意数のアウタ
ー端子を有しそのアウター端子の少なくとも１つにおけ
るチップ搭載部に、電気的に導通するように導電体を介
在させて搭載する半導体装置において、 前記チップ搭載部と前記チップにおける前記第１又は第
２の接続端子とを、前記導電体のまわりに充填した、鉛
を含まない接着材によって接着するようにしたことを特
徴とする半導体装置。1. A semiconductor chip in which an arbitrary number of first connection terminals are formed on a first surface and a planar second connection terminal is formed on a second surface opposite to the first surface. A semiconductor device having a number of outer terminals and mounted on a chip mounting portion of at least one of the outer terminals via a conductor so as to be electrically conductive, wherein the chip mounting portion and the first of the chip Alternatively, the semiconductor device is characterized in that the second connection terminal and the second connection terminal are bonded by a lead-free adhesive filled around the conductor. 【請求項２】前記半導体チップは、前記第２の面が前記
チップ搭載部に向かい合うように搭載され、前記第２の
面における面状の前記第２の接続端子が前記導電体によ
って前記チップ搭載部に電気的に接続されていることを
特徴とする請求項１に記載の半導体装置。2. The semiconductor chip is mounted such that the second surface faces the chip mounting portion, and the planar second connection terminals on the second surface are mounted on the chip by the conductor. The semiconductor device according to claim 1, wherein the semiconductor device is electrically connected to the unit. 【請求項３】前記半導体チップは、主面としての前記第
２の面が前記チップ搭載部に向かい合うように搭載され
て、前記面状の第２の接続端子を有する前記第２の面が
外側に向けられており、さらに前記第１の面における前
記第１の接続端子が前記導電体によって前記チップ搭載
部に電気的に接続されていることを特徴とする請求項１
に記載の半導体装置。3. The semiconductor chip is mounted such that the second surface as a main surface faces the chip mounting portion, and the second surface having the planar second connection terminals is located outside. The first connection terminal on the first surface is further electrically connected to the chip mounting portion by the conductor.
3. The semiconductor device according to claim 1.
JP2000281212A 2000-09-18 2000-09-18 Semiconductor device Pending JP2002093855A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000281212A JP2002093855A (en) 2000-09-18 2000-09-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000281212A JP2002093855A (en) 2000-09-18 2000-09-18 Semiconductor device

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Publication Number Publication Date
JP2002093855A true JP2002093855A (en) 2002-03-29

Family

ID=18765902

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000281212A Pending JP2002093855A (en) 2000-09-18 2000-09-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2002093855A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014040661A (en) * 2006-07-21 2014-03-06 Valtion Teknillinen Tutkimuskeskus Method for manufacturing conductor and semiconductor
JP2017143134A (en) * 2016-02-09 2017-08-17 株式会社東芝 Method for manufacturing semiconductor device and semiconductor device
JPWO2020175619A1 (en) * 2019-02-28 2021-12-16 京セラ株式会社 Package for mounting electronic components, electronic devices and light emitting devices

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JPH1197463A (en) * 1997-09-22 1999-04-09 Hitachi Ltd Pressure joint semiconductor device
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Publication number Priority date Publication date Assignee Title
JPH02146757A (en) * 1988-11-28 1990-06-05 Mitsubishi Electric Corp Semiconductor device
JPH03149864A (en) * 1989-11-07 1991-06-26 Matsushita Electron Corp Lead frame
JPH10118783A (en) * 1996-10-17 1998-05-12 Matsushita Electric Ind Co Ltd Soldering material, and electronic parts using it
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JPH10233406A (en) * 1997-02-19 1998-09-02 Rohm Co Ltd Bonding device of ic chip
JPH1192736A (en) * 1997-09-22 1999-04-06 Sumitomo Bakelite Co Ltd Conductive resin paste and semiconductor device prepared by using same
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014040661A (en) * 2006-07-21 2014-03-06 Valtion Teknillinen Tutkimuskeskus Method for manufacturing conductor and semiconductor
US9011762B2 (en) 2006-07-21 2015-04-21 Valtion Teknillinen Tutkimuskeskus Method for manufacturing conductors and semiconductors
JP2017143134A (en) * 2016-02-09 2017-08-17 株式会社東芝 Method for manufacturing semiconductor device and semiconductor device
JPWO2020175619A1 (en) * 2019-02-28 2021-12-16 京セラ株式会社 Package for mounting electronic components, electronic devices and light emitting devices

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