JPS5847705Y2 - Dai Collection - Google Patents
Dai CollectionInfo
- Publication number
- JPS5847705Y2 JPS5847705Y2 JP1979051616U JP5161679U JPS5847705Y2 JP S5847705 Y2 JPS5847705 Y2 JP S5847705Y2 JP 1979051616 U JP1979051616 U JP 1979051616U JP 5161679 U JP5161679 U JP 5161679U JP S5847705 Y2 JPS5847705 Y2 JP S5847705Y2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- receiving space
- processed
- die collet
- protrusions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
Description
【考案の詳細な説明】
本考案は半導体素子（チップ）等を、ステム、リードフ
レーム、または回路基板等に搭載固着する際に用いるダ
イ・コレットの改良に関する。[Detailed Description of the Invention] The present invention relates to an improvement of a die collet used for mounting and fixing semiconductor elements (chips) etc. on stems, lead frames, circuit boards, etc.
近年半導体チップ等の電子部品を、ステム、リードフレ
ーム、または回路基板等に搭載固着する際に、粉末状の
半田にフラックスが均質に混合されたいわゆるクリーム
半田がしばしば使われている。In recent years, when mounting and fixing electronic components such as semiconductor chips on stems, lead frames, circuit boards, etc., so-called cream solder, which is a homogeneous mixture of powdered solder and flux, is often used.
それには従来第１図に示すように、四角錐台形の半導体
チップ受容空間を有するダイ・コレット１を用いて半導
体チップ２を真空吸引しつつ、該半導体チップ２をステ
ム３等の上に塗布され加熱溶融せしめられたクリーム半
田４上に押しつけ、ダイ・コレットを前後及び／または
左右に移動させて半導体チップをスライドさせることに
より、クリーム半田の半田がフラックスと共に薄い層に
押し延ばされて半田層４を所定の厚さにすると共に、フ
ラックスが気化したガスを大気中に放出して前記半田層
中にボイドが発生することを防止する半導体チップの固
着方法が用いられている。Conventionally, as shown in FIG. 1, a die collet 1 having a truncated quadrangular pyramid-shaped semiconductor chip receiving space is used to vacuum-suction the semiconductor chip 2, and apply the semiconductor chip 2 onto a stem 3, etc. By pressing the semiconductor chip onto the heated and melted cream solder 4 and moving the die collet back and forth and/or left and right to slide the semiconductor chip, the solder of the cream solder is stretched together with flux into a thin layer, forming a solder layer. A semiconductor chip fixing method is used in which the solder layer 4 is made to have a predetermined thickness, and the vaporized flux is released into the atmosphere to prevent voids from being generated in the solder layer.
なお、同図において、１′は真空吸引用孔である。In addition, in the figure, 1' is a vacuum suction hole.
このような従来の固着方法は、半田層の厚さを薄くし且
つボイドの発生は防止できるが、かかる固着処理の際、
フラックスの一部が半導体チップ表面に這い上りチップ
表面に付着するという問題がある。Such conventional fixing methods can reduce the thickness of the solder layer and prevent the generation of voids, but during the fixing process,
There is a problem in that some of the flux creeps up onto the surface of the semiconductor chip and adheres to the surface of the chip.
つまり第１図において、例えば゛ダイ・コレット１を図
の左方向へ動かすとチップの右肩の部分はダイ・コレッ
ト１の内壁に密着するが、左肩の部分とダイ・コレット
の壁面との間に僅かな隙間ができる。In other words, in Fig. 1, for example, if the die collet 1 is moved to the left in the figure, the right shoulder part of the chip comes into close contact with the inner wall of the die collet 1, but there is a gap between the left shoulder part and the wall surface of the die collet. There will be a slight gap between.
そのため毛細管現象によりフラックスが上記隙間を這い
上り、第２図に示すように該半導体チツブ２表面に付着
する。Therefore, the flux creeps up through the gap due to capillarity and adheres to the surface of the semiconductor chip 2 as shown in FIG.
半導体チップ２表面に形成された電極５にフラックス６
が付着すると該電極５にアルミニウム線等をボンディン
グしようとしても十分な接着強度が得られず、製造歩留
や信頼度が低下するという問題を生じる。Flux 6 is applied to the electrode 5 formed on the surface of the semiconductor chip 2.
If this adheres, even if an aluminum wire or the like is bonded to the electrode 5, sufficient adhesive strength cannot be obtained, resulting in a problem that manufacturing yield and reliability are lowered.
本考案はかかる問題点を解消して、フラックスが電極等
要部に付着することを防止し得るダイ・コレットの構造
を提供することを目的とする。It is an object of the present invention to provide a structure of a die/collet which can solve such problems and prevent flux from adhering to important parts such as electrodes.
このため本考案によれば、多角錐台形の素子受容空間を
有し、前記素子受容空間は天井面と天井面から下方に突
出して配設された突起の内壁面とからなり、該突起の内
壁面は天井面より下方に行くに従って外側に拡がる傾斜
面とされ、且つ被処理素子の上面の各辺に少なくとも１
個所当接するよう配設されてなるダイ・コレットが提供
される。Therefore, according to the present invention, there is provided an element receiving space in the shape of a truncated polygonal pyramid, and the element receiving space is made up of a ceiling surface and an inner wall surface of a protrusion disposed to protrude downward from the ceiling surface. The wall surface is an inclined surface that expands outward as it goes downward from the ceiling surface, and at least one wall surface is formed on each side of the upper surface of the device to be processed.
A die collet is provided that is arranged to abut in locations.
以下本考案の一実施例を図面に基いて説明する。An embodiment of the present invention will be described below with reference to the drawings.
第３図は本考案のダイ・コレットの一実施例の構成を被
処理素子との関連で説明するための要部分解斜視図であ
る。FIG. 3 is an exploded perspective view of essential parts for explaining the structure of one embodiment of the die collet of the present invention in relation to the device to be processed.
図面において１は本考案にかかるダイ・コレット、２は
被処理素子の半導体チップ、３はステム、４はクリーム
半田で゛ある。In the drawings, 1 is a die collet according to the present invention, 2 is a semiconductor chip of an element to be processed, 3 is a stem, and 4 is cream solder.
ダイ・コレット１は天井面７と、該天井面７から下方に
突出して配設された複数個の突起８を有する。The die collet 1 has a ceiling surface 7 and a plurality of protrusions 8 arranged to protrude downward from the ceiling surface 7.
該突起８の内壁面９は天井面７から下に行くに従って、
外側に傾斜し、該内壁面９と天井面７との４個の交線に
より形成される多角形１０即ち本実施例では一点鎖線で
囲まれた長方形１０と、前記内壁面９の横方向への延長
面１１即ち二点鎖線と一点鎖線で囲まれた傾斜した台形
面１１により多角錐台形（本実施例では四角錐台形）の
素子受容空間を構成する。As the inner wall surface 9 of the projection 8 goes downward from the ceiling surface 7,
A polygon 10 that is inclined outward and is formed by four lines of intersection between the inner wall surface 9 and the ceiling surface 7, that is, a rectangle 10 surrounded by a dashed line in this embodiment, and The extended surface 11, that is, the inclined trapezoidal surface 11 surrounded by the two-dot chain line and the one-dot chain line constitutes a polygonal truncated pyramid (in this embodiment, a quadrangular truncated pyramid) element receiving space.
該素子受容空間の各壁面１１に突起８を少なくとも１個
設け、該突起８の内壁面９は前述のごとく傾斜面をなし
、被処理素子２の上面の各辺に当接し、その位置は被処
理素子の上面のフラックスが付着しても差支えない部分
、例えば半導体チップ２上面の電極の近傍を避け、図示
の矢印１３で示した部分に当接するよう選択する。At least one protrusion 8 is provided on each wall surface 11 of the element receiving space, and the inner wall surface 9 of the protrusion 8 forms an inclined surface as described above, contacts each side of the upper surface of the element to be processed 2, and its position is determined by the surface of the target element 2. Avoid areas on the upper surface of the processing element where flux may adhere, for example, the vicinity of the electrodes on the upper surface of the semiconductor chip 2, and select the area indicated by the arrow 13 in the figure to contact.
前記突起８を本実施例では、四つの壁面１１のうち一つ
の面には２個設けであるが、これの目的は被処理素子２
の固着処理の際に被処理素子２が回転するのを防止して
、所定の位置に正確に固着せしめるためである。In this embodiment, two protrusions 8 are provided on one of the four wall surfaces 11, but the purpose of these protrusions is to
This is to prevent the to-be-processed element 2 from rotating during the fixing process and to accurately fix it in a predetermined position.
次に上述のダイ・コレットを用いて半導体チップをステ
ム上に固着する方法について説明し、その効果を明らか
にする。Next, a method for fixing a semiconductor chip onto a stem using the above-mentioned die collet will be explained, and its effects will be clarified.
第４図に示すようにまずステム３上にクリーム半田４を
塗布し、その上に半導体チップ２を載置する。As shown in FIG. 4, cream solder 4 is first applied onto the stem 3, and the semiconductor chip 2 is placed on top of it.
これを所定の温度に設定された加熱装置（図示せず）を
通過させる等の方法により加熱し、半田が溶融した状態
にして、前記半導体チップ２をダイ・コレット１の突起
８の内壁面９で押しつけながら半導体チップ２を前後及
び／または左右にスライドさせてクリーム半田４を押し
延ばす。This is heated by a method such as passing through a heating device (not shown) set at a predetermined temperature, and the solder is melted, and the semiconductor chip 2 is attached to the inner wall surface 9 of the protrusion 8 of the die collet 1. The cream solder 4 is pushed out by sliding the semiconductor chip 2 back and forth and/or left and right while pressing it with the .
このような固着処理により半導体チップ２とステム３の
間には、ボンドのない薄い半田層が形成される。Through this fixing process, a thin solder layer with no bond is formed between the semiconductor chip 2 and the stem 3.
半田層を所望の厚さに形成するには、ステム３上に塗布
するクリーム半田の量と、半田を押し延ばす範囲即ち半
導体チップをスライドさせる長さを調節すればよい。In order to form the solder layer to a desired thickness, the amount of cream solder applied to the stem 3 and the range over which the solder is stretched, that is, the length over which the semiconductor chip is slid, may be adjusted.
上記工程中、クリーム半田に含まれているフラックスは
前述のごとく半導体チップ２の側面と、ダイ・コレット
１の突起８の内壁面９との隙間から半導体チップ２の表
面に這い上がるが、前記突起８は半導体チップ２表面に
おいてフラックスが付着してはならない部分、例えば電
極１２等の近傍を避けて設けであるので、電極１２等は
清浄なよ・保たれる。During the above process, the flux contained in the cream solder creeps up to the surface of the semiconductor chip 2 through the gap between the side surface of the semiconductor chip 2 and the inner wall surface 9 of the protrusion 8 of the die collet 1, as described above. 8 is provided to avoid areas on the surface of the semiconductor chip 2 where flux should not be attached, such as the vicinity of the electrodes 12, etc., so that the electrodes 12 etc. can be kept clean.
本考案は更に種々変形して実施できる。The present invention can be further modified and implemented in various ways.
例えば突起８の大きさは、位置、数は前述の説明より明
らかなごとく、被処理素子との関連により適宜選択して
よい。For example, the size, position, and number of the protrusions 8 may be appropriately selected in relation to the device to be processed, as is clear from the above description.
また、素子受容空間の形状も被処理素子の形状に合せて
四角錐台形、六角錐台形等種々選択し得る。Further, the shape of the element receiving space can be selected from various shapes such as a truncated quadrangular pyramid and a truncated hexagonal pyramid depending on the shape of the element to be processed.
更に、前記一実施例では、ダイ・コレットに素子受容空
間を１個形成した場合について説明したが、本考案を用
いて例えば混成集積回路等において回路基板上に半導体
チップ及び他の電子部品等を複数個同時に固着処理する
ために、一枚の天井板に素子受容空間を複数個形成した
ダイ・コレットを製作することもできる。Furthermore, in the above embodiment, a case was explained in which one element receiving space was formed in the die collet, but the present invention can be used to place semiconductor chips and other electronic components on a circuit board in, for example, a hybrid integrated circuit. In order to fix a plurality of elements at the same time, it is also possible to manufacture a die collet in which a plurality of element receiving spaces are formed in one ceiling plate.
また前記一実施例では半導体チップを半田で固着処理す
る例について説明したが、本考案のダイ・コレットは、
例えば半導体チップを金・シリコンの共晶を利用して固
着処理を行う所謂ダイ・ポンチ゛イングに用いても金の
電極への付着を防止するのに有効である。Furthermore, in the above embodiment, an example was explained in which a semiconductor chip is fixed with solder, but the die collet of the present invention
For example, it is effective to prevent gold from adhering to electrodes by using so-called die punching, which fixes semiconductor chips using gold-silicon eutectic.
以上説明したごとく本考案によれば、例えば半導体チッ
プ等の素子をステム、リードフレーム、または回路基板
等に半田付は等の方法により搭載固着処理する際に、フ
ラックス等が該素子の表面に這い上がり電極等に付着す
ることがなく、アルミニウム線等のリードのボンディン
グに悪影響を及は゛すことがなくなり、製造歩留及び信
頼性を向上させることができる。As explained above, according to the present invention, when an element such as a semiconductor chip is mounted and fixed on a stem, lead frame, circuit board, etc. by a method such as soldering, flux etc. creep onto the surface of the element. It does not adhere to rising electrodes, etc., and does not adversely affect the bonding of leads such as aluminum wires, thereby improving manufacturing yield and reliability.
【図面の簡単な説明】
第１図及び第２図は従来構造のダイ・コレットを用いて
の素子の基板への搭載固着の状態を示す断面図及び平面
図、第３図は本考案のダイ・コレットの構造を示す要部
斜視図、第４図は本考案のダイ・コレットによる素子の
基板への固着法を示す要部正面図である。
図において １はダイ・コレット、２は被処理素子、７
は天井面、８は突起、９は突起の内壁面、１０は素子受
容空間天井面、１１は素子受容空間内壁、１２は電極。[Brief Description of the Drawings] Figures 1 and 2 are a cross-sectional view and a plan view showing how an element is mounted and fixed on a substrate using a die collet of the conventional structure, and Figure 3 is a die collet of the present invention. - A perspective view of the main part showing the structure of the collet, and FIG. 4 is a front view of the main part showing the method of fixing the element to the substrate using the die collet of the present invention. In the figure, 1 is the die collet, 2 is the device to be processed, and 7
8 is a ceiling surface, 8 is a protrusion, 9 is an inner wall surface of the protrusion, 10 is an element receiving space ceiling surface, 11 is an inner wall of the element receiving space, and 12 is an electrode.
Claims (1)
多角錐台形の素子受容空間を有し、前記素子受容空間が
天井面と該天井面から下方に向って突出して配設された
複数個の突起の内壁面とにより構成されてなるダイ・コ
レットにおいて、該突起は、被処理素子表面に設けられ
る電極近傍を避けて前記素子受容空間天井面の各辺に配
設され、かつ該辺のうちの１つには少なくとも２個配設
され、該突起の内壁面は被処理素子上面の各辺に当接し
、かつ天井面から下方に行くに従って外側に拡がる傾斜
面とされてなることを特徴とするダイ・コレット。A truncated polygonal pyramid-shaped element receiving space corresponding to the shape of the element to be processed whose surface is provided with electrodes, etc., and the element receiving space is a ceiling surface and a plurality of elements arranged so as to protrude downward from the ceiling surface. In the die collet, the protrusions are arranged on each side of the ceiling surface of the element receiving space, avoiding the vicinity of the electrodes provided on the surface of the element to be processed, and One of the protrusions is provided with at least two protrusions, and the inner wall surface of the protrusion is in contact with each side of the upper surface of the device to be processed, and is an inclined surface that widens outward as it goes downward from the ceiling surface. Dai Colette.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1979051616U JPS5847705Y2 (en) | 1979-04-18 | 1979-04-18 | Dai Collection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1979051616U JPS5847705Y2 (en) | 1979-04-18 | 1979-04-18 | Dai Collection |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55152048U JPS55152048U (en) | 1980-11-01 |
| JPS5847705Y2 true JPS5847705Y2 (en) | 1983-10-31 |
Family
ID=28941296
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1979051616U Expired JPS5847705Y2 (en) | 1979-04-18 | 1979-04-18 | Dai Collection |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5847705Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52156558A (en) * | 1976-06-23 | 1977-12-27 | Hitachi Ltd | Collet for die bonding |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5653548Y2 (en) * | 1977-06-09 | 1981-12-14 |
-
1979
- 1979-04-18 JP JP1979051616U patent/JPS5847705Y2/en not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52156558A (en) * | 1976-06-23 | 1977-12-27 | Hitachi Ltd | Collet for die bonding |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55152048U (en) | 1980-11-01 |
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