JP3052615B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

Info

Publication number
JP3052615B2
JP3052615B2 JP4294822A JP29482292A JP3052615B2 JP 3052615 B2 JP3052615 B2 JP 3052615B2 JP 4294822 A JP4294822 A JP 4294822A JP 29482292 A JP29482292 A JP 29482292A JP 3052615 B2 JP3052615 B2 JP 3052615B2
Authority
JP
Japan
Prior art keywords
electrode
insulating film
semiconductor element
wiring board
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP4294822A
Other languages
Japanese (ja)
Other versions
JPH06151505A (en
Inventor
眞司 梅田
博昭 藤本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP4294822A priority Critical patent/JP3052615B2/en
Publication of JPH06151505A publication Critical patent/JPH06151505A/en
Application granted granted Critical
Publication of JP3052615B2 publication Critical patent/JP3052615B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81897—Mechanical interlocking, e.g. anchoring, hook and loop-type fastening or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は半導体装置、特に多端
子、狭ピッチのＩＣ，ＬＳＩのパッケージング構造およ
びその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a packaging structure of a multi-terminal, narrow-pitch IC or LSI and a method of manufacturing the same.

【０００２】[0002]

【従来の技術】従来の技術を（図４）、（図５）によっ
て説明する。2. Description of the Related Art A conventional technique will be described with reference to FIGS.

【０００３】まず、（図４（ａ））に示すようにセラミ
ック、ガラス、ガラスエポキシ、シリコン等よりなる配
線基板１の基板配線２を有する面に、接着用の絶縁性樹
脂３を塗布する。基板配線２はＡｌ、Ｃｕ、Ｃｒ−Ａｕ
等であり、スパッタリング法、蒸着法により基板配線用
金属を形成した後、フォトリソグラフィー技術により基
板配線用金属をエッチングして形成するか、または、印
刷技術を用いて形成する。絶縁性樹脂３は、紫外線硬化
型または熱硬化型のエポキシ、シリコーン、アクリル等
の樹脂である。次に、（図４（ｂ））に示すように半導
体素子５の突起電極４を基板配線３と一致させ、半導体
素子５の裏面側から、突起電極４を基板配線２に押し当
てるように加圧する。次に、半導体素子５を配線基板１
に加圧する。このとき、突起電極４の下にあった絶縁性
樹脂３は、この加圧力によって押し出され、突起電極４
と基板配線２の電気的接続を得る。そして、加熱もしく
は紫外線照射によって絶縁性樹脂３を硬化し、半導体素
子５を配線基板１に固着させる。その後、（図４
（ｃ））に示すように、半導体素子５の加圧力が解除さ
れても、基板配線２と突起電極４の電気的接続は絶縁性
樹脂３の収縮力によって維持される。First, as shown in FIG. 4A, an insulating resin 3 for bonding is applied to a surface of a wiring board 1 made of ceramic, glass, glass epoxy, silicon, or the like, having a board wiring 2. Substrate wiring 2 is made of Al, Cu, Cr-Au
After the metal for the substrate wiring is formed by a sputtering method or an evaporation method, the metal for the substrate wiring is etched by a photolithography technique or formed by using a printing technique. The insulating resin 3 is a resin such as an ultraviolet-curing or thermosetting epoxy, silicone, or acrylic resin. Next, as shown in FIG. 4 (b), the projecting electrode 4 of the semiconductor element 5 is made to coincide with the substrate wiring 3, and the projecting electrode 4 is pressed against the substrate wiring 2 from the back side of the semiconductor element 5. Press. Next, the semiconductor element 5 is connected to the wiring board 1.
Press. At this time, the insulating resin 3 under the protruding electrode 4 is extruded by this pressing force, and
And an electrical connection of the substrate wiring 2 is obtained. Then, the insulating resin 3 is cured by heating or irradiation with ultraviolet rays, and the semiconductor element 5 is fixed to the wiring board 1. Then, (FIG. 4
As shown in (c), even when the pressing force of the semiconductor element 5 is released, the electrical connection between the substrate wiring 2 and the protruding electrode 4 is maintained by the contracting force of the insulating resin 3.

【０００４】突起電極４と基板配線２の接続原理を（図
５）で説明する。前述の従来例（図４）の突起電極４と
基板配線２の接続部を（図５）に示す。絶縁性樹脂３の
収縮力Ｆ3は突起電極の個数分に分配され、分配された
力ｆ3は各突起電極の基板配線２と突起電極４に印加さ
れる。突起電極４と基板配線２の電気的接続はこの力ｆ
3によって維持される。したがって、高消費電力の半導
体素子を駆動している場合には、半導体素子５が発熱
し、温度が上昇するにつれて絶縁性樹脂３の収縮力が弱
まる。さらに温度が上昇すると、絶縁性樹脂３は膨張し
て突起電極４と基板配線１との間に間隔生じ、電気的接
続がとれなくなる。The principle of connection between the protruding electrodes 4 and the substrate wiring 2 will be described with reference to FIG. FIG. 5 shows a connection portion between the protruding electrode 4 and the substrate wiring 2 in the above-described conventional example (FIG. 4). The contracting force F3 of the insulating resin 3 is distributed by the number of the protruding electrodes, and the distributed force f3 is applied to the substrate wiring 2 and the protruding electrode 4 of each protruding electrode. The electrical connection between the protruding electrode 4 and the substrate wiring 2 is caused by this force f
Maintained by three. Therefore, when driving a semiconductor element with high power consumption, the semiconductor element 5 generates heat, and the shrinking force of the insulating resin 3 weakens as the temperature increases. When the temperature further rises, the insulating resin 3 expands and a space is formed between the protruding electrode 4 and the substrate wiring 1, so that electrical connection cannot be established.

【０００５】[0005]

【発明が解決しようとする課題】以上の様に、従来の技
術では半導体素子の突起電極と基板配線の接続に紫外線
硬化型或いは、熱硬化型の絶縁性樹脂を用いる方式であ
るため、次のような課題がある。As described above, in the prior art, an ultraviolet-curing or thermosetting insulating resin is used to connect the protruding electrode of the semiconductor element to the substrate wiring. There is such a problem.

【０００６】（１）絶縁性樹脂の塗布用の設備、絶縁性
樹脂の硬化用の設備、絶縁性樹脂材料が必要となり、コ
ストが著しく高い。(1) Equipment for applying the insulating resin, equipment for curing the insulating resin, and an insulating resin material are required, and the cost is extremely high.

【０００７】（２）絶縁性樹脂の塗布及び硬化工程時間
が必要であり、生産性が低い。 （３）高温環境での使用時、または、高発熱の半導体素
子の使用時では、絶縁性樹脂が熱的影響を受けて膨張す
るため、突起電極と基板配線の間に間隔が生じ、電気的
な接続不良が生じる。(2) The time for applying and curing the insulating resin is required, and the productivity is low. (3) When used in a high-temperature environment or when using a semiconductor device that generates a large amount of heat, the insulating resin expands under the influence of heat, so that a space is generated between the protruding electrodes and the wiring on the substrate. Poor connection occurs.

【０００８】（４）高温かつ高湿の使用環境において、
絶縁性樹脂は吸湿し易く、絶縁性樹脂が吸湿すると絶縁
性樹脂の収縮力が低下するため、電気的な接続不良が生
じる。(4) In a high-temperature and high-humidity use environment,
The insulating resin easily absorbs moisture, and when the insulating resin absorbs moisture, the contraction force of the insulating resin is reduced, resulting in poor electrical connection.

【０００９】（５）半導体素子が絶縁性樹脂の収縮力に
よって、反りを生じるため、半導体素子内の配線のマイ
グレーション等による半導体素子破壊が生じ易い。(5) Since the semiconductor element is warped by the contraction force of the insulating resin, the semiconductor element is likely to be destroyed due to migration of wiring in the semiconductor element.

【００１０】（６）使用時の温度差が激しい場合には、
配線基板材質と半導体素子材料との熱膨張係数差によっ
て熱応力が生じ、突起電極と基板配線との接続不良や、
半導体素子の破壊が生じ易い。(6) When the temperature difference during use is severe,
Thermal stress occurs due to the difference in thermal expansion coefficient between the wiring board material and the semiconductor element material, resulting in poor connection between the protruding electrodes and the board wiring,
The semiconductor element is easily broken.

【００１１】[0011]

【課題を解決するための手段】本発明は、上記問題点を
解決するために、半導体素子と配線基板間に絶縁性樹脂
を介入させない下記構造および製造方法を提供するもの
である。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides the following structure and manufacturing method in which an insulating resin is not interposed between a semiconductor element and a wiring board.

【００１２】本発明は、半導体素子の電極上に具備され
た突起電極と、配線基板上に具備された電極とを合致さ
せた半導体装置において、配線基板上の電極を圧延性を
有する材料で構成し、配線基板上の電極下に突起電極よ
り柔らかい絶縁膜を配置し、突起電極と配線基板上の電
極が合致する部分の、圧延性を有する電極と突起電極よ
り柔らかい絶縁膜が凹状に変形し、凹状の部分に突起電
極が合致していることにより、突起電極と配線基板上の
電極とが電気的に接続しているとともに、前記半導体素
子が機械的に前記配線基板に固定される構造の半導体装
置とする。According to the present invention, in a semiconductor device in which a protruding electrode provided on an electrode of a semiconductor element is matched with an electrode provided on a wiring board, the electrode on the wiring board is made of a material having rollability. Then, an insulating film softer than the protruding electrode is arranged below the electrode on the wiring board, and the insulating film softer than the rollable electrode and the protruding electrode in a portion where the protruding electrode and the electrode on the wiring board match is deformed into a concave shape. Since the projection electrode matches the concave portion, the projection electrode and the electrode on the wiring board are electrically connected, and the semiconductor element is mechanically fixed to the wiring board. A semiconductor device.

【００１３】本発明の方法は、圧延性電極の下部に突起
電極よりも柔らかい絶縁膜を有した配線基板の圧延性電
極と半導体素子の突起電極を一致させ、半導体素子を配
線基板に加圧することにより、絶縁膜上の圧延性電極と
絶縁膜を凹状に変形させ、突起電極を凹状の部分に合致
させることにより、突起電極と絶縁膜上の圧延性電極と
の電気的接続を得、且つ、半導体素子を機械的に配線基
板に固定することを特徴とする半導体装置の製造方法で
ある。According to the method of the present invention, a rollable electrode of a wiring substrate having an insulating film softer than a protruding electrode below a rollable electrode is made to coincide with a protruding electrode of a semiconductor element, and the semiconductor element is pressed onto the wiring substrate. Thereby, the rollable electrode on the insulating film and the insulating film are deformed in a concave shape, and the bump electrode is matched with the concave portion, thereby obtaining an electrical connection between the bump electrode and the rollable electrode on the insulating film, and A method for manufacturing a semiconductor device, wherein a semiconductor element is mechanically fixed to a wiring board.

【００１４】[0014]

【作用】本発明の半導体装置とその製造方法によれば、
基板電極及び絶縁膜が凹状に変形した部分の絶縁膜の水
平方向の弾性回復力によって、突起電極と基板電極との
電気的接続と、半導体素子と配線基板の機械的接続が得
られているため、接着用の絶縁性樹脂が不要である。以
上の事から、以下に示す作用がある。According to the semiconductor device and the method of manufacturing the same of the present invention,
The electrical connection between the protruding electrode and the substrate electrode and the mechanical connection between the semiconductor element and the wiring board are obtained by the horizontal elastic recovery force of the insulating film at the portion where the substrate electrode and the insulating film are deformed in a concave shape. In addition, no insulating resin for bonding is required. From the above, the following effects are obtained.

【００１５】（１）接着用の絶縁性樹脂を用いないた
め、絶縁性樹脂の塗布および硬化の工程が不要である。(1) Since an insulating resin for bonding is not used, the steps of applying and curing the insulating resin are not required.

【００１６】（２）半導体素子と配線基板との間に接着
用の絶縁性樹脂を介入させないため、絶縁性樹脂の膨張
や収縮力の低下による高温時や高湿時の電気的接続不良
が生じない。(2) Since the insulating resin for bonding is not interposed between the semiconductor element and the wiring board, poor electrical connection at high temperature or high humidity occurs due to a decrease in expansion or contraction force of the insulating resin. Absent.

【００１７】（３）絶縁性樹脂の収縮力による半導体素
子の反りが生じないため、半導体素子内の配線の耐マイ
グレーション性が向上する。(3) Since the warpage of the semiconductor element due to the contraction force of the insulating resin does not occur, the migration resistance of the wiring in the semiconductor element is improved.

【００１８】（４）使用時の温度差が激しい場合に問題
となる、配線基板材質と半導体素子材料との熱膨張係数
差によって生じる熱応力は、凹状に変形した柔らかい絶
縁膜の部分で緩和され、半導体素子にあたえる応力が非
常に小さいため、高信頼性である。(4) The thermal stress caused by the difference in the coefficient of thermal expansion between the material of the wiring board and the material of the semiconductor element, which is a problem when the temperature difference during use is large, is alleviated by the concave portion of the soft insulating film deformed. In addition, since the stress applied to the semiconductor element is very small, high reliability is achieved.

【００１９】[0019]

【実施例】本発明における第一の実施例について、図を
参照にして説明する。（図１）は本発明における半導体
装置およびその製造方法の第一の実施例である。図１に
おいて１１は基板、１２は絶縁膜、１３は基板配線、１
４は圧延性を有する基板電極、１５は突起電極、１６は
半導体素子、１７は加圧ツールである。基板１１は、ガ
ラス、セラミック、ガラスエポキシ、シリコン基板など
である。また、絶縁膜１２は、突起電極１５より柔らか
い、ポリイミドなどの有機絶縁膜やエポキシ、アクリル
系の絶縁性樹脂膜などである。基板配線１３は導電性金
属であり、基板電極１４は、Ａｕ、Ａｌ、Ｃｕ等の圧延
性に優れた金属である。基板電極１４及び絶縁膜１２は
凹状に変形し、凹状部分の絶縁膜１２の水平方向の弾性
回復力によって、突起電極１５と基板電極１４との電気
的接続と、半導体素子と配線基板の機械的接続を得る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a first embodiment of a semiconductor device and a method of manufacturing the same according to the present invention. In FIG. 1, 11 is a substrate, 12 is an insulating film, 13 is a substrate wiring, 1
Reference numeral 4 denotes a substrate electrode having rollability, 15 denotes a protruding electrode, 16 denotes a semiconductor element, and 17 denotes a pressing tool. The substrate 11 is a glass, ceramic, glass epoxy, silicon substrate, or the like. The insulating film 12 is an organic insulating film made of polyimide or the like, which is softer than the bump electrode 15, or an epoxy or acrylic insulating resin film. The substrate wiring 13 is a conductive metal, and the substrate electrode 14 is a metal excellent in rollability, such as Au, Al, or Cu. The substrate electrode 14 and the insulating film 12 are deformed in a concave shape, and the horizontal elastic recovery force of the insulating film 12 in the concave portion causes an electrical connection between the protruding electrode 15 and the substrate electrode 14 and a mechanical connection between the semiconductor element and the wiring board. Get a connection.

【００２０】本発明の半導体装置の製造方法は、まず、
基板１１上に、突起電極１５より柔らかい絶縁膜１２を
形成する。絶縁膜１２は、基板１１上にスピンナー等を
用いて塗布することにより形成する。次に絶縁膜１２上
に、基板配線１３と基板電極１４を形成する。基板配線
１３と基板電極１４は、導電性金属の膜をスパッタリン
グ法や真空蒸着法等を用いて絶縁膜１２上に堆積した
後、フォトリソグラフィー技術を用いて不要な導電性金
属をエッチングすることにより形成する。基板電極１４
とそれに対応する基板配線１３は電気的に接続されてお
り、また、基板電極１４と基板配線１３の材料や形成方
法は同一かつ同時に行ってもよい。そして、（図１
（ａ））に示すように、突起電極１５を有した半導体素
子１６を、突起電極１５と基板電極１４が一致するよう
に基板１１上に設置する。その後、（図１（ｂ））に示
すように、加圧ツールにより半導体素子１６の裏面側か
ら加圧し、突起電極１５と基板電極１４が一致する部分
の基板電極１４と絶縁膜１２を凹状に変形させる。この
時、突起電極１５と基板電極１４の電気的接続が得られ
ると同時に半導体素子を回路基板に固定する。その後、
（図１（ｃ））のように加圧を解除しても基板電極１４
と絶縁膜１２は凹状に変形したままで、突起電極１５と
基板電極１４との接続が維持される。突起電極１５の高
さは５μｍ〜１００μｍ程度である。絶縁膜１２の厚さ
は、突起電極１５が絶縁膜１２を変形させる深さより厚
くなければならないため、５μｍ〜２００μｍ以上の厚
さが必要である。圧延性のある電極は、容易に変形し且
つ断線しない程度の厚さであり、約０．３μｍ〜５μｍ
の厚さが適当である。The method of manufacturing a semiconductor device according to the present invention comprises:
On the substrate 11, an insulating film 12 softer than the protruding electrodes 15 is formed. The insulating film 12 is formed by coating the substrate 11 with a spinner or the like. Next, a substrate wiring 13 and a substrate electrode 14 are formed on the insulating film 12. The substrate wiring 13 and the substrate electrode 14 are formed by depositing a conductive metal film on the insulating film 12 using a sputtering method, a vacuum evaporation method, or the like, and then etching unnecessary conductive metal using a photolithography technique. Form. Substrate electrode 14
And the corresponding substrate wiring 13 are electrically connected, and the materials and forming method of the substrate electrode 14 and the substrate wiring 13 may be the same and may be performed simultaneously. And (FIG. 1
As shown in (a), the semiconductor element 16 having the protruding electrode 15 is placed on the substrate 11 so that the protruding electrode 15 and the substrate electrode 14 coincide. Thereafter, as shown in FIG. 1B, pressure is applied from the back surface side of the semiconductor element 16 by a pressing tool, and the substrate electrode 14 and the insulating film 12 at the portion where the protruding electrode 15 and the substrate electrode 14 coincide are formed in a concave shape. Deform. At this time, the semiconductor element is fixed to the circuit board at the same time as the electrical connection between the protruding electrode 15 and the substrate electrode 14 is obtained. afterwards,
Even if the pressure is released as shown in FIG.
The connection between the protruding electrode 15 and the substrate electrode 14 is maintained while the insulating film 12 and the insulating film 12 remain deformed in a concave shape. The height of the protruding electrode 15 is about 5 μm to 100 μm. The thickness of the insulating film 12 must be greater than the depth at which the protruding electrode 15 deforms the insulating film 12, so that the thickness is 5 μm to 200 μm or more. The rollable electrode has a thickness such that it is easily deformed and does not break, and is about 0.3 μm to 5 μm.
Is appropriate.

【００２１】この半導体装置の突起電極１５と基板電極
１４の接続原理を（図２）を用いて説明する。（図２
（ａ））は、前述した本発明の第一の実施例における半
導体装置の製造工程のなかで、半導体素子１６を加圧し
ている場合（図１（ｂ））における、突起電極１５付近
の力の加わり方を示したものである。半導体素子１６を
加圧している荷重は、突起電極１５、及び、圧延性のあ
る基板電極１４を介して突起電極１５よりも柔らかい絶
縁膜１２に加わる。絶縁膜１２は、突起電極よりも柔ら
かく変形し易いため、凹状に変形する。この時、突起電
極１５から絶縁膜１２に加わる力は、加圧方向に直接加
わる力ｆ2と、絶縁膜１２を水平方向に押し出して変形
させようとする力ｆ1とに分けられる。また、それらの
力の反発力として、絶縁膜１２からの力Ｆ1、Ｆ2が生じ
る。この時、Ｆ2は荷重Ｆ0の反発力にであり、次式が成
り立つ。The principle of connection between the protruding electrode 15 and the substrate electrode 14 of this semiconductor device will be described with reference to FIG. (Figure 2
(A)) shows the force near the protruding electrode 15 when the semiconductor element 16 is pressurized (FIG. 1 (b)) in the manufacturing process of the semiconductor device according to the first embodiment of the present invention. It shows how to join. The load pressing the semiconductor element 16 is applied to the insulating film 12 that is softer than the protruding electrode 15 via the protruding electrode 15 and the rollable substrate electrode 14. Since the insulating film 12 is softer and more easily deformed than the protruding electrode, it is deformed in a concave shape. At this time, the force applied from the protruding electrode 15 to the insulating film 12 is divided into a force f2 directly applied in the pressing direction and a force f1 for pushing the insulating film 12 horizontally to deform it. Further, forces F1 and F2 from the insulating film 12 are generated as repulsive forces of those forces. At this time, F2 is the repulsive force of the load F0, and the following equation is established.

【００２２】 Ｆ1＝ｆ1 Ｆ2＝ｆ2＝Ｆ0 （式１） 加圧前に突起電極１５の下にあった絶縁膜１２は、塑性
変形などにより水平方向に押し出されるため、突起電極
１５付近の絶縁膜１２はやや盛り上がる。そして、絶縁
膜１２にはその変形を回復しようとする水平方向の弾性
回復力Ｆ1が働く。F1 = f1 F2 = f2 = F0 (Equation 1) The insulating film 12 under the bump electrode 15 before pressing is extruded in the horizontal direction due to plastic deformation or the like. 12 rises slightly. Then, a horizontal elastic recovery force F1 acting to recover the deformation acts on the insulating film 12.

【００２３】したがって、加圧解除後（図２（ｂ））
は、Ｆ2＝ｆ2＝Ｆ0＝０であり、Ｆ1、ｆ1だけが突起電
極１５及び絶縁膜１２に加わる。加圧解除後に電気的接
続が維持されるのは、このＦ1、ｆ1の弾性回復力による
ものである。絶縁膜１２をポリイミド膜とした場合、絶
縁膜１２に塑性変形を生じさせるには、突起電極１５に
加える圧力は約１５ｍｇ／μｍ2程度以上である。Therefore, after the pressure is released (FIG. 2B)
Is F2 = f2 = F0 = 0, and only F1 and f1 are applied to the bump electrode 15 and the insulating film 12. The reason why the electrical connection is maintained after the pressure is released is due to the elastic recovery force of F1 and f1. When the insulating film 12 is a polyimide film, the pressure applied to the bump electrode 15 is about 15 mg / μm 2 or more in order to cause the insulating film 12 to undergo plastic deformation.

【００２４】また、（図２）の本発明の一実施例が高温
時においては、突起電極１５や絶縁膜１２は熱膨張によ
り膨張する傾向にあり、前述の絶縁膜１２の弾性回復力
Ｆ1、ｆ1は大きくなる。よって、高温時には、むしろ電
気的接続が維持される傾向にある。したがって、従来例
で記述したような高温時に生じるような絶縁性樹脂の膨
張による接続不良は生じない。In one embodiment of the present invention (FIG. 2), when the temperature is high, the protruding electrodes 15 and the insulating film 12 tend to expand due to thermal expansion, and the elastic recovery force F1, f1 increases. Therefore, at a high temperature, the electrical connection tends to be maintained. Therefore, the connection failure due to the expansion of the insulating resin, which occurs at a high temperature as described in the conventional example, does not occur.

【００２５】なお、（図１）、（図２）に示す突起電極
１５と基板電極１６を、同一金属とし、金属結合させれ
ばより接触抵抗が小さくなり高温での接続信頼性も向上
する。If the protruding electrode 15 and the substrate electrode 16 shown in FIG. 1 and FIG. 2 are made of the same metal and metal-bonded, the contact resistance becomes smaller and the connection reliability at high temperatures is improved.

【００２６】本発明の第二の実施例における突起電極１
５と基板電極１４の接続原理を示した断面図を（図３）
に示す。本発明の第二の実施例は、突起電極１５の形状
を円柱形もしくは多角柱形で構成し、（図３）に示すよ
うに、突起電極１５の断面構造を台形の構成にし、台形
の半導体素子１６側の上辺の長さよりも配線電極１４側
の底辺の長さの方が長くなるような構成にするものであ
る。第一の実施例の場合に凹形に変形させた絶縁膜１２
は、第二の実施例の場合には、突起電極１５の形状に沿
うように台形に変形し、絶縁膜１２の弾性回復力Ｆ1は
水平方向のみでなくやや基板１１側の方向に加わる。し
たがって、第二の実施例においては、突起電極１５が上
方に抜けようとする力が働いた場合の抵抗力は、突起電
極１５と基板電極１４の摩擦力だけでなく、さらに絶縁
膜１２の垂直方向の弾性回復力が加わる。つまり、半導
体素子１６が基板１１に固定される機会的強度が強くな
る。The bump electrode 1 according to the second embodiment of the present invention
5 is a sectional view showing the principle of connection between the substrate electrode 14 and the substrate electrode 14 (FIG. 3).
Shown in In the second embodiment of the present invention, the projecting electrode 15 is formed in a columnar or polygonal column shape, and the sectional structure of the projecting electrode 15 is made trapezoidal as shown in FIG. The configuration is such that the length of the bottom side on the wiring electrode 14 side is longer than the length of the upper side on the element 16 side. Insulating film 12 deformed concavely in the case of the first embodiment
In the case of the second embodiment, is deformed into a trapezoid so as to follow the shape of the bump electrode 15, and the elastic recovery force F1 of the insulating film 12 is applied not only in the horizontal direction but also slightly in the direction toward the substrate 11. Therefore, in the second embodiment, the resistance force when the projecting electrode 15 tries to escape upward acts not only on the frictional force between the projecting electrode 15 and the substrate electrode 14, but also on the vertical direction of the insulating film 12. Direction elastic recovery force is applied. That is, the opportunity strength at which the semiconductor element 16 is fixed to the substrate 11 increases.

【００２７】[0027]

【発明の効果】本発明の半導体装置およびその製造方法
によれば、以下に示す効果がある。According to the semiconductor device and the method of manufacturing the same of the present invention, the following effects can be obtained.

【００２８】（１）接着用の絶縁性樹脂を用いないた
め、絶縁性樹脂の塗布および硬化の工程が不要であり、
且つ、常温で接続されるため加熱工程も不要であり、生
産コストが大幅に低くなり、生産性も著しく向上する。(1) Since an insulating resin for bonding is not used, a step of applying and curing the insulating resin is not required.
Further, since the connection is performed at room temperature, a heating step is not required, so that the production cost is significantly reduced and the productivity is significantly improved.

【００２９】（２）半導体素子と配線基板との間に接着
用の絶縁性樹脂を介入させないため、絶縁性樹脂の膨張
や収縮力の低下による高温時や高湿時の電気的接続不良
が生じない。(2) Since the insulating resin for bonding is not interposed between the semiconductor element and the wiring board, poor electrical connection at high temperature or high humidity occurs due to a decrease in expansion or contraction force of the insulating resin. Absent.

【００３０】（３）絶縁性樹脂の収縮力による半導体素
子の反りが生じないため、半導体素子内の配線の耐マイ
グレーション性が向上する。(3) Since the warpage of the semiconductor element due to the contraction force of the insulating resin does not occur, the migration resistance of the wiring in the semiconductor element is improved.

【００３１】（４）使用時の温度差が激しい場合に問題
となる、配線基板材質と半導体素子材料との熱膨張係数
差によって生じる熱応力は、凹状に変形した柔らかい絶
縁膜の部分で緩和され、半導体素子にあたえる応力が非
常に小さいため、高信頼性である。(4) The thermal stress caused by the difference in the thermal expansion coefficient between the wiring board material and the semiconductor element material, which becomes a problem when the temperature difference during use is large, is relaxed at the portion of the concavely deformed soft insulating film. In addition, since the stress applied to the semiconductor element is very small, high reliability is achieved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の半導体装置とその製造方法の第一の実
施例を示した工程別断面図FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention and a method for manufacturing the same according to a process.

【図２】図１における突起電極と基板電極の接続原理を
示した断面図FIG. 2 is a cross-sectional view showing the principle of connection between a protruding electrode and a substrate electrode in FIG.

【図３】本発明の半導体装置の第二の実施例を示した断
面図FIG. 3 is a sectional view showing a second embodiment of the semiconductor device of the present invention;

【図４】従来の技術を示す半導体装置とその製造方法の
工程別断面図FIG. 4 is a cross-sectional view of a semiconductor device showing a conventional technique and a manufacturing method of the same, for each process.

【図５】図４における突起電極と基板配線の接続原理を
示した断面図FIG. 5 is a sectional view showing the principle of connection between the protruding electrodes and the substrate wiring in FIG. 4;

【符号の説明】[Explanation of symbols]

１１ 基板 １２ 絶縁膜 １３ 基板配線 １４ 基板電極 １５ 突起電極 １６ 半導体素子 １７ 加圧ツール DESCRIPTION OF SYMBOLS 11 Substrate 12 Insulating film 13 Substrate wiring 14 Substrate electrode 15 Protruding electrode 16 Semiconductor element 17 Pressure tool

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 半導体素子の電極上に具備された突起電
極と、配線基板上に具備された電極とを合致させた半導
体装置において、前記配線基板上の電極を圧延性を有す
る材料で構成し、前記配線基板上の電極下に前記突起電
極より柔らかい絶縁膜を配置し、前記突起電極と前記配
線基板上の電極が合致する部分の、前記圧延性を有する
電極と前記突起電極より柔らかい絶縁膜が凹状に変形
し、前記凹状の部分に前記突起電極が合致していること
により、前記突起電極と前記配線基板上の電極とが電気
的に接続しているとともに、前記半導体素子が機械的に
前記配線基板に固定される構造を特徴とする半導体装
置。In a semiconductor device in which a protruding electrode provided on an electrode of a semiconductor element is matched with an electrode provided on a wiring board, the electrode on the wiring board is made of a material having a rolling property. Disposing an insulating film softer than the protruding electrode under the electrode on the wiring substrate, and forming an insulating film softer than the rollable electrode and the protruding electrode in a portion where the protruding electrode and the electrode on the wiring substrate match. There deformed into a concave shape, by being the matching protrusion electrodes in the concave portion, the conjunction between the projection electrodes and the electrodes of the wiring substrate are electrically connected, wherein the semiconductor device is mechanically
Wherein a structure to be fixed to the wiring board. 【請求項２】 配線基板上の電極と突起電極との電気的
接続及び機械的強度が、凹状に変形した絶縁膜の水平方
向の弾性回復力により維持する構造を特徴とする請求項
１記載の半導体装置。2. The structure according to claim 1, wherein the electrical connection and the mechanical strength between the electrode on the wiring board and the protruding electrode are maintained by a horizontal elastic recovery force of the concavely deformed insulating film. Semiconductor device. 【請求項３】 配線基板上の電極を圧延性を有する金属
で構成し、突起電極と前記配線基板上の電極が金属結合
していることを特徴とする請求項１叉は２記載の半導体
装置。3. The semiconductor device according to claim 1, wherein the electrode on the wiring board is made of a metal having rollability, and the protruding electrode and the electrode on the wiring board are metal-bonded. . 【請求項４】 突起電極の形状を円柱形もしくは多角柱
形で構成し、前記突起電極の半導体素子側の面の面積よ
りも前記突起電極の配線基板側の面の面積の方が大きく
なるように構成したことを特徴とする請求項１、２叉は
３記載の半導体装置。4. The shape of the protruding electrode is a column or a polygon, and the area of the surface of the protruding electrode on the wiring substrate side is larger than the area of the surface of the protruding electrode on the semiconductor element side. 4. The semiconductor device according to claim 1, wherein the semiconductor device is configured as follows. 【請求項５】 圧延性電極の下部に突起電極よりも柔ら
かい絶縁膜を有した配線基板の前記圧延性電極と半導体
素子の前記突起電極を一致させ、前記半導体素子を前記
配線基板に加圧することにより、前記絶縁膜上の前記圧
延性電極と前記絶縁膜を凹状に変形させ、前記突起電極
を前記凹状の部分に合致させることにより、前記突起電
極と前記絶縁膜上の前記圧延性電極との電気的接続を
得、且つ、前記半導体素子を機械的に前記配線基板に固
定することを特徴とする半導体装置の製造方法。5. The method according to claim 5, wherein the rollable electrode of the wiring board having an insulating film softer than the protruding electrode below the rollable electrode is aligned with the protruding electrode of the semiconductor element, and the semiconductor element is pressed against the wiring board. By deforming the rollable electrode and the insulating film on the insulating film in a concave shape, and by matching the projecting electrode to the concave portion, the rollable electrode on the insulating film and the rollable electrode on the insulating film A method for manufacturing a semiconductor device, comprising: obtaining electrical connection; and mechanically fixing the semiconductor element to the wiring substrate.
JP4294822A 1992-11-04 1992-11-04 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3052615B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4294822A JP3052615B2 (en) 1992-11-04 1992-11-04 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4294822A JP3052615B2 (en) 1992-11-04 1992-11-04 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH06151505A JPH06151505A (en) 1994-05-31
JP3052615B2 true JP3052615B2 (en) 2000-06-19

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ID=17812703

Family Applications (1)

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Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10498260B2 (en) * 2015-11-13 2019-12-03 Seiko Epson Corporation Electric device, piezoelectric motor, robot, hand, and liquid transport pump

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1443555A3 (en) 1997-01-23 2005-02-23 Seiko Epson Corporation Semiconductor device and method of manufacturing the same
JPH10270496A (en) * 1997-03-27 1998-10-09 Hitachi Ltd Electronic device, information processor, semiconductor device, semiconductor chip, and mounting method thereof
JP3030271B2 (en) 1997-05-19 2000-04-10 富士通株式会社 How to mount semiconductor components
JP4813255B2 (en) * 2006-05-23 2011-11-09 パナソニック株式会社 WIRING BOARD, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE
JP2010027717A (en) * 2008-07-16 2010-02-04 Sharp Corp Production process of semiconductor device and semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10498260B2 (en) * 2015-11-13 2019-12-03 Seiko Epson Corporation Electric device, piezoelectric motor, robot, hand, and liquid transport pump

Also Published As

Publication number Publication date
JPH06151505A (en) 1994-05-31

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