JPH02141442A - Method for anodically bonding silicon wafer and glass substrate - Google Patents
Method for anodically bonding silicon wafer and glass substrateInfo
- Publication number
- JPH02141442A JPH02141442A JP29395688A JP29395688A JPH02141442A JP H02141442 A JPH02141442 A JP H02141442A JP 29395688 A JP29395688 A JP 29395688A JP 29395688 A JP29395688 A JP 29395688A JP H02141442 A JPH02141442 A JP H02141442A
- Authority
- JP
- Japan
- Prior art keywords
- silicon wafer
- conductor plate
- glass substrate
- wafer
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 57
- 239000010703 silicon Substances 0.000 title claims abstract description 57
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 57
- 239000011521 glass Substances 0.000 title claims abstract description 46
- 239000000758 substrate Substances 0.000 title claims abstract description 44
- 238000000034 method Methods 0.000 title claims abstract description 14
- 239000004020 conductor Substances 0.000 claims abstract description 33
- 235000012431 wafers Nutrition 0.000 claims description 48
- 238000010438 heat treatment Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 238000009826 distribution Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 239000005297 pyrex Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は、半導体デバイスの製作におけるシリコンウ
ェハとガラス基板の陽極接合法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an anodic bonding method for silicon wafers and glass substrates in the production of semiconductor devices.
［従来の技術］
第３図は、例えば特公昭５３−２８７４７号公報（Ｄ
しボメランツの発明）に示された接合法を示す構成断面
図である。図において（１）はシリコンウェハ （２〉
はガラス基板、（３）は陽極導体板、（４）は加熱ヒー
タ、（５）は陰極導体板である。[Prior art] Fig. 3 shows, for example, Japanese Patent Publication No. 53-28747 (D
FIG. 3 is a cross-sectional view showing the structure of the joining method disclosed in the invention of Bomerantz. In the figure, (1) is a silicon wafer (2)
is a glass substrate, (3) is an anode conductor plate, (4) is a heater, and (5) is a cathode conductor plate.
従来の半導体デバイス、例えばシリコンのピエゾ抵抗効
果を利用する半導体圧力センサー等は、その製作工程に
おいてシリコンウェハとガラス基板を接合した構造体と
して構成されるが、この構造体の接続方法として、陽極
接合法は極めて有効であることが知られている。シリコ
ンウェハ（１）とガラス基板（２）を加熱ヒータ（４）
で加熱し、シリコンウェハ側を陽極導体板り３）を通し
て陽極とし、ガラス基板側を同じ（陰極導体板り５〉を
通して陰極として直流電圧を印加し、接合する方法が行
われている。Conventional semiconductor devices, such as semiconductor pressure sensors that utilize the piezoresistance effect of silicon, are constructed as a structure in which a silicon wafer and a glass substrate are bonded during the manufacturing process. Legal is known to be extremely effective. Heater (4) heats silicon wafer (1) and glass substrate (2)
The silicon wafer side is passed through the anode conductor plate 3) as an anode, and the glass substrate side is passed through the same cathode conductor plate 5> as the cathode and DC voltage is applied to bond them.
［発明が解決しようとする課題］
上記のような、従来のシリコンウェハとガラス基板の陽
極接合法においては、陰極導体板（５〉をシリコンウェ
ハの中央部に設置した場合、接合の完結後、シリコン−
ガラス接合体のシリコンウエハとガラス基板界面におけ
る残留応力が第５図に示すごとく、その対向する真下で
ピークとなり、シリコンウェハ内での分布が不均一とな
ることである。このような大きな残留応力は、接合体ウ
ェハのハンドリングによる破損及びダイシングによるチ
ップ分割時にしばしばクラックを発生し、歩習まり低下
の原因となるという問題点があった。[Problems to be Solved by the Invention] In the conventional anodic bonding method of a silicon wafer and a glass substrate as described above, when the cathode conductor plate (5) is installed in the center of the silicon wafer, after the bonding is completed, Silicon-
As shown in FIG. 5, the residual stress at the interface between the silicon wafer and the glass substrate of the glass bonded body reaches a peak just below the opposing sides, and the distribution within the silicon wafer becomes non-uniform. Such a large residual stress has the problem that it often causes damage to the bonded wafer during handling and cracks when dividing the bonded wafer into chips by dicing, resulting in a decrease in yield.
この発明は、かかる問題点を解決するためになされたも
ので、シリコンウェハとガラス基板接合時に発生するシ
リコンとガラス界面の残留応力を減少し、かつ均一化し
て結合を達成することを目的とする。This invention was made to solve these problems, and aims to reduce and equalize the residual stress at the interface between silicon and glass that occurs when bonding a silicon wafer and a glass substrate to achieve bonding. .
［課題を解決するための手段］
この発明は、シリコンウェハとガラス基板の陽極接合時
における上記問題点を解決するため、ガラス基板の主面
にシリコンウェハを当接し、このガラス基板の他主面に
陰極導体板を当接し、上記シリコンウェハな陽極、上記
陰極導体板を陰極として、直流電圧を印加すると同時に
加熱し、上記シリコンウェハとガラス基板を接合する陽
極接合法において、上記ガラス基板の他主面に当接した
陰極導体板の当接位置を、シリコンウェハの外周部と対
向する位置に設けて電圧を印可し、接合を達成するよう
にしたものである。[Means for Solving the Problems] In order to solve the above-mentioned problems during anodic bonding of a silicon wafer and a glass substrate, the present invention abuts the silicon wafer on the main surface of the glass substrate, and then contacts the other main surface of the glass substrate. In the anodic bonding method, the silicon wafer is brought into contact with a cathode conductor plate, the silicon wafer is used as an anode, the cathode conductor plate is used as a cathode, and a direct current voltage is applied and the glass substrate is simultaneously heated to bond the silicon wafer and the glass substrate. The contact position of the cathode conductor plate that is in contact with the main surface is provided at a position facing the outer circumference of the silicon wafer, and a voltage is applied to achieve bonding.
［作 用］
この発明における陽極接合法は、ガラス基板の他主面に
当接した陰極導体板の当接位置をシリコンウェハの外周
部と対向する位置に当接して電圧を印可し接合を達成す
ると、その実験結果からシリコンウェハとガラス基板界
面に発生する残留応力を減少させると共に、シリコンウ
ェハ面内での残留応力の分布の均一化を図ることができ
る。[Function] In the anodic bonding method of the present invention, the cathode conductor plate that is in contact with the other main surface of the glass substrate is brought into contact with a position facing the outer periphery of the silicon wafer, and a voltage is applied to achieve bonding. Then, based on the experimental results, it is possible to reduce the residual stress generated at the interface between the silicon wafer and the glass substrate, and to make the distribution of the residual stress uniform within the plane of the silicon wafer.
［実施例］
第１図はこの発明の一実施例を示す構成断面図であり、
シリコンウェハとガラス基板の陽極接合法において、加
熱ヒータク４）上に同ヒータから電気的に絶縁された陽
極導体板（３）を設置し、その上に通常の半導体プロセ
スを経て回路を形成している４インチシリコンウェハ（
１）、または未処理の４インチシリコンウェハ（１）を
載せ、シリコンと熱膨張係数が近似する同サイズのホウ
ケイ酸ガラス基板（２〉（例えばコーニング製商品名：
パイレックスガラス）を重ね、さらにその上に陰極導体
板（５）をシリコンウェハ（１）の外周部と対抗する位
置に設けて、接合されるシリコンウェハ（１）及びガラ
ス基板（２）を接合に必要な所定の温度（例えば４００
〜４５０°Ｃ）に加熱ヒータ（４）で加熱し、陽極導体
板＜３）と陰極導体板（５）の間に、直流電圧（例えば
５００〜１００ＯＶ）を所定時間（例えば１０〜６０分
間）印加し、接合を達成して陽極導体板（３）、及び陰
極導体板〈５〉を取りはずし、シリコンウェハとガラス
基板の接合を完成させる。[Embodiment] FIG. 1 is a cross-sectional view showing an embodiment of the present invention.
In the anodic bonding method of silicon wafers and glass substrates, an anode conductor plate (3) electrically insulated from the heater is placed on top of the heater (4), and a circuit is formed on it through a normal semiconductor process. 4-inch silicon wafer (
1), or place an untreated 4-inch silicon wafer (1) on a borosilicate glass substrate (2) of the same size with a thermal expansion coefficient similar to that of silicon (for example, Corning product name:
The silicon wafer (1) and glass substrate (2) to be bonded are stacked together (Pyrex glass), and a cathode conductor plate (5) is placed on top of the cathode conductor plate (5) at a position opposite to the outer periphery of the silicon wafer (1). the required predetermined temperature (e.g. 400
~450°C) with a heater (4), and apply a DC voltage (e.g. 500 to 100OV) between the anode conductor plate <3) and the cathode conductor plate (5) for a predetermined time (e.g. 10 to 60 minutes). A voltage is applied to achieve bonding, and the anode conductor plate (3) and cathode conductor plate <5> are removed to complete the bonding of the silicon wafer and the glass substrate.
従来のシリコンウェハとガラス基板の陽極接合法におい
ては、陰極導体板（５〉をシリコンウェハの中央部に設
置しているため、接合の完結後、シリコン−ガラス接合
体のシリコンウェハとガラス基板界面における残留応力
が第５図に示すごとく、その対向する真下でピークとな
り、シリコンウェハ内での分布が不均一となっていたが
、この発明では第１図及びその平面図である第２図に示
したように、外周部に４Ｘ４５ｍｍＯ）陰極導体板（５
）を設！した場合、シリコンウェハとガラス基板接合体
のシリコンとガラス界面における残留応力は、その実験
結果から第４図に示すように電極直下ではピークとなる
が、そのピーク幅は、電極幅が細いため狭く、また、電
極直下より離れると急激に減少し、ウェハ面内では小さ
いレベルで残留応力は均一となり、分布が改善され、シ
リコンウェハ〈１〉とガラス基板（２）の接合完了後、
陰極導体板（５〉直下以外では、均一でかつ減少して接
合が達成される。In the conventional anodic bonding method of a silicon wafer and a glass substrate, the cathode conductor plate (5) is installed in the center of the silicon wafer, so that after the bonding is completed, the interface between the silicon wafer and the glass substrate of the silicon-glass bonded body is As shown in Fig. 5, the residual stress in the silicon wafer peaks directly below the opposing stress, and the distribution within the silicon wafer is non-uniform.However, in this invention, the residual stress in Fig. As shown, a 4x45mmO) cathode conductor plate (5
) established! In this case, the residual stress at the silicon-glass interface of the silicon wafer and glass substrate assembly reaches a peak directly below the electrode as shown in Figure 4 from the experimental results, but the peak width is narrow because the electrode width is narrow. In addition, the residual stress decreases rapidly when moving away from directly under the electrode, and within the wafer surface, the residual stress becomes uniform at a small level, and the distribution is improved. After the bonding of the silicon wafer (1) and the glass substrate (2) is completed,
In areas other than directly under the cathode conductor plate (5>), the bonding is uniform and reduced.
［発明の効果］
この発明は、以上説明したように、ガラス基板の他主面
に当接した陰極導体板の当接位置を、シリコンウェハの
外周部と対向する位置に設けて接合を達成することによ
り、シリコンウェハとガラス基板接合体のシリコンとガ
ラス界面における残留応力を減少し、かつ均一化して接
合が達成できる。これは後プロセスにおける同接合体の
クラック及びデバイス特性のバラツキを防止することが
でき、また、同構造体のシリコンデバイスの歩留まりを
改善できる。[Effects of the Invention] As explained above, the present invention achieves bonding by providing the contact position of the cathode conductor plate that is in contact with the other main surface of the glass substrate at a position that faces the outer periphery of the silicon wafer. By doing so, the residual stress at the silicon-glass interface of the silicon wafer and glass substrate assembly can be reduced and uniformly bonded. This can prevent cracks in the bonded body and variations in device characteristics in post-processing, and can also improve the yield of silicon devices of the same structure.
第１図はこの発明の一実施例によるシリコンウェハとガ
ラス基板の陽極接合法を説明する構成断面図、第２図は
その平面図である。第３図は従来のシリコンウェハとガ
ラス基板の陽極接合法を示す構成断面図である。
第４図はこの発明によるシリコンウェハとガラス基板接
合体のシリコンとガラス界面におけるウェハ面内の残留
応力分布図。第５図は従来法によるシリコンウェハとガ
ラス基板接合体のシリコンとガラス界面におけるウェハ
面内の残留応力分布図である。
図において（１）はシリコンウェハ （２）はガラス基
板、（３〉は陰極導体板、（４〉は加熱ヒータ、り５〉
は陰極導体板である。
なお、図中同一符号は同−又は相当部分を示す。FIG. 1 is a cross-sectional view of a structure illustrating an anodic bonding method of a silicon wafer and a glass substrate according to an embodiment of the present invention, and FIG. 2 is a plan view thereof. FIG. 3 is a cross-sectional view showing a conventional anodic bonding method for silicon wafers and glass substrates. FIG. 4 is a residual stress distribution diagram within the wafer plane at the silicon and glass interface of the silicon wafer and glass substrate assembly according to the present invention. FIG. 5 is a residual stress distribution diagram within the wafer plane at the silicon-glass interface of a silicon wafer-glass substrate assembly obtained by a conventional method. In the figure, (1) is the silicon wafer, (2) is the glass substrate, (3> is the cathode conductor plate, (4> is the heater, and 5) is the cathode conductor plate.
is the cathode conductor plate. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
ラス基板の他主面に陰極導体板を当接し、上記シリコン
ウェハを陽極、上記陰極導体板を陰極として、直流電圧
を印加すると同時に加熱し、上記シリコンウェハとガラ
ス基板を接合する陽極接合法において、上記ガラス基板
の他主面に当接した陰極導体板の当接位置を、シリコン
ウェハの外周部と対向する位置に設けて電圧を印加し、
接合を達成することを特徴とするシリコンウェハとガラ
ス基板の陽極接合法。A silicon wafer is brought into contact with the main surface of a glass substrate, a cathode conductor plate is brought into contact with the other main surface of the glass substrate, the silicon wafer is used as an anode, the cathode conductor plate is used as a cathode, and a direct current voltage is applied and heating is performed at the same time, In the anodic bonding method for bonding the silicon wafer and the glass substrate, the contact position of the cathode conductor plate that is in contact with the other main surface of the glass substrate is provided at a position facing the outer periphery of the silicon wafer, and a voltage is applied. ,
An anodic bonding method for silicon wafers and glass substrates, which is characterized by achieving bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63293956A JPH07112939B2 (en) | 1988-11-21 | 1988-11-21 | Anodic bonding method of silicon wafer and glass substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63293956A JPH07112939B2 (en) | 1988-11-21 | 1988-11-21 | Anodic bonding method of silicon wafer and glass substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02141442A true JPH02141442A (en) | 1990-05-30 |
| JPH07112939B2 JPH07112939B2 (en) | 1995-12-06 |
Family
ID=17801360
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63293956A Expired - Fee Related JPH07112939B2 (en) | 1988-11-21 | 1988-11-21 | Anodic bonding method of silicon wafer and glass substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07112939B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5266824A (en) * | 1991-03-15 | 1993-11-30 | Shin-Etsu Handotai Co., Ltd. | SOI semiconductor substrate |
| WO1999016114A1 (en) * | 1997-09-23 | 1999-04-01 | Infineon Technologies Ag | Method for producing a composite part and composite part |
| US5900671A (en) * | 1994-07-12 | 1999-05-04 | Mitsubishi Denki Kabushiki Kaisha | Electronic component including conductor connected to electrode and anodically bonded to insulating coating |
| WO2001092715A1 (en) * | 2000-05-29 | 2001-12-06 | Olivetti Tecnost S.P.A. | Ejection head for aggressive liquids manufactured by anodic bonding |
| US6475326B2 (en) | 2000-12-13 | 2002-11-05 | Applied Materials, Inc. | Anodic bonding of a stack of conductive and glass layers |
| JP2006231039A (en) * | 2005-01-25 | 2006-09-07 | Technoscan:Kk | Walking stick |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63229863A (en) * | 1987-03-19 | 1988-09-26 | Ishizuka Glass Ltd | Method of joining anode |
| JPS63229864A (en) * | 1987-03-19 | 1988-09-26 | Ishizuka Glass Ltd | Method of joining anode |
-
1988
- 1988-11-21 JP JP63293956A patent/JPH07112939B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63229863A (en) * | 1987-03-19 | 1988-09-26 | Ishizuka Glass Ltd | Method of joining anode |
| JPS63229864A (en) * | 1987-03-19 | 1988-09-26 | Ishizuka Glass Ltd | Method of joining anode |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5266824A (en) * | 1991-03-15 | 1993-11-30 | Shin-Etsu Handotai Co., Ltd. | SOI semiconductor substrate |
| US5900671A (en) * | 1994-07-12 | 1999-05-04 | Mitsubishi Denki Kabushiki Kaisha | Electronic component including conductor connected to electrode and anodically bonded to insulating coating |
| US6087201A (en) * | 1994-07-12 | 2000-07-11 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing ball grid array electronic component |
| US6133069A (en) * | 1994-07-12 | 2000-10-17 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing the electronic using the anode junction method |
| US6181009B1 (en) | 1994-07-12 | 2001-01-30 | Mitsubishi Denki Kabushiki Kaisha | Electronic component with a lead frame and insulating coating |
| US6268647B1 (en) | 1994-07-12 | 2001-07-31 | Mitsubishi Denki Kabushiki Kaisha | Electronic component with an insulating coating |
| US6310395B1 (en) | 1994-07-12 | 2001-10-30 | Mitsubishi Denki Kabushiki Kaisha | Electronic component with anodically bonded contact |
| WO1999016114A1 (en) * | 1997-09-23 | 1999-04-01 | Infineon Technologies Ag | Method for producing a composite part and composite part |
| WO2001092715A1 (en) * | 2000-05-29 | 2001-12-06 | Olivetti Tecnost S.P.A. | Ejection head for aggressive liquids manufactured by anodic bonding |
| US6475326B2 (en) | 2000-12-13 | 2002-11-05 | Applied Materials, Inc. | Anodic bonding of a stack of conductive and glass layers |
| US6972154B2 (en) | 2000-12-13 | 2005-12-06 | Applied Materials, Inc. | Anodically bonded device structure |
| JP2006231039A (en) * | 2005-01-25 | 2006-09-07 | Technoscan:Kk | Walking stick |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07112939B2 (en) | 1995-12-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |